[llvm] [AMDGPU] Reject named single register inline asm constraints for wider types (PR #200771)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 19c89251b..df8b4b619 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -19290,7 +19290,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
       // Reject types that do not fit a single 32-bit register: any scalar wider
       // than 32 bits, or a vector that is not exactly 32 bits.
       if (VT.SimpleTy != MVT::Other &&
-          (VT.getSizeInBits() > 32 || (VT.isVector() && VT.getSizeInBits() != 32)))
+          (VT.getSizeInBits() > 32 ||
+           (VT.isVector() && VT.getSizeInBits() != 32)))
         return std::pair(0U, nullptr);
       if (RC && Idx < RC->getNumRegs())
         return std::pair(RC->getRegister(Idx), RC);

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https://github.com/llvm/llvm-project/pull/200771