[llvm] [AMDGPU] Reject named single register inline asm constraints for wider types (PR #200771)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/200771

>From 59a952458ffa54235d2fff8419f5cf99b1f815e2 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 1 Jun 2026 11:46:28 +0200
Subject: [PATCH] [AMDGPU] Reject named single register inline asm constraints
 for wider types

A named single register constraint like `={v0}` was silently accepted for i64 result, binding it to one 32-bit register

Reject scalars larger than 32 bits as well
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |  7 +++++--
 .../GlobalISel/inline-asm-mismatched-size.ll  |  2 --
 .../AMDGPU/inlineasm-mismatched-size-error.ll | 21 +++++++++++++++++++
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f03c5748455ee..df8b4b61956dd 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -19287,8 +19287,11 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
         }
       }
 
-      // Check for lossy scalar/vector conversions.
-      if (VT.isVector() && VT.getSizeInBits() != 32)
+      // Reject types that do not fit a single 32-bit register: any scalar wider
+      // than 32 bits, or a vector that is not exactly 32 bits.
+      if (VT.SimpleTy != MVT::Other &&
+          (VT.getSizeInBits() > 32 ||
+           (VT.isVector() && VT.getSizeInBits() != 32)))
         return std::pair(0U, nullptr);
       if (RC && Idx < RC->getNumRegs())
         return std::pair(RC->getRegister(Idx), RC);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
index 4e0446ac97f7d..7d1913cb36b93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
@@ -53,7 +53,6 @@ define i64 @return_type_is_too_big_scalar() {
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"; def $0", sideeffect attdialect, regdef, implicit-def $vgpr8
   %reg = call i64 asm sideeffect "; def $0", "={v8}" ()
   ret i64 %reg
 }
@@ -74,7 +73,6 @@ define ptr addrspace(1) @return_type_is_too_big_pointer() {
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"; def $0", sideeffect attdialect, regdef, implicit-def $vgpr8
   %reg = call ptr addrspace(1) asm sideeffect "; def $0", "={v8}" ()
   ret ptr addrspace(1) %reg
 }
diff --git a/llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll b/llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
index 7e9d9b6ee4c9b..e3b280f31d62b 100644
--- a/llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
+++ b/llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
@@ -56,6 +56,27 @@ define void @inline_asm_scalar_read_too_narrow() {
   ret void
 }
 
+; A single named register cannot hold a scalar wider than 32 bits; this must be
+; diagnosed instead of silently synthesising the missing high bits.
+
+; ERR: error: could not allocate output register for constraint '{v0}'
+define i64 @inline_asm_i64_in_single_v_def() {
+  %asm = call i64 asm sideeffect "; def $0", "={v0}"()
+  ret i64 %asm
+}
+
+; ERR: error: could not allocate output register for constraint '{s4}'
+define i64 @inline_asm_i64_in_single_s_def() {
+  %asm = call i64 asm sideeffect "; def $0", "={s4}"()
+  ret i64 %asm
+}
+
+; ERR: error: could not allocate input reg for constraint '{v0}'
+define void @inline_asm_i64_in_single_v_use(i64 %val) {
+  call void asm sideeffect "; use $0", "{v0}"(i64 %val)
+  ret void
+}
+
 ; Single registers for vector types that are too wide or too narrow should be
 ; diagnosed.