[llvm] [AMDGPU] Add regression test for wave.reduce constant folding. (PR #198673)

[via llvm-commits]

https://github.com/carlobertolli updated https://github.com/llvm/llvm-project/pull/198673

>From 4f51ded750ea8829bb8bded2e926d73263fcdb2f Mon Sep 17 00:00:00 2001
From: Carlo Bertolli <carlo.bertolli at amd.com>
Date: Tue, 19 May 2026 18:47:24 +0000
Subject: [PATCH] [AMDGPU] Add regression test for wave.reduce constant
 folding.

Ensure wave.reduce.xor, wave.reduce.add, and wave.reduce.sub with
constant operands are not folded to the input value, since their
results depend on the number of active lanes at runtime.

Assisted-by: Cursor (Claude)
---
 .../CodeGen/AMDGPU/wave-reduce-constant.ll    | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/wave-reduce-constant.ll

diff --git a/llvm/test/CodeGen/AMDGPU/wave-reduce-constant.ll b/llvm/test/CodeGen/AMDGPU/wave-reduce-constant.ll
new file mode 100644
index 0000000000000..532481bebbe10
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wave-reduce-constant.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -O0 -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -check-prefix=O0 %s
+
+; Regression tests for wave.reduce intrinsics with constant operands.
+; The -O2 DAGCombine must not fold these to the unreduced input value;
+; the result depends on the number of active lanes at runtime.
+
+; wave.reduce.xor(30) across a full 64-lane wave = 0 (even parity).
+define amdgpu_ps i32 @wave_reduce_xor_constant() {
+; GCN-LABEL: wave_reduce_xor_constant:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_mov_b64 s[0:1], exec
+; GCN-NEXT:    s_bcnt1_i32_b64 s0, s[0:1]
+; GCN-NEXT:    s_and_b32 s0, s0, 1
+; GCN-NEXT:    s_mul_i32 s0, s0, 30
+; GCN-NEXT:    ; return to shader part epilog
+;
+; O0-LABEL: wave_reduce_xor_constant:
+; O0:       ; %bb.0:
+; O0-NEXT:    s_mov_b32 s0, 30
+; O0-NEXT:    s_mov_b64 s[2:3], exec
+; O0-NEXT:    s_bcnt1_i32_b64 s1, s[2:3]
+; O0-NEXT:    s_and_b32 s1, s1, 1
+; O0-NEXT:    s_mul_i32 s0, s0, s1
+; O0-NEXT:    v_mov_b32_e32 v0, s0
+; O0-NEXT:    s_nop 0
+; O0-NEXT:    v_readfirstlane_b32 s0, v0
+; O0-NEXT:    ; return to shader part epilog
+  %r = call i32 @llvm.amdgcn.wave.reduce.xor.i32(i32 30, i32 0)
+  ret i32 %r
+}
+
+; wave.reduce.add(65536) across a full 64-lane wave = 65536 * 64 = 0x400000.
+define amdgpu_ps i32 @wave_reduce_add_constant() {
+; GCN-LABEL: wave_reduce_add_constant:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_mov_b64 s[0:1], exec
+; GCN-NEXT:    s_bcnt1_i32_b64 s0, s[0:1]
+; GCN-NEXT:    s_mul_i32 s0, s0, 0x10000
+; GCN-NEXT:    ; return to shader part epilog
+;
+; O0-LABEL: wave_reduce_add_constant:
+; O0:       ; %bb.0:
+; O0-NEXT:    s_mov_b32 s0, 0x10000
+; O0-NEXT:    s_mov_b64 s[2:3], exec
+; O0-NEXT:    s_bcnt1_i32_b64 s1, s[2:3]
+; O0-NEXT:    s_mul_i32 s0, s0, s1
+; O0-NEXT:    v_mov_b32_e32 v0, s0
+; O0-NEXT:    s_nop 0
+; O0-NEXT:    v_readfirstlane_b32 s0, v0
+; O0-NEXT:    ; return to shader part epilog
+  %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 65536, i32 1)
+  ret i32 %r
+}
+
+declare i32 @llvm.amdgcn.wave.reduce.xor.i32(i32, i32 immarg)
+declare i32 @llvm.amdgcn.wave.reduce.add.i32(i32, i32 immarg)