[llvm] [AMDGPU] Add regression test for wave.reduce constant folding. (PR #198673)

[Quentin Colombet via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -O0 -mtriple=amdgcn-- -mcpu=gfx950 < %s | FileCheck -check-prefix=O0 %s
+
+; Regression tests for wave.reduce intrinsics with constant operands.
+; The -O2 DAGCombine must not fold these to the unreduced input value;
+; the result depends on the number of active lanes at runtime.
+
+; wave.reduce.xor(30) across a full 64-lane wave = 0 (even parity).
+; Reproducer for m035.
+define amdgpu_ps i32 @wave_reduce_xor_constant() {
+; GCN-LABEL: wave_reduce_xor_constant:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_mov_b64 s[0:1], exec
+; GCN-NEXT:    s_bcnt1_i32_b64 s0, s[0:1]
+; GCN-NEXT:    s_and_b32 s0, s0, 1
+; GCN-NEXT:    s_mul_i32 s0, s0, 30
+; GCN-NEXT:    ; return to shader part epilog
+;
+; O0-LABEL: wave_reduce_xor_constant:
+; O0:       ; %bb.0:
+; O0-NEXT:    s_mov_b32 s0, 30
+; O0-NEXT:    s_mov_b64 s[2:3], exec
+; O0-NEXT:    s_bcnt1_i32_b64 s1, s[2:3]
+; O0-NEXT:    s_and_b32 s1, s1, 1
+; O0-NEXT:    s_mul_i32 s0, s0, s1
+; O0-NEXT:    v_mov_b32_e32 v0, s0
+; O0-NEXT:    s_nop 0
+; O0-NEXT:    v_readfirstlane_b32 s0, v0
+; O0-NEXT:    ; return to shader part epilog
+  %r = call i32 @llvm.amdgcn.wave.reduce.xor.i32(i32 30, i32 0)
+  ret i32 %r
+}
+
+; wave.reduce.add(65536) across a full 64-lane wave = 65536 * 64 = 0x400000.
+; Reproducer for m036.
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qcolombet wrote:

You can remove the mention of m036.

https://github.com/llvm/llvm-project/pull/198673