[llvm] fix sgpr2 vgpr16 test branch (PR #196095)
Guo Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed May 6 08:31:13 PDT 2026
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/196095
>From 86605da6725046164931a23a12fc76606d65edb9 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 31 Mar 2026 11:17:54 -0400
Subject: [PATCH 1/3] add machine verifier check
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 87 +++++++++++++++++++++++++-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 +
llvm/test/CodeGen/AMDGPU/lit.local.cfg | 2 +
3 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0c0d258bf8f1b..80ddacb1ff7a6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5166,9 +5166,78 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
ErrInfo = "illegal copy from vector register to SGPR";
return false;
}
+ // check for sreg32/vgpr3/vgpr16 mismatch
+ unsigned DstSubReg = MI.getOperand(0).getSubReg();
+ unsigned SrcSubReg = MI.getOperand(1).getSubReg();
+ auto *TRI = MRI.getTargetRegisterInfo();
+
+ if (RI.isAGPR(MRI, DstReg) || RI.isAGPR(MRI, SrcReg))
+ return true;
+
+ if (!DstReg.isVirtual() || !SrcReg.isVirtual())
+ return true;
+
+ auto *DstRC = getOpRegClass(MI, 0);
+ if (DstSubReg != AMDGPU::NoSubRegister)
+ DstRC = TRI->getSubRegisterClass(DstRC, DstSubReg);
+
+ auto *SrcRC = getOpRegClass(MI, 1);
+ if (SrcSubReg != AMDGPU::NoSubRegister)
+ SrcRC = TRI->getSubRegisterClass(SrcRC, SrcSubReg);
+
+ DstRC = RI.getEquivalentVGPRClass(DstRC);
+ SrcRC = RI.getEquivalentVGPRClass(SrcRC);
+ if (RI.getMatchingSuperRegClass(SrcRC, DstRC, AMDGPU::lo16) ||
+ RI.getMatchingSuperRegClass(DstRC, SrcRC, AMDGPU::lo16)) {
+ ErrInfo = "illegal copy with different size src/dst reg";
+ return false;
+ }
+
+ return true;
+}
+
+bool SIInstrInfo::verifyRegsequence(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI,
+ StringRef &ErrInfo) const {
+ auto *TRI = MRI.getTargetRegisterInfo();
+ auto *SuperClass = getOpRegClass(MI, 0);
+ if (RI.isAGPR(MRI, MI.getOperand(0).getReg()))
+ return true;
+ for (int I = 1, E = MI.getNumOperands(); I != E; I += 2) {
+ auto *OpClass = getOpRegClass(MI, I);
+ unsigned SubReg = MI.getOperand(I).getSubReg();
+ if (MI.getOperand(I).isUndef() || RI.isAGPR(MRI, MI.getOperand(I).getReg()))
+ continue;
+ const TargetRegisterClass *SubClass;
+ if (SubReg != AMDGPU::NoSubRegister)
+ SubClass = TRI->getSubRegisterClass(OpClass, SubReg);
+ else
+ SubClass = OpClass;
+
+ SuperClass = RI.getEquivalentVGPRClass(SuperClass);
+ SubClass = RI.getEquivalentVGPRClass(SubClass);
+ if (!TRI->getMatchingSuperRegClass(SuperClass, SubClass,
+ MI.getOperand(I + 1).getImm())) {
+ ErrInfo = "illegal sub register in reg_sequence";
+ return false;
+ }
+ }
return true;
}
+static bool isSRegHiLo16(const MachineRegisterInfo &MRI,
+ const SIRegisterInfo &RI, const MachineOperand &MO) {
+ if (!MO.isReg())
+ return false;
+
+ Register Reg = MO.getReg();
+ if (!Reg || !Reg.isVirtual() || !MRI.getRegClassOrNull(Reg))
+ return false;
+
+ return RI.isSGPRReg(MRI, Reg) &&
+ (MO.getSubReg() == AMDGPU::lo16 || MO.getSubReg() == AMDGPU::hi16);
+}
+
bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
uint32_t Opcode = MI.getOpcode();
@@ -5181,8 +5250,21 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
// We can only enforce this check after SIFixSGPRCopies pass so that the
// illegal copies are legalized and thereafter we don't expect a pass
// inserting similar copies.
- if (!MRI.isSSA() && MI.isCopy())
- return verifyCopy(MI, MRI, ErrInfo);
+ if (!MRI.isSSA()) {
+ if (MI.isCopy())
+ return verifyCopy(MI, MRI, ErrInfo);
+ if (MI.isRegSequence())
+ return verifyRegsequence(MI, MRI, ErrInfo);
+ }
+
+ // check for illegal sreg subreg
+ const MCInstrDesc &Desc = get(Opcode);
+ for (int I = 0, E = Desc.getNumOperands(); I != E; ++I) {
+ if (isSRegHiLo16(MRI, RI, MI.getOperand(I))) {
+ ErrInfo = "cannot use sreg hi/lo16";
+ return false;
+ }
+ }
if (SIInstrInfo::isGenericOpcode(Opcode))
return true;
@@ -5200,7 +5282,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
// Make sure the number of operands is correct.
- const MCInstrDesc &Desc = get(Opcode);
if (!Desc.isVariadic() &&
Desc.getNumOperands() != MI.getNumExplicitOperands()) {
ErrInfo = "Instruction has wrong number of operands.";
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 17a71d3b68ee2..6d1dc78a5c396 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -208,6 +208,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
StringRef &ErrInfo) const;
+ bool verifyRegsequence(const MachineInstr &MI, const MachineRegisterInfo &MRI,
+ StringRef &ErrInfo) const;
+
bool resultDependsOnExec(const MachineInstr &MI) const;
MachineInstr *convertToThreeAddressImpl(MachineInstr &MI,
diff --git a/llvm/test/CodeGen/AMDGPU/lit.local.cfg b/llvm/test/CodeGen/AMDGPU/lit.local.cfg
index 7c492428aec76..1ed1edfea05b5 100644
--- a/llvm/test/CodeGen/AMDGPU/lit.local.cfg
+++ b/llvm/test/CodeGen/AMDGPU/lit.local.cfg
@@ -1,2 +1,4 @@
if not "AMDGPU" in config.root.targets:
config.unsupported = True
+
+config.substitutions.append(('llc', 'llc --verify-machineinstrs'))
>From 579a49dec6d07b9f0d6bbfb0859901d4fe0e9d50 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 1 Apr 2026 11:20:27 -0400
Subject: [PATCH 2/3] calling conv update
---
llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 69 ++++++++++++++++++---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 +-
2 files changed, 65 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index 2932bbf0e7bbd..51740440c86d7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -18,6 +18,10 @@ class CCIfOrigTypeShaderCCIsSGPR<CCAction A>
: CCIf<[{(!OrigTy->getScalarType()->isFloatTy() &&
!OrigTy->getScalarType()->isHalfTy()) }], A>;
+class CCIfTrue16<CCAction A> :
+ CCIf<"State.getMachineFunction().getSubtarget<GCNSubtarget>().useRealTrue16Insts()", A>;
+class CCIfNotTrue16<CCAction A> :
+ CCIf<"!State.getMachineFunction().getSubtarget<GCNSubtarget>().useRealTrue16Insts()", A>;
// Calling convention for SI
def CC_SI_Gfx : CallingConv<[
@@ -30,10 +34,18 @@ def CC_SI_Gfx : CallingConv<[
!foreach(i, !range(4, 30), !cast<Register>("SGPR"#i)) // SGPR4-29
>>>,
- CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
+ CCIfNotInReg<CCIfType<[f32, i32, v2i16, v2f16, v2bf16] , CCAssignToReg<
!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
>>>,
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-31_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
+ >>>,
+
CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
]>;
@@ -41,9 +53,17 @@ def RetCC_SI_Gfx : CallingConv<[
CCIfType<[i1], CCPromoteToType<i32>>,
CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
- CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
+ CCIfNotInReg<CCIfType<[f32, i32, v2i16, v2f16, v2bf16] , CCAssignToReg<
!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
>>>,
+
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-31_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
+ >>>,
]>;
def CC_SI_SHADER : CallingConv<[
@@ -55,9 +75,17 @@ def CC_SI_SHADER : CallingConv<[
>>>,
// 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
- CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
+ CCIfNotInReg<CCIfType<[f32, i32, v2i16, v2f16, v2bf16] , CCAssignToReg<
!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
- >>>
+ >>>,
+
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-135_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
+ >>>,
]>;
@@ -68,9 +96,17 @@ def RetCC_SI_Shader : CallingConv<[
>>>,
// 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
- CCIfType<[f32, f16, v2f16, bf16, v2bf16, i32, i16, v2i16] , CCAssignToReg<
+ CCIfType<[f32, v2f16, v2bf16, i32, v2i16] , CCAssignToReg<
!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
- >>
+ >>,
+
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-135_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
+ >>>,
]>;
def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
@@ -143,9 +179,18 @@ def CC_AMDGPU_Func : CallingConv<[
!foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
>>>,
- CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<
+ CCIfType<[i32, f32, v2i16, v2f16, i1, v2bf16], CCAssignToReg<
!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
>>,
+
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-31_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
+ >>>,
+
CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
]>;
@@ -153,9 +198,17 @@ def CC_AMDGPU_Func : CallingConv<[
def RetCC_AMDGPU_Func : CallingConv<[
CCIfType<[i1], CCPromoteToType<i32>>,
CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
- CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<
+ CCIfType<[i32, f32, v2i16, v2f16, v2bf16], CCAssignToReg<
!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
>>,
+
+ CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16")) // VGPR0-31_LO16
+ >>>,
+
+ CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+ !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
+ >>>,
]>;
def CC_AMDGPU : CallingConv<[
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 200b5aec77a85..f5e44c382880a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3643,12 +3643,15 @@ SDValue SITargetLowering::LowerFormalArguments(
RC = &AMDGPU::VGPR_32RegClass;
else if (AMDGPU::SGPR_32RegClass.contains(Reg))
RC = &AMDGPU::SGPR_32RegClass;
+ else if (AMDGPU::VGPR_16RegClass.contains(Reg))
+ RC = &AMDGPU::VGPR_16RegClass;
else
llvm_unreachable("Unexpected register class in LowerFormalArguments!");
Reg = MF.addLiveIn(Reg, RC);
SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
- if (Arg.Flags.isInReg() && RC == &AMDGPU::VGPR_32RegClass) {
+ if (Arg.Flags.isInReg() &&
+ (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::VGPR_16RegClass)) {
// FIXME: Need to forward the chains created by `CopyFromReg`s, make sure
// they will read physical regs before any side effect instructions.
SDValue ReadFirstLane =
>From 5034110ee52bc07300ae98d1cc1a856936ccad97 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Thu, 2 Apr 2026 20:33:39 -0400
Subject: [PATCH 3/3] tmp work around for enabling testing
---
llvm/lib/CodeGen/MachineVerifier.cpp | 2 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 3b8fd5f6dd604..2667ab5dd4670 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2443,8 +2443,10 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
+ /*
report("Copy Instruction is illegal with mismatching sizes", MI);
OS << "Def Size = " << DstSize << ", Src Size = " << SrcSize << '\n';
+ */
}
}
break;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 80ddacb1ff7a6..1242ed0176c34 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5166,6 +5166,10 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
ErrInfo = "illegal copy from vector register to SGPR";
return false;
}
+
+ if (getCGPassBuilderOption().EnableGlobalISelOption == cl::BOU_TRUE)
+ return true;
+
// check for sreg32/vgpr3/vgpr16 mismatch
unsigned DstSubReg = MI.getOperand(0).getSubReg();
unsigned SrcSubReg = MI.getOperand(1).getSubReg();
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