[llvm] [AArch64] Improve fixed vector lowering for cttz/ctlz when sve (PR #192427)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,323 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=NEON
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+sve  | FileCheck %s --check-prefix=SVE
+
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paulwalker-arm wrote:

We shouldn't need a new test file.  I'd expect the NEON side to be well tested and for SVE VLS there is sve-fixed-length-bit-counting.ll.  The current ctlz/cttz testing is based on the setOperationAction layout prior to this PR so you only need to change the relevant functions to remove `vscale_range(2,0)` to reflect the custom lowering is no longer gated on 256+ bit SVE:
```
ctlz_v1i64
ctlz_v2i64
cttz_v1i64
cttz_v2i64
```

https://github.com/llvm/llvm-project/pull/192427