[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for cluster_load_async_to_lds (PR #195956)

[via llvm-commits]

https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/195956

None

>From 0aa1094076c5d877dcff50cfea415e8709a9fcaf Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Tue, 5 May 2026 18:30:08 -0400
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for
 cluster_load_async_to_lds

---
 .../AMDGPU/AMDGPURegBankLegalizeRules.cpp     |  6 +++++
 .../llvm.amdgcn.cluster.load.async.to.lds.ll  | 24 ++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index ae8a4c951a7a7..edaf6db3fddca 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1854,6 +1854,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
                     amdgcn_global_store_async_from_lds_b128})
       .Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
 
+  addRulesForIOpcs({amdgcn_cluster_load_async_to_lds_b8,
+                    amdgcn_cluster_load_async_to_lds_b32,
+                    amdgcn_cluster_load_async_to_lds_b64,
+                    amdgcn_cluster_load_async_to_lds_b128})
+      .Any({{}, {{}, {IntrId, VgprP1, VgprP3, Imm, Imm, SgprB32_M0}}});
+
   addRulesForIOpcs({amdgcn_perm_pk16_b4_u4}, StandardB)
       .Uni(B64, {{UniInVgprB64}, {IntrId, Vgpr32, Vgpr32, VgprV2S32}})
       .Div(B64, {{VgprB64}, {IntrId, Vgpr32, Vgpr32, VgprV2S32}});
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
index 34616bde59598..cdbeceeacc71b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
 
 declare void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)
 declare void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)
@@ -308,3 +308,25 @@ entry:
   call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)
   ret void
 }
+
+define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr_sladdr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) inreg %laddr, i32 inreg %mask) {
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr_sladdr:
+; GFX1250-SDAG:       ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v0, 32 :: v_dual_mov_b32 v1, s2
+; GFX1250-SDAG-NEXT:    s_mov_b32 m0, s3
+; GFX1250-SDAG-NEXT:    cluster_load_async_to_lds_b32 v1, v0, s[0:1] offset:16
+; GFX1250-SDAG-NEXT:    s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr_sladdr:
+; GFX1250-GISEL:       ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 32
+; GFX1250-GISEL-NEXT:    s_mov_b32 m0, s3
+; GFX1250-GISEL-NEXT:    cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250-GISEL-NEXT:    s_endpgm
+entry:
+  %gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
+  call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
+  ret void
+}