[llvm] [AMDGPU] Fix some links in the GFX950 documentation (PR #195951)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 14:54:45 PDT 2026
https://github.com/jwanggit86 created https://github.com/llvm/llvm-project/pull/195951
Some links in the GFX950 documentation are incorrect. For example all the links for the operand 'simm16' in SOPK. This patch fixes those problems. As part of the fix, an entry fo simm16 was added to AMDGPUOperandSyntax.rst.
>From b4125c9f9816ab2d13c7d076f95e42633e5864d6 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 5 May 2026 14:48:30 -0700
Subject: [PATCH] [AMDGPU] Fix some links in the GFX950 documentation
Some links in the GFX950 documentation are incorrect. For example
all the links for the operand 'simm16' in SOPK. This patch fixes
those problems. As part of the fix, an entry fo simm16 was added
to AMDGPUOperandSyntax.rst.
---
llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst | 1501 ++++++++++----------------
llvm/docs/AMDGPU/gfx950_operands.rst | 303 ++++--
llvm/docs/AMDGPUOperandSyntax.rst | 10 +
3 files changed, 832 insertions(+), 982 deletions(-)
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
index 726414ff69b64..1c791a39e08dc 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
@@ -687,27 +687,27 @@ SOPK
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_addk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_call_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_i_fork :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_eq_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_eq_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_ge_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_ge_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_gt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_gt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_le_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_le_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_lg_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_lg_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_lt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_cmpk_lt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_7ed651>`
- s_movk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_setreg_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_cc1716>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_02b357>`
- s_setreg_imm32_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_cc1716>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_i_fork :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_eq_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_eq_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_ge_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_ge_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_gt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_gt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_le_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_le_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_lg_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_lg_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_lt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_cmpk_lt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_de962b>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_setreg_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_de962b>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_02b357>`
+ s_setreg_imm32_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_de962b>`, :ref:`literal<amdgpu_synid_gfx950_literal_a3e80c>`
SOPP
----
@@ -717,36 +717,36 @@ SOPP
**INSTRUCTION** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_barrier
- s_branch :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_cdbgsys :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_cdbgsys_and_user :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_cdbgsys_or_user :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_cdbguser :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_execnz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_execz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_scc0 :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_scc1 :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_vccnz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_cbranch_vccz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
- s_decperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_branch :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_cdbgsys :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_cdbgsys_and_user :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_cdbgsys_or_user :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_cdbguser :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_execnz :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_execz :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_scc0 :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_scc1 :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_vccnz :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_cbranch_vccz :ref:`simm16<amdgpu_synid_gfx950_simm16_dff4f4>`
+ s_decperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
s_endpgm
s_endpgm_ordered_ps_done
s_endpgm_saved
s_icache_inv
- s_incperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_nop :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_sendmsg :ref:`simm16<amdgpu_synid_gfx950_simm16_ee8b30>`
- s_sendmsghalt :ref:`simm16<amdgpu_synid_gfx950_simm16_ee8b30>`
- s_set_gpr_idx_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_incperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_nop :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_sendmsg :ref:`simm16<amdgpu_synid_gfx950_simm16_2f6714>`
+ s_sendmsghalt :ref:`simm16<amdgpu_synid_gfx950_simm16_2f6714>`
+ s_set_gpr_idx_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
s_set_gpr_idx_off
- s_set_valu_coexec_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_sethalt :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_setkill :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_setprio :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_sleep :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
- s_trap :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_set_valu_coexec_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_sethalt :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_setkill :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_setprio :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_sleep :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
+ s_trap :ref:`simm16<amdgpu_synid_gfx950_simm16_ad4155>`
s_ttracedata
- s_waitcnt :ref:`simm16<amdgpu_synid_gfx950_simm16_218bea>`
+ s_waitcnt :ref:`simm16<amdgpu_synid_gfx950_simm16_6d9906>`
s_wakeup
VOP1
@@ -754,418 +754,418 @@ VOP1
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_accvgpr_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`src0<amdgpu_synid_gfx950_src0_1027ca>`
- v_accvgpr_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_1027ca>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_accvgpr_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_1027ca>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_ceil_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ **INSTRUCTION** **DST** **SRC** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`src0<amdgpu_synid_gfx950_src0_1027ca>`
+ v_accvgpr_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_1027ca>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_accvgpr_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_1027ca>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_ceil_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
v_clrexcp
- v_cos_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cos_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_bf16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_bf16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_bf8_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_cvt_f32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_fp8_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f64_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_f64_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_cvt_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_pk_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_pk_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_pk_f32_bf8_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_pk_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_pk_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_pk_f32_fp8_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_cvt_u32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_exp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_exp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_exp_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_floor_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_floor_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_floor_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_floor_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fract_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_fract_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_fract_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_fract_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_frexp_exp_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_frexp_mant_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_log_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_log_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_log_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mov_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_mov_b64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mov_b64_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_e30a18>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_bf16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_bf16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_cvt_f32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_cvt_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_pk_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_pk_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_pk_f32_bf8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_pk_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_pk_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_pk_f32_fp8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_cvt_u32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_floor_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_fract_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_frexp_exp_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_frexp_mant_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mov_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_mov_b64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mov_b64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_e30a18>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_nop
- v_nop_dpp :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_nop_sdwa :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_not_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_permlane16_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
- v_permlane32_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
- v_prng_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_prng_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_prng_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_readfirstlane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_516946>`
- v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sin_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sin_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
- v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
- v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
- v_trunc_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_nop_dpp :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_nop_dpp :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_permlane16_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_permlane32_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_prng_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_prng_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_prng_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_readfirstlane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_516946>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_trunc_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
VOP2
----
.. parsed-literal::
- **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_add_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_add_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
- v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_addc_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_and_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
- v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_dot2c_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_dot2c_f32_bf16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`
- v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
- v_fmac_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mac_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_madak_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_39b593>`
- v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_39b593>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_max_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_max_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_i16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_max_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_max_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_max_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_i16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_min_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_lo_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_pk_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sub_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sub_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sub_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_sub_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_sub_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
- v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
- v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
- v_xor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
- v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_add_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_dot2c_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot2c_f32_bf16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_6f0844>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_fmac_f64_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_fd235e>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_6f0844>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mac_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_madak_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_ad4155>`
+ v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_ad4155>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_pk_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sub_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_sub_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`quad_perm<amdgpu_synid_dpp_ctrl>` :ref:`row_shr<amdgpu_synid_dpp_ctrl>` :ref:`row_shl<amdgpu_synid_dpp_ctrl>` :ref:`row_ror<amdgpu_synid_dpp_ctrl>` :ref:`row_bcast<amdgpu_synid_dpp_ctrl>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
VOP3
----
@@ -1175,266 +1175,27 @@ VOP3
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_add3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_add_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
v_add_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_add_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_add_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_595c25>`
v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_and_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_ashr_pk_i8_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_ashr_pk_u8_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_bitop3_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_bitop3_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_clrexcp
- v_cmp_class_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_class_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_class_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_eq_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_eq_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_eq_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_f_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_f_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_f_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_f_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ge_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ge_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ge_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ge_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_gt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_gt_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_gt_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_gt_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_le_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_le_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_le_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_le_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_lg_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lg_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lg_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_lt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_lt_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_lt_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_lt_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ne_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ne_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ne_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ne_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ne_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ne_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_neq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_neq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_neq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_nge_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nge_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nge_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_ngt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ngt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_ngt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_nle_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nle_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nle_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_nlg_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nlg_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nlg_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_nlt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nlt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_nlt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_o_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_o_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_o_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_t_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_t_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_t_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_t_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_t_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_t_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_tru_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_tru_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_tru_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmp_u_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_u_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmp_u_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_class_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_class_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_class_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_eq_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_eq_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_eq_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_f_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_f_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_f_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_f_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ge_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ge_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ge_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ge_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_gt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_gt_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_gt_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_gt_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_le_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_le_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_le_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_le_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_lg_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lg_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lg_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_lt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_lt_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_lt_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_lt_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ne_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ne_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ne_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ne_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ne_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ne_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_neq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_neq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_neq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_nge_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nge_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nge_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_ngt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ngt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_ngt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_nle_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nle_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nle_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_nlg_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nlg_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nlg_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_nlt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nlt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_nlt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_o_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_o_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_o_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_t_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_t_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_t_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_t_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_t_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_t_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_tru_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_tru_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_tru_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cmpx_u_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_u_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cmpx_u_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_595c25>`
- v_cos_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cos_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_cvt_pk_bf16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_pk_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_pk_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
@@ -1448,7 +1209,6 @@ VOP3
v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_cvt_scalef32_2xpk16_bf6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_d52854>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_cvt_scalef32_2xpk16_fp6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_d52854>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_cvt_scalef32_f16_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
@@ -1502,9 +1262,6 @@ VOP3
v_cvt_sr_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_sr_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_cvt_sr_fp8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
@@ -1513,52 +1270,18 @@ VOP3
v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_1db612>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_1db612>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
- v_dot2c_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_exp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_exp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_floor_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_floor_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_floor_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_fma_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_fma_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_fma_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
v_fma_legacy_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_fract_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_fract_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_fract_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_log_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_log_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_lshl_add_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_mac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mad_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_mad_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
@@ -1577,13 +1300,7 @@ VOP3
v_max3_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_max3_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_max3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_max_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_max_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_max_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_max_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_max_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_max_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_max_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_maximum3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
@@ -1599,86 +1316,30 @@ VOP3
v_min3_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_min3_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_min3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_min_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_min_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_min_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
- v_min_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_min_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_min_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_min_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_minimum3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_mov_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_69a144>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e016a1>`
v_msad_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_mul_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mul_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_nop
- v_not_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_or3_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_perm_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_permlane16_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_permlane32_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_prng_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
- v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_readlane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_43aa79>`
- v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_sad_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_sad_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
v_sad_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sin_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sin_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_sub_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_sub_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_sub_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_sub_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_sub_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_sub_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_595c25>`
- v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_595c25>`
- v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
- v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_43aa79>`
v_xad_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
- v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
- v_xor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
VOP3P
-----
@@ -1810,334 +1471,334 @@ VOPC
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_class_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_class_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_eq_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_f_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_f_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_f_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ge_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_gt_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_le_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lg_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lg_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_lt_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ne_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ne_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ne_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ne_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_neq_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_neq_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nge_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nge_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ngt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_ngt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nle_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nle_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nlg_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nlg_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nlt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_nlt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_o_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_o_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_t_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_t_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_t_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_t_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_t_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_t_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_tru_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_tru_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_u_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmp_u_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_class_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_class_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_class_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_class_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_class_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_eq_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_f_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_f_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_f_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_f_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_f_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ge_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_gt_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_le_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_le_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_le_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_le_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_le_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lg_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lg_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_lt_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ne_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ne_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ne_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ne_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_neq_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_neq_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nge_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nge_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ngt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_ngt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nle_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nle_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nlg_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nlg_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nlt_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_nlt_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_o_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_o_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_o_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_o_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_o_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_t_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_t_i16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_t_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_t_i32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_t_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_t_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_t_u16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_t_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_t_u32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_t_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_tru_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_tru_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
v_cmpx_u_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_u_f16_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_u_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
- v_cmpx_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
+ v_cmpx_u_f32_dpp :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0_14b47a>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_14b47a>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>`
v_cmpx_u_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
.. |---| unicode:: U+02014 .. em dash
diff --git a/llvm/docs/AMDGPU/gfx950_operands.rst b/llvm/docs/AMDGPU/gfx950_operands.rst
index 50386b87d2ef8..4107637cbc658 100644
--- a/llvm/docs/AMDGPU/gfx950_operands.rst
+++ b/llvm/docs/AMDGPU/gfx950_operands.rst
@@ -133,23 +133,29 @@ Instruction input.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
-.. _amdgpu_synid_gfx950_literal_81e671:
+.. _amdgpu_synid_gfx950_literal_ad4155:
literal
-------
*Size:* 1 dword.
-*Operands:*
+*Operands:* :ref:`simm16<amdgpu_synid_simm16>`
-.. _amdgpu_synid_gfx950_literal_39b593:
+.. _amdgpu_synid_gfx950_literal_6f0844:
literal
-------
-*Size:* 1 dword.
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
+
+.. _amdgpu_synid_gfx950_literal_a3e80c:
+
+literal
+-------
-*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
.. _amdgpu_synid_gfx950_saddr_13d69a:
@@ -410,61 +416,267 @@ Instruction output.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
-.. _amdgpu_synid_gfx950_simm16_7ed651:
+.. _amdgpu_synid_gfx950_simm16_ad4155:
simm16
------
*Size:* 1 dword.
-*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
+*Operands:* :ref:`simm16<amdgpu_synid_simm16>`
-.. _amdgpu_synid_gfx950_simm16_39b593:
+.. _amdgpu_synid_gfx950_simm16_2f6714:
simm16
------
-*Size:* 1 dword.
-
-*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
-
-.. _amdgpu_synid_gfx950_simm16_3d2a4f:
+A 16-bit message code. The bits of this operand have the following meaning:
+
+ ============ =============================== ===============
+ Bits Description Value Range
+ ============ =============================== ===============
+ 3:0 Message *type*. 0..15
+ 6:4 Optional *operation*. 0..7
+ 7:7 Unused. \-
+ 9:8 Optional *stream*. 0..3
+ 15:10 Unused. \-
+ ============ =============================== ===============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A *sendmsg* value described below.
+
+ ==================================== ====================================================
+ Sendmsg Value Syntax Description
+ ==================================== ====================================================
+ sendmsg(<*type*>) A message identified by its *type*.
+ sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
+ sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
+ with a stream *id*.
+ ==================================== ====================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Each message type supports specific operations:
+
+ ====================== ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ====================== ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_SAVEWAVE 4 \- \- \-
+ MSG_STALL_WAVE_GEN 5 \- \- \-
+ MSG_HALT_WAVES 6 \- \- \-
+ MSG_ORDERED_PS_DONE 7 \- \- \-
+ MSG_EARLY_PRIM_DEALLOC 8 \- \- \-
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_GET_DOORBELL 10 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ====================== ========== ============================== ============ ==========
+
+*Sendmsg* arguments are validated depending on how *type* value is specified:
+
+* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
+* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+
+Examples:
+
+.. parsed-literal::
+
+ // numeric message code
+ msg = 0x10
+ s_sendmsg 0x12
+ s_sendmsg msg + 2
+
+ // sendmsg with strict arguments validation
+ s_sendmsg sendmsg(MSG_INTERRUPT)
+ s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+ s_sendmsg sendmsg(MSG_GS, 2)
+ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+ s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+ s_sendmsg sendmsg(MSG_GET_DOORBELL)
+
+ // sendmsg with validation of value range only
+ msg = 2
+ op = 3
+ stream = 1
+ s_sendmsg sendmsg(msg, op, stream)
+ s_sendmsg sendmsg(2, GS_OP_CUT)
+
+.. _amdgpu_synid_gfx950_simm16_dff4f4:
simm16
------
-*Size:* 1 dword.
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
-*Operands:* :ref:`label<amdgpu_synid_label>`
+This operand may be specified as one of the following:
-.. _amdgpu_synid_gfx950_simm16_ee8b30:
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..32767.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
-simm16
-------
+Examples:
-*Size:* 1 dword.
+.. parsed-literal::
-*Operands:* :ref:`sendmsg<amdgpu_synid_sendmsg>`
+ offset = 30
+ label_1:
+ label_2 = . + 4
-.. _amdgpu_synid_gfx950_simm16_218bea:
+ s_branch 32
+ s_branch offset + 2
+ s_branch label_1
+ s_branch label_2
+ s_branch label_3
+ s_branch label_4
-simm16
-------
+ label_3 = label_2 + 4
+ label_4:
-*Size:* 1 dword.
+.. _amdgpu_synid_gfx950_simm16_de962b:
-*Operands:* :ref:`waitcnt<amdgpu_synid_waitcnt>`
+simm16
+------
-.. _amdgpu_synid_gfx950_simm16_cc1716:
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+ ======= ===================== ============
+ Bits Description Value Range
+ ======= ===================== ============
+ 5:0 Register *id*. 0..63
+ 10:6 First bit *offset*. 0..31
+ 15:11 *Size* in bits. 1..32
+ ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+ ==================================== ============================================================================
+ Hwreg Value Syntax Description
+ ==================================== ============================================================================
+ hwreg({0..63}) All bits of a register indicated by its *id*.
+ hwreg(<*name*>) All bits of a register indicated by its *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
+ ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+ =================== ==========================================
+ Name Description
+ =================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID Id of wave, simd, compute unit, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+ reg = 1
+ offset = 2
+ size = 4
+ hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+ s_getreg_b32 s2, 0x1881
+ s_getreg_b32 s2, hwreg_enc // the same as above
+ s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
+ s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
+
+ s_getreg_b32 s2, hwreg(15)
+ s_getreg_b32 s2, hwreg(51, 1, 31)
+ s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+
+.. _amdgpu_synid_gfx950_simm16_6d9906:
simm16
------
-Instruction output.
+Counts of outstanding instructions to wait for.
-*Size:* 1 dword.
+The bits of this operand have the following meaning:
+
+ ========== ========= ================================================ ============
+ High Bits Low Bits Description Value Range
+ ========== ========= ================================================ ============
+ 15:14 3:0 VM_CNT: vector memory operations count. 0..63
+ \- 6:4 EXP_CNT: export count. 0..7
+ \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
+ ========== ========= ================================================ ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
+
+ ====================== ======================================================================
+ Syntax Description
+ ====================== ======================================================================
+ vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
+ expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+ lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+ vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
+ expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+ lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+ ====================== ======================================================================
+
+These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ vm_cnt = 1
+ exp_cnt = 2
+ lgkm_cnt = 3
+ cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
+
+ s_waitcnt cnt
+ s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
+ s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
+ s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
-*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
+ s_waitcnt vmcnt(1)
+ s_waitcnt expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+ s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
.. _amdgpu_synid_gfx950_soffset_1189ef:
@@ -740,17 +952,6 @@ Instruction input.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
-.. _amdgpu_synid_gfx950_src2_595c25:
-
-src2
-----
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
-
.. _amdgpu_synid_gfx950_src2_6802ce:
src2
@@ -1168,28 +1369,6 @@ Instruction output.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
-.. _amdgpu_synid_gfx950_vdst_718cc4:
-
-vdst
-----
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
-
-.. _amdgpu_synid_gfx950_vdst_a319e6:
-
-vdst
-----
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
-
.. _amdgpu_synid_gfx950_vdst_bdb32f:
vdst
diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index 722290fb72e16..247a10dd222e4 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -745,6 +745,16 @@ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
The value must be in the range 0..0xFFFFF.
+.. _amdgpu_synid_simm16:
+
+simm16
+------
+
+A 16-bit :ref:`integer number<amdgpu_synid_integer_number>`
+or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+The value must be in the range -0x8000..0x7FFF.
+
.. _amdgpu_synid_simm21:
simm21
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