[llvm] [TableGen] Emit Debug code for dynamic bits(eg: instruction operands) in DecoderEmitter (PR #194699)

[Craig Topper via llvm-commits]

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@@ -12,8 +12,7 @@ def MyTarget : Target {
 }
 
 // CHECK-LABEL: case 0:
-// CHECK-NEXT:    if (!Check(S, DecodeRCRegisterClass(MI, Decoder)))
-// CHECK-NEXT:      return MCDisassembler::Fail;
+// CHECK-NEXT:    if (!Check(S, DecodeRCRegisterClass(MI, Decoder))) return dbgFail("op0: bits<0> using DecodeRCRegisterClass");
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topperc wrote:

This creates a unique string in the binary for every variation of "op0: bits<0> using DecodeRCRegisterClass". Can we have more a specialized dbg function that takes an operand number, operand type, and decode function name and builds the message?

https://github.com/llvm/llvm-project/pull/194699