[llvm] [AArch64] Match vector neg(and X, 1) as CMTST (PR #194833)

[David Green via llvm-commits]

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@@ -23207,6 +23207,42 @@ static SDValue performAddTruncShiftCombine(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(ISD::ADD, DL, VT, Trunc, Shift);
 }
 
+static bool isOneVector(SDValue V) {
+  APInt Splat;
+  if (V.getOpcode() == ISD::SPLAT_VECTOR)
+    return ISD::isConstantSplatVector(V.getNode(), Splat) && Splat.isOne();
+
+  if (auto *BV = dyn_cast<BuildVectorSDNode>(V.getNode())) {
+    APInt SplatUndef;
+    unsigned SplatBitSize;
+    bool HasUndefs;
+    unsigned EltSize = V.getValueType().getVectorElementType().getSizeInBits();
+    return BV->isConstantSplat(Splat, SplatUndef, SplatBitSize, HasUndefs,
+                               EltSize, /*IsBigEndian=*/false) &&
+           !HasUndefs && EltSize == SplatBitSize && Splat.isOne();
+  }
+
+  return V.getOpcode() == AArch64ISD::DUP && isOneConstant(V.getOperand(0));
+}
+
+static SDValue performSubNegAndOneCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() != ISD::SUB)
+    return SDValue();
+
+  EVT VT = N->getValueType(0);
+  if (!VT.isFixedLengthVector() || !VT.isInteger())
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davemgreen wrote:

Is the isInteger testing something in particular? You might be able to remove that bit of the check.

https://github.com/llvm/llvm-project/pull/194833