[llvm] Consolidate infrastructure for exanding scalable intrinsics [NFC] (PR #195309)
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llvm-commits at lists.llvm.org
Fri May 1 10:56:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Philip Reames (preames)
<details>
<summary>Changes</summary>
We (by which I mostly mean I) have introduced multiple routines for generating runtime loops to iterate through scalable vectors. Consolidate the implementations to share code, and sink analysis preservation into the lowest level for future reuse.
---
Patch is 247.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195309.diff
15 Files Affected:
- (modified) llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h (+9-3)
- (modified) llvm/lib/Transforms/Utils/BasicBlockUtils.cpp (+27-7)
- (modified) llvm/lib/Transforms/Utils/LoopUtils.cpp (+17-43)
- (modified) llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp (+19-32)
- (modified) llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll (+14-14)
- (modified) llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll (+60-60)
- (modified) llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll (+260-260)
- (modified) llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll (+12-12)
- (modified) llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll (+26-26)
- (modified) llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll (+10-10)
- (modified) llvm/test/Instrumentation/MemorySanitizer/vscale.ll (+14-14)
- (modified) llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll (+1-1)
- (modified) llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-fp-math.ll (+12-12)
- (modified) llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll (+1-1)
- (modified) llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll (+6-6)
``````````diff
diff --git a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
index f9bfff09673f0..b05708e6c8638 100644
--- a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
@@ -568,8 +568,12 @@ inline void SplitBlockAndInsertIfThenElse(Value *Cond, Instruction *SplitBefore,
/// that \p End is assumed > 0, and thus not checked on entry) at \p
/// SplitBefore. Returns the first insert point in the loop body, and the
/// PHINode for the induction variable (i.e. "i" above).
+/// If \p DT and/or \p LI are provided, they are updated to reflect the
+/// new basic blocks.
LLVM_ABI std::pair<Instruction *, Value *>
-SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore);
+SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore,
+ DominatorTree *DT = nullptr,
+ LoopInfo *LI = nullptr);
/// Utility function for performing a given action on each lane of a vector
/// with \p EC elements. To simplify porting legacy code, this defaults to
@@ -581,7 +585,8 @@ SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore);
/// This index *may* be a constant.
LLVM_ABI void SplitBlockAndInsertForEachLane(
ElementCount EC, Type *IndexTy, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func);
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT = nullptr, LoopInfo *LI = nullptr);
/// Utility function for performing a given action on each lane of a vector
/// with \p EVL effective length. EVL is assumed > 0. To simplify porting legacy
@@ -593,7 +598,8 @@ LLVM_ABI void SplitBlockAndInsertForEachLane(
/// index *may* be a constant.
LLVM_ABI void SplitBlockAndInsertForEachLane(
Value *End, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func);
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT = nullptr, LoopInfo *LI = nullptr);
/// Check whether BB is the merge point of a if-region.
/// If so, return the branch instruction that determines which entry into
diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index 425faf57f8b63..c839944f8cc03 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -1680,10 +1680,13 @@ void llvm::SplitBlockAndInsertIfThenElse(
std::pair<Instruction *, Value *>
llvm::SplitBlockAndInsertSimpleForLoop(Value *End,
- BasicBlock::iterator SplitBefore) {
+ BasicBlock::iterator SplitBefore,
+ DominatorTree *DT, LoopInfo *LI) {
BasicBlock *LoopPred = SplitBefore->getParent();
- BasicBlock *LoopBody = SplitBlock(SplitBefore->getParent(), SplitBefore);
- BasicBlock *LoopExit = SplitBlock(SplitBefore->getParent(), SplitBefore);
+ BasicBlock *LoopBody = SplitBlock(SplitBefore->getParent(), SplitBefore,
+ DT, LI, /*MSSAU=*/nullptr, "ec.loop");
+ BasicBlock *LoopExit = SplitBlock(SplitBefore->getParent(), SplitBefore,
+ DT, LI, /*MSSAU=*/nullptr, "ec.exit");
auto *Ty = End->getType();
auto &DL = SplitBefore->getDataLayout();
@@ -1703,12 +1706,27 @@ llvm::SplitBlockAndInsertSimpleForLoop(Value *End,
IV->addIncoming(ConstantInt::get(Ty, 0), LoopPred);
IV->addIncoming(IVNext, LoopBody);
+ // SplitBlock above updated DT/LI for LoopPred -> LoopBody -> LoopExit.
+ // Now update for the backedge LoopBody -> LoopBody.
+ if (DT)
+ DT->applyUpdates({{DominatorTree::Insert, LoopBody, LoopBody}});
+
+ if (LI) {
+ Loop *NewLoop = LI->AllocateLoop();
+ if (Loop *ParentLoop = LI->getLoopFor(LoopPred))
+ ParentLoop->addChildLoop(NewLoop);
+ else
+ LI->addTopLevelLoop(NewLoop);
+ NewLoop->addBasicBlockToLoop(LoopBody, *LI);
+ }
+
return std::make_pair(&*LoopBody->getFirstNonPHIIt(), IV);
}
void llvm::SplitBlockAndInsertForEachLane(
ElementCount EC, Type *IndexTy, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func) {
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT, LoopInfo *LI) {
IRBuilder<> IRB(InsertBefore->getParent(), InsertBefore);
@@ -1716,7 +1734,7 @@ void llvm::SplitBlockAndInsertForEachLane(
Value *NumElements = IRB.CreateElementCount(IndexTy, EC);
auto [BodyIP, Index] =
- SplitBlockAndInsertSimpleForLoop(NumElements, InsertBefore);
+ SplitBlockAndInsertSimpleForLoop(NumElements, InsertBefore, DT, LI);
IRB.SetInsertPoint(BodyIP);
Func(IRB, Index);
@@ -1732,13 +1750,15 @@ void llvm::SplitBlockAndInsertForEachLane(
void llvm::SplitBlockAndInsertForEachLane(
Value *EVL, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func) {
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT, LoopInfo *LI) {
IRBuilder<> IRB(InsertBefore->getParent(), InsertBefore);
Type *Ty = EVL->getType();
if (!isa<ConstantInt>(EVL)) {
- auto [BodyIP, Index] = SplitBlockAndInsertSimpleForLoop(EVL, InsertBefore);
+ auto [BodyIP, Index] =
+ SplitBlockAndInsertSimpleForLoop(EVL, InsertBefore, DT, LI);
IRB.SetInsertPoint(BodyIP);
Func(IRB, Index);
return;
diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
index 03b693974e5fe..e5093a54b2fcd 100644
--- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -1342,58 +1342,32 @@ Value *llvm::expandReductionViaLoop(IRBuilderBase &Builder, Value *Vec,
DominatorTree *DT, LoopInfo *LI) {
auto *VTy = cast<VectorType>(Vec->getType());
Type *EltTy = VTy->getElementType();
- Function *F = Builder.GetInsertBlock()->getParent();
- const DataLayout &DL = F->getDataLayout();
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
Type *IdxTy = DL.getIndexType(EltTy->getContext(), 0);
- unsigned MinElts = VTy->getElementCount().getKnownMinValue();
- Value *NumElts = Builder.CreateVScale(IdxTy);
- NumElts = Builder.CreateMul(NumElts, ConstantInt::get(IdxTy, MinElts));
+ Value *NumElts = Builder.CreateElementCount(IdxTy,
+ VTy->getElementCount());
- BasicBlock *EntryBB = Builder.GetInsertBlock();
- BasicBlock *LoopBB = BasicBlock::Create(F->getContext(), "rdx.loop", F);
- BasicBlock *ExitBB = SplitBlock(EntryBB, Builder.GetInsertPoint(), DT, LI,
- nullptr, "rdx.exit");
+ auto [BodyIP, IV] =
+ SplitBlockAndInsertSimpleForLoop(NumElts, Builder.GetInsertPoint(),
+ DT, LI);
- EntryBB->getTerminator()->eraseFromParent();
- Builder.SetInsertPoint(EntryBB);
- Builder.CreateBr(LoopBB);
+ BasicBlock *LoopBB = BodyIP->getParent();
+ auto *IVPhi = cast<PHINode>(IV);
+ BasicBlock *Preheader =
+ IVPhi->getIncomingBlock(IVPhi->getIncomingBlock(0) == LoopBB);
- Builder.SetInsertPoint(LoopBB);
- PHINode *IV = Builder.CreatePHI(IdxTy, 2, "rdx.iv");
- PHINode *AccPhi = Builder.CreatePHI(EltTy, 2, "rdx.acc");
- IV->addIncoming(ConstantInt::get(IdxTy, 0), EntryBB);
- AccPhi->addIncoming(Acc, EntryBB);
+ PHINode *AccPhi = PHINode::Create(EltTy, 2, "rdx.acc", BodyIP);
+ AccPhi->addIncoming(Acc, Preheader);
+ Builder.SetInsertPoint(BodyIP);
Value *Elt = Builder.CreateExtractElement(Vec, IV);
- Value *Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, AccPhi,
- Elt, "rdx.op");
-
- Value *NextIV =
- Builder.CreateNUWAdd(IV, ConstantInt::get(IdxTy, 1), "rdx.next");
- IV->addIncoming(NextIV, LoopBB);
+ Value *Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode,
+ AccPhi, Elt, "rdx.op");
AccPhi->addIncoming(Res, LoopBB);
- Value *Done = Builder.CreateICmpEQ(NextIV, NumElts, "rdx.done");
- Builder.CreateCondBr(Done, ExitBB, LoopBB);
-
- // SplitBlock above updated DT/LI for EntryBB -> ExitBB. Now update
- // for replacing that edge with EntryBB -> LoopBB -> {ExitBB, LoopBB}.
- if (DT)
- DT->applyUpdates({{DominatorTree::Insert, EntryBB, LoopBB},
- {DominatorTree::Insert, LoopBB, LoopBB},
- {DominatorTree::Insert, LoopBB, ExitBB},
- {DominatorTree::Delete, EntryBB, ExitBB}});
-
- if (LI) {
- Loop *NewLoop = LI->AllocateLoop();
- if (Loop *ParentLoop = LI->getLoopFor(EntryBB))
- ParentLoop->addChildLoop(NewLoop);
- else
- LI->addTopLevelLoop(NewLoop);
- NewLoop->addBasicBlockToLoop(LoopBB, *LI);
- }
-
+ auto *ExitBr = cast<BranchInst>(LoopBB->getTerminator());
+ BasicBlock *ExitBB = ExitBr->getSuccessor(ExitBr->getSuccessor(0) == LoopBB);
Builder.SetInsertPoint(ExitBB, ExitBB->begin());
return Res;
}
diff --git a/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp b/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
index f534acfc70578..ecf1b0ca4a07f 100644
--- a/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
+++ b/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
@@ -8,54 +8,41 @@
#include "llvm/Transforms/Utils/LowerVectorIntrinsics.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#define DEBUG_TYPE "lower-vector-intrinsics"
using namespace llvm;
bool llvm::lowerUnaryVectorIntrinsicAsLoop(Module &M, CallInst *CI) {
- Type *ArgTy = CI->getArgOperand(0)->getType();
- VectorType *VecTy = cast<VectorType>(ArgTy);
+ VectorType *VecTy = cast<VectorType>(CI->getArgOperand(0)->getType());
+ Type *IdxTy = M.getDataLayout().getIndexType(CI->getContext(), 0);
- BasicBlock *PreLoopBB = CI->getParent();
- BasicBlock *PostLoopBB = nullptr;
- Function *ParentFunc = PreLoopBB->getParent();
- LLVMContext &Ctx = PreLoopBB->getContext();
- Type *IdxTy = M.getDataLayout().getIndexType(Ctx, 0);
-
- PostLoopBB = PreLoopBB->splitBasicBlock(CI);
- BasicBlock *LoopBB = BasicBlock::Create(Ctx, "", ParentFunc, PostLoopBB);
- PreLoopBB->getTerminator()->setSuccessor(0, LoopBB);
-
- // Loop preheader
- IRBuilder<> PreLoopBuilder(PreLoopBB->getTerminator());
+ IRBuilder<> Builder(CI);
Value *LoopEnd =
- PreLoopBuilder.CreateElementCount(IdxTy, VecTy->getElementCount());
+ Builder.CreateElementCount(IdxTy, VecTy->getElementCount());
+
+ auto [BodyIP, IV] =
+ SplitBlockAndInsertSimpleForLoop(LoopEnd, CI->getIterator());
- // Loop body
- IRBuilder<> LoopBuilder(LoopBB);
+ BasicBlock *LoopBB = BodyIP->getParent();
+ auto *IVPhi = cast<PHINode>(IV);
+ BasicBlock *Preheader =
+ IVPhi->getIncomingBlock(IVPhi->getIncomingBlock(0) == LoopBB);
- PHINode *LoopIndex = LoopBuilder.CreatePHI(IdxTy, 2);
- LoopIndex->addIncoming(ConstantInt::get(IdxTy, 0U), PreLoopBB);
- PHINode *Vec = LoopBuilder.CreatePHI(VecTy, 2);
- Vec->addIncoming(CI->getArgOperand(0), PreLoopBB);
+ PHINode *Vec = PHINode::Create(VecTy, 2, "", BodyIP);
+ Vec->addIncoming(CI->getArgOperand(0), Preheader);
- Value *Elem = LoopBuilder.CreateExtractElement(Vec, LoopIndex);
+ Builder.SetInsertPoint(BodyIP);
+ Value *Elem = Builder.CreateExtractElement(Vec, IV);
Function *Exp = Intrinsic::getOrInsertDeclaration(&M, CI->getIntrinsicID(),
VecTy->getElementType());
- Value *Res = LoopBuilder.CreateCall(Exp, Elem);
- Value *NewVec = LoopBuilder.CreateInsertElement(Vec, Res, LoopIndex);
+ Value *Res = Builder.CreateCall(Exp, Elem);
+ Value *NewVec = Builder.CreateInsertElement(Vec, Res, IV);
Vec->addIncoming(NewVec, LoopBB);
- Value *One = ConstantInt::get(IdxTy, 1U);
- Value *NextLoopIndex = LoopBuilder.CreateAdd(LoopIndex, One);
- LoopIndex->addIncoming(NextLoopIndex, LoopBB);
-
- Value *ExitCond =
- LoopBuilder.CreateICmp(CmpInst::ICMP_EQ, NextLoopIndex, LoopEnd);
- LoopBuilder.CreateCondBr(ExitCond, PostLoopBB, LoopBB);
-
CI->replaceAllUsesWith(NewVec);
CI->eraseFromParent();
return true;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index a46d039dcf250..edb3c557bf833 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -961,14 +961,14 @@ define float @vreduce_fmul_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: .LBB75_1: # %rdx.loop
+; CHECK-NEXT: .LBB75_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB75_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -981,14 +981,14 @@ define float @vreduce_ord_fmul_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: .LBB76_1: # %rdx.loop
+; CHECK-NEXT: .LBB76_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB76_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmul.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -1001,14 +1001,14 @@ define float @vreduce_fmul_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: .LBB77_1: # %rdx.loop
+; CHECK-NEXT: .LBB77_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB77_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -1021,14 +1021,14 @@ define float @vreduce_ord_fmul_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: .LBB78_1: # %rdx.loop
+; CHECK-NEXT: .LBB78_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB78_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmul.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -1041,14 +1041,14 @@ define float @vreduce_fmul_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-NEXT: .LBB79_1: # %rdx.loop
+; CHECK-NEXT: .LBB79_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v10, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v10
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB79_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red
@@ -1061,14 +1061,14 @@ define double @vreduce_fmul_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: .LBB80_1: # %rdx.loop
+; CHECK-NEXT: .LBB80_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.d fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB80_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fmul.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
@@ -1081,14 +1081,14 @@ define double @vreduce_ord_fmul_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: .LBB81_1: # %rdx.loop
+; CHECK-NEXT: .LBB81_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.d fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB81_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmul.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 5753fbbb5b7d0..93b6034de8d62 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -1710,14 +1710,14 @@ define signext i8 @vreduce_mul_nxv1i8(<vscale x 1 x i8> %v) {
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: .LBB114_1: # %rdx.loop
+; RV32-NEXT: .LBB114_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB114_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srai a0, a0, 24
; RV32-NEXT: ret
@@ -1729,14 +1729,14 @@ define signext i8 @vreduce_mul_nxv1i8(<vscale x 1 x i8> %v) {
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: .LBB114_1: # %rdx.loop
+; RV64-NEXT: .LBB114_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB114_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srai a0, a0, 56
; RV64-NEXT: ret
@@ -1752,14 +1752,14 @@ define signext i8 @vreduce_mul_nxv2i8(<vscale x 2 x i8> %v) {
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV32-NEXT: .LBB115_1: # %rdx.loop
+; RV32-NEXT: .LBB115_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB115_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srai a0, a0, 24
; RV32-NEXT: ret
@@ -1771,14 +1771,14 @@ define signext i8 @vreduce_mul_nxv2i8(<vscale x 2 x i8> %v) {
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64-NEXT: .LBB115_1: # %rdx.loop
+; RV64-NEXT: .LBB115_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsl...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195309
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