[llvm] Consolidate infrastructure for exanding scalable intrinsics [NFC] (PR #195309)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 10:55:44 PDT 2026
https://github.com/preames created https://github.com/llvm/llvm-project/pull/195309
We (by which I mostly mean I) have introduced multiple routines for generating runtime loops to iterate through scalable vectors. Consolidate the implementations to share code, and sink analysis preservation into the lowest level for future reuse.
>From 8c14a1b2750ce688ea382539f2446e1b1d64bd5d Mon Sep 17 00:00:00 2001
From: Philip Reames <listmail at philipreames.com>
Date: Fri, 1 May 2026 10:29:15 -0700
Subject: [PATCH] Consolidate infrastructure for exanding scalable intrinsics
[NFC]
We (by which I mostly mean I) have introduced multiple routines
for generating runtime loops to iterate through scalable vectors.
Consolidate the implementations to share code, and sink analysis
preservation into the lowest level for future reuse.
---
.../llvm/Transforms/Utils/BasicBlockUtils.h | 12 +-
llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 34 +-
llvm/lib/Transforms/Utils/LoopUtils.cpp | 60 +-
.../Utils/LowerVectorIntrinsics.cpp | 51 +-
.../RISCV/rvv/vreductions-fp-sdnode.ll | 28 +-
.../test/CodeGen/RISCV/rvv/vreductions-int.ll | 120 ++--
.../RISCV/asan-rvv-intrinsics.ll | 520 +++++++++---------
.../asan-masked-load-store.ll | 24 +-
.../AddressSanitizer/asan-vp-load-store.ll | 52 +-
.../MemorySanitizer/vector-load-store.ll | 20 +-
.../Instrumentation/MemorySanitizer/vscale.ll | 28 +-
.../AArch64/expand-exp.ll | 2 +-
.../AArch64/expand-fp-math.ll | 24 +-
.../AArch64/expand-log.ll | 2 +-
.../RISCV/expand-fp-math.ll | 12 +-
15 files changed, 488 insertions(+), 501 deletions(-)
diff --git a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
index f9bfff09673f0..b05708e6c8638 100644
--- a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
@@ -568,8 +568,12 @@ inline void SplitBlockAndInsertIfThenElse(Value *Cond, Instruction *SplitBefore,
/// that \p End is assumed > 0, and thus not checked on entry) at \p
/// SplitBefore. Returns the first insert point in the loop body, and the
/// PHINode for the induction variable (i.e. "i" above).
+/// If \p DT and/or \p LI are provided, they are updated to reflect the
+/// new basic blocks.
LLVM_ABI std::pair<Instruction *, Value *>
-SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore);
+SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore,
+ DominatorTree *DT = nullptr,
+ LoopInfo *LI = nullptr);
/// Utility function for performing a given action on each lane of a vector
/// with \p EC elements. To simplify porting legacy code, this defaults to
@@ -581,7 +585,8 @@ SplitBlockAndInsertSimpleForLoop(Value *End, BasicBlock::iterator SplitBefore);
/// This index *may* be a constant.
LLVM_ABI void SplitBlockAndInsertForEachLane(
ElementCount EC, Type *IndexTy, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func);
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT = nullptr, LoopInfo *LI = nullptr);
/// Utility function for performing a given action on each lane of a vector
/// with \p EVL effective length. EVL is assumed > 0. To simplify porting legacy
@@ -593,7 +598,8 @@ LLVM_ABI void SplitBlockAndInsertForEachLane(
/// index *may* be a constant.
LLVM_ABI void SplitBlockAndInsertForEachLane(
Value *End, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func);
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT = nullptr, LoopInfo *LI = nullptr);
/// Check whether BB is the merge point of a if-region.
/// If so, return the branch instruction that determines which entry into
diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index 425faf57f8b63..c839944f8cc03 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -1680,10 +1680,13 @@ void llvm::SplitBlockAndInsertIfThenElse(
std::pair<Instruction *, Value *>
llvm::SplitBlockAndInsertSimpleForLoop(Value *End,
- BasicBlock::iterator SplitBefore) {
+ BasicBlock::iterator SplitBefore,
+ DominatorTree *DT, LoopInfo *LI) {
BasicBlock *LoopPred = SplitBefore->getParent();
- BasicBlock *LoopBody = SplitBlock(SplitBefore->getParent(), SplitBefore);
- BasicBlock *LoopExit = SplitBlock(SplitBefore->getParent(), SplitBefore);
+ BasicBlock *LoopBody = SplitBlock(SplitBefore->getParent(), SplitBefore,
+ DT, LI, /*MSSAU=*/nullptr, "ec.loop");
+ BasicBlock *LoopExit = SplitBlock(SplitBefore->getParent(), SplitBefore,
+ DT, LI, /*MSSAU=*/nullptr, "ec.exit");
auto *Ty = End->getType();
auto &DL = SplitBefore->getDataLayout();
@@ -1703,12 +1706,27 @@ llvm::SplitBlockAndInsertSimpleForLoop(Value *End,
IV->addIncoming(ConstantInt::get(Ty, 0), LoopPred);
IV->addIncoming(IVNext, LoopBody);
+ // SplitBlock above updated DT/LI for LoopPred -> LoopBody -> LoopExit.
+ // Now update for the backedge LoopBody -> LoopBody.
+ if (DT)
+ DT->applyUpdates({{DominatorTree::Insert, LoopBody, LoopBody}});
+
+ if (LI) {
+ Loop *NewLoop = LI->AllocateLoop();
+ if (Loop *ParentLoop = LI->getLoopFor(LoopPred))
+ ParentLoop->addChildLoop(NewLoop);
+ else
+ LI->addTopLevelLoop(NewLoop);
+ NewLoop->addBasicBlockToLoop(LoopBody, *LI);
+ }
+
return std::make_pair(&*LoopBody->getFirstNonPHIIt(), IV);
}
void llvm::SplitBlockAndInsertForEachLane(
ElementCount EC, Type *IndexTy, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func) {
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT, LoopInfo *LI) {
IRBuilder<> IRB(InsertBefore->getParent(), InsertBefore);
@@ -1716,7 +1734,7 @@ void llvm::SplitBlockAndInsertForEachLane(
Value *NumElements = IRB.CreateElementCount(IndexTy, EC);
auto [BodyIP, Index] =
- SplitBlockAndInsertSimpleForLoop(NumElements, InsertBefore);
+ SplitBlockAndInsertSimpleForLoop(NumElements, InsertBefore, DT, LI);
IRB.SetInsertPoint(BodyIP);
Func(IRB, Index);
@@ -1732,13 +1750,15 @@ void llvm::SplitBlockAndInsertForEachLane(
void llvm::SplitBlockAndInsertForEachLane(
Value *EVL, BasicBlock::iterator InsertBefore,
- std::function<void(IRBuilderBase &, Value *)> Func) {
+ std::function<void(IRBuilderBase &, Value *)> Func,
+ DominatorTree *DT, LoopInfo *LI) {
IRBuilder<> IRB(InsertBefore->getParent(), InsertBefore);
Type *Ty = EVL->getType();
if (!isa<ConstantInt>(EVL)) {
- auto [BodyIP, Index] = SplitBlockAndInsertSimpleForLoop(EVL, InsertBefore);
+ auto [BodyIP, Index] =
+ SplitBlockAndInsertSimpleForLoop(EVL, InsertBefore, DT, LI);
IRB.SetInsertPoint(BodyIP);
Func(IRB, Index);
return;
diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
index 03b693974e5fe..e5093a54b2fcd 100644
--- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -1342,58 +1342,32 @@ Value *llvm::expandReductionViaLoop(IRBuilderBase &Builder, Value *Vec,
DominatorTree *DT, LoopInfo *LI) {
auto *VTy = cast<VectorType>(Vec->getType());
Type *EltTy = VTy->getElementType();
- Function *F = Builder.GetInsertBlock()->getParent();
- const DataLayout &DL = F->getDataLayout();
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
Type *IdxTy = DL.getIndexType(EltTy->getContext(), 0);
- unsigned MinElts = VTy->getElementCount().getKnownMinValue();
- Value *NumElts = Builder.CreateVScale(IdxTy);
- NumElts = Builder.CreateMul(NumElts, ConstantInt::get(IdxTy, MinElts));
+ Value *NumElts = Builder.CreateElementCount(IdxTy,
+ VTy->getElementCount());
- BasicBlock *EntryBB = Builder.GetInsertBlock();
- BasicBlock *LoopBB = BasicBlock::Create(F->getContext(), "rdx.loop", F);
- BasicBlock *ExitBB = SplitBlock(EntryBB, Builder.GetInsertPoint(), DT, LI,
- nullptr, "rdx.exit");
+ auto [BodyIP, IV] =
+ SplitBlockAndInsertSimpleForLoop(NumElts, Builder.GetInsertPoint(),
+ DT, LI);
- EntryBB->getTerminator()->eraseFromParent();
- Builder.SetInsertPoint(EntryBB);
- Builder.CreateBr(LoopBB);
+ BasicBlock *LoopBB = BodyIP->getParent();
+ auto *IVPhi = cast<PHINode>(IV);
+ BasicBlock *Preheader =
+ IVPhi->getIncomingBlock(IVPhi->getIncomingBlock(0) == LoopBB);
- Builder.SetInsertPoint(LoopBB);
- PHINode *IV = Builder.CreatePHI(IdxTy, 2, "rdx.iv");
- PHINode *AccPhi = Builder.CreatePHI(EltTy, 2, "rdx.acc");
- IV->addIncoming(ConstantInt::get(IdxTy, 0), EntryBB);
- AccPhi->addIncoming(Acc, EntryBB);
+ PHINode *AccPhi = PHINode::Create(EltTy, 2, "rdx.acc", BodyIP);
+ AccPhi->addIncoming(Acc, Preheader);
+ Builder.SetInsertPoint(BodyIP);
Value *Elt = Builder.CreateExtractElement(Vec, IV);
- Value *Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, AccPhi,
- Elt, "rdx.op");
-
- Value *NextIV =
- Builder.CreateNUWAdd(IV, ConstantInt::get(IdxTy, 1), "rdx.next");
- IV->addIncoming(NextIV, LoopBB);
+ Value *Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode,
+ AccPhi, Elt, "rdx.op");
AccPhi->addIncoming(Res, LoopBB);
- Value *Done = Builder.CreateICmpEQ(NextIV, NumElts, "rdx.done");
- Builder.CreateCondBr(Done, ExitBB, LoopBB);
-
- // SplitBlock above updated DT/LI for EntryBB -> ExitBB. Now update
- // for replacing that edge with EntryBB -> LoopBB -> {ExitBB, LoopBB}.
- if (DT)
- DT->applyUpdates({{DominatorTree::Insert, EntryBB, LoopBB},
- {DominatorTree::Insert, LoopBB, LoopBB},
- {DominatorTree::Insert, LoopBB, ExitBB},
- {DominatorTree::Delete, EntryBB, ExitBB}});
-
- if (LI) {
- Loop *NewLoop = LI->AllocateLoop();
- if (Loop *ParentLoop = LI->getLoopFor(EntryBB))
- ParentLoop->addChildLoop(NewLoop);
- else
- LI->addTopLevelLoop(NewLoop);
- NewLoop->addBasicBlockToLoop(LoopBB, *LI);
- }
-
+ auto *ExitBr = cast<BranchInst>(LoopBB->getTerminator());
+ BasicBlock *ExitBB = ExitBr->getSuccessor(ExitBr->getSuccessor(0) == LoopBB);
Builder.SetInsertPoint(ExitBB, ExitBB->begin());
return Res;
}
diff --git a/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp b/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
index f534acfc70578..ecf1b0ca4a07f 100644
--- a/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
+++ b/llvm/lib/Transforms/Utils/LowerVectorIntrinsics.cpp
@@ -8,54 +8,41 @@
#include "llvm/Transforms/Utils/LowerVectorIntrinsics.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#define DEBUG_TYPE "lower-vector-intrinsics"
using namespace llvm;
bool llvm::lowerUnaryVectorIntrinsicAsLoop(Module &M, CallInst *CI) {
- Type *ArgTy = CI->getArgOperand(0)->getType();
- VectorType *VecTy = cast<VectorType>(ArgTy);
+ VectorType *VecTy = cast<VectorType>(CI->getArgOperand(0)->getType());
+ Type *IdxTy = M.getDataLayout().getIndexType(CI->getContext(), 0);
- BasicBlock *PreLoopBB = CI->getParent();
- BasicBlock *PostLoopBB = nullptr;
- Function *ParentFunc = PreLoopBB->getParent();
- LLVMContext &Ctx = PreLoopBB->getContext();
- Type *IdxTy = M.getDataLayout().getIndexType(Ctx, 0);
-
- PostLoopBB = PreLoopBB->splitBasicBlock(CI);
- BasicBlock *LoopBB = BasicBlock::Create(Ctx, "", ParentFunc, PostLoopBB);
- PreLoopBB->getTerminator()->setSuccessor(0, LoopBB);
-
- // Loop preheader
- IRBuilder<> PreLoopBuilder(PreLoopBB->getTerminator());
+ IRBuilder<> Builder(CI);
Value *LoopEnd =
- PreLoopBuilder.CreateElementCount(IdxTy, VecTy->getElementCount());
+ Builder.CreateElementCount(IdxTy, VecTy->getElementCount());
+
+ auto [BodyIP, IV] =
+ SplitBlockAndInsertSimpleForLoop(LoopEnd, CI->getIterator());
- // Loop body
- IRBuilder<> LoopBuilder(LoopBB);
+ BasicBlock *LoopBB = BodyIP->getParent();
+ auto *IVPhi = cast<PHINode>(IV);
+ BasicBlock *Preheader =
+ IVPhi->getIncomingBlock(IVPhi->getIncomingBlock(0) == LoopBB);
- PHINode *LoopIndex = LoopBuilder.CreatePHI(IdxTy, 2);
- LoopIndex->addIncoming(ConstantInt::get(IdxTy, 0U), PreLoopBB);
- PHINode *Vec = LoopBuilder.CreatePHI(VecTy, 2);
- Vec->addIncoming(CI->getArgOperand(0), PreLoopBB);
+ PHINode *Vec = PHINode::Create(VecTy, 2, "", BodyIP);
+ Vec->addIncoming(CI->getArgOperand(0), Preheader);
- Value *Elem = LoopBuilder.CreateExtractElement(Vec, LoopIndex);
+ Builder.SetInsertPoint(BodyIP);
+ Value *Elem = Builder.CreateExtractElement(Vec, IV);
Function *Exp = Intrinsic::getOrInsertDeclaration(&M, CI->getIntrinsicID(),
VecTy->getElementType());
- Value *Res = LoopBuilder.CreateCall(Exp, Elem);
- Value *NewVec = LoopBuilder.CreateInsertElement(Vec, Res, LoopIndex);
+ Value *Res = Builder.CreateCall(Exp, Elem);
+ Value *NewVec = Builder.CreateInsertElement(Vec, Res, IV);
Vec->addIncoming(NewVec, LoopBB);
- Value *One = ConstantInt::get(IdxTy, 1U);
- Value *NextLoopIndex = LoopBuilder.CreateAdd(LoopIndex, One);
- LoopIndex->addIncoming(NextLoopIndex, LoopBB);
-
- Value *ExitCond =
- LoopBuilder.CreateICmp(CmpInst::ICMP_EQ, NextLoopIndex, LoopEnd);
- LoopBuilder.CreateCondBr(ExitCond, PostLoopBB, LoopBB);
-
CI->replaceAllUsesWith(NewVec);
CI->eraseFromParent();
return true;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index a46d039dcf250..edb3c557bf833 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -961,14 +961,14 @@ define float @vreduce_fmul_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: .LBB75_1: # %rdx.loop
+; CHECK-NEXT: .LBB75_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB75_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -981,14 +981,14 @@ define float @vreduce_ord_fmul_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: .LBB76_1: # %rdx.loop
+; CHECK-NEXT: .LBB76_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB76_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmul.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -1001,14 +1001,14 @@ define float @vreduce_fmul_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: .LBB77_1: # %rdx.loop
+; CHECK-NEXT: .LBB77_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB77_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -1021,14 +1021,14 @@ define float @vreduce_ord_fmul_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: .LBB78_1: # %rdx.loop
+; CHECK-NEXT: .LBB78_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB78_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmul.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -1041,14 +1041,14 @@ define float @vreduce_fmul_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-NEXT: .LBB79_1: # %rdx.loop
+; CHECK-NEXT: .LBB79_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v10, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v10
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.s fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB79_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fmul.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red
@@ -1061,14 +1061,14 @@ define double @vreduce_fmul_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: .LBB80_1: # %rdx.loop
+; CHECK-NEXT: .LBB80_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.d fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB80_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fmul.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
@@ -1081,14 +1081,14 @@ define double @vreduce_ord_fmul_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: .LBB81_1: # %rdx.loop
+; CHECK-NEXT: .LBB81_1: # %ec.loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vslidedown.vx v9, v8, a0
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: fmul.d fa0, fa0, fa5
; CHECK-NEXT: bne a0, a1, .LBB81_1
-; CHECK-NEXT: # %bb.2: # %rdx.exit
+; CHECK-NEXT: # %bb.2: # %ec.exit
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmul.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 5753fbbb5b7d0..93b6034de8d62 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -1710,14 +1710,14 @@ define signext i8 @vreduce_mul_nxv1i8(<vscale x 1 x i8> %v) {
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: .LBB114_1: # %rdx.loop
+; RV32-NEXT: .LBB114_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB114_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srai a0, a0, 24
; RV32-NEXT: ret
@@ -1729,14 +1729,14 @@ define signext i8 @vreduce_mul_nxv1i8(<vscale x 1 x i8> %v) {
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: .LBB114_1: # %rdx.loop
+; RV64-NEXT: .LBB114_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB114_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srai a0, a0, 56
; RV64-NEXT: ret
@@ -1752,14 +1752,14 @@ define signext i8 @vreduce_mul_nxv2i8(<vscale x 2 x i8> %v) {
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV32-NEXT: .LBB115_1: # %rdx.loop
+; RV32-NEXT: .LBB115_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB115_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srai a0, a0, 24
; RV32-NEXT: ret
@@ -1771,14 +1771,14 @@ define signext i8 @vreduce_mul_nxv2i8(<vscale x 2 x i8> %v) {
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64-NEXT: .LBB115_1: # %rdx.loop
+; RV64-NEXT: .LBB115_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB115_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srai a0, a0, 56
; RV64-NEXT: ret
@@ -1794,14 +1794,14 @@ define signext i8 @vreduce_mul_nxv4i8(<vscale x 4 x i8> %v) {
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; RV32-NEXT: .LBB116_1: # %rdx.loop
+; RV32-NEXT: .LBB116_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB116_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srai a0, a0, 24
; RV32-NEXT: ret
@@ -1813,14 +1813,14 @@ define signext i8 @vreduce_mul_nxv4i8(<vscale x 4 x i8> %v) {
; RV64-NEXT: srli a2, a2, 1
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; RV64-NEXT: .LBB116_1: # %rdx.loop
+; RV64-NEXT: .LBB116_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB116_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srai a0, a0, 56
; RV64-NEXT: ret
@@ -1836,14 +1836,14 @@ define signext i16 @vreduce_mul_nxv1i16(<vscale x 1 x i16> %v) {
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: .LBB117_1: # %rdx.loop
+; RV32-NEXT: .LBB117_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB117_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 16
; RV32-NEXT: srai a0, a0, 16
; RV32-NEXT: ret
@@ -1855,14 +1855,14 @@ define signext i16 @vreduce_mul_nxv1i16(<vscale x 1 x i16> %v) {
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: .LBB117_1: # %rdx.loop
+; RV64-NEXT: .LBB117_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB117_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 48
; RV64-NEXT: srai a0, a0, 48
; RV64-NEXT: ret
@@ -1878,14 +1878,14 @@ define signext i16 @vreduce_mul_nxv2i16(<vscale x 2 x i16> %v) {
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV32-NEXT: .LBB118_1: # %rdx.loop
+; RV32-NEXT: .LBB118_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB118_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 16
; RV32-NEXT: srai a0, a0, 16
; RV32-NEXT: ret
@@ -1897,14 +1897,14 @@ define signext i16 @vreduce_mul_nxv2i16(<vscale x 2 x i16> %v) {
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64-NEXT: .LBB118_1: # %rdx.loop
+; RV64-NEXT: .LBB118_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB118_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 48
; RV64-NEXT: srai a0, a0, 48
; RV64-NEXT: ret
@@ -1920,14 +1920,14 @@ define signext i16 @vreduce_mul_nxv4i16(<vscale x 4 x i16> %v) {
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV32-NEXT: .LBB119_1: # %rdx.loop
+; RV32-NEXT: .LBB119_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB119_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 16
; RV32-NEXT: srai a0, a0, 16
; RV32-NEXT: ret
@@ -1939,14 +1939,14 @@ define signext i16 @vreduce_mul_nxv4i16(<vscale x 4 x i16> %v) {
; RV64-NEXT: srli a2, a2, 1
; RV64-NEXT: li a1, 1
; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64-NEXT: .LBB119_1: # %rdx.loop
+; RV64-NEXT: .LBB119_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a0
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB119_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 48
; RV64-NEXT: srai a0, a0, 48
; RV64-NEXT: ret
@@ -1962,14 +1962,14 @@ define signext i32 @vreduce_mul_nxv1i32(<vscale x 1 x i32> %v) {
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: .LBB120_1: # %rdx.loop
+; RV32-NEXT: .LBB120_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a1
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a1, a1, 1
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: bne a1, a2, .LBB120_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv1i32:
@@ -1979,14 +1979,14 @@ define signext i32 @vreduce_mul_nxv1i32(<vscale x 1 x i32> %v) {
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a0, 1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: .LBB120_1: # %rdx.loop
+; RV64-NEXT: .LBB120_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a1
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mulw a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB120_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -2000,14 +2000,14 @@ define signext i32 @vreduce_mul_nxv2i32(<vscale x 2 x i32> %v) {
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: .LBB121_1: # %rdx.loop
+; RV32-NEXT: .LBB121_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a1
; RV32-NEXT: vmv.x.s a3, v9
; RV32-NEXT: addi a1, a1, 1
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: bne a1, a2, .LBB121_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv2i32:
@@ -2017,14 +2017,14 @@ define signext i32 @vreduce_mul_nxv2i32(<vscale x 2 x i32> %v) {
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a0, 1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: .LBB121_1: # %rdx.loop
+; RV64-NEXT: .LBB121_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a1
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mulw a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB121_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -2039,7 +2039,7 @@ define signext i32 @vreduce_mul_nxv4i32(<vscale x 4 x i32> %v) {
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a0, 1
-; RV32-NEXT: .LBB122_1: # %rdx.loop
+; RV32-NEXT: .LBB122_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vslidedown.vx v9, v8, a1
@@ -2047,7 +2047,7 @@ define signext i32 @vreduce_mul_nxv4i32(<vscale x 4 x i32> %v) {
; RV32-NEXT: addi a1, a1, 1
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: bne a1, a2, .LBB122_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv4i32:
@@ -2058,7 +2058,7 @@ define signext i32 @vreduce_mul_nxv4i32(<vscale x 4 x i32> %v) {
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a0, 1
-; RV64-NEXT: .LBB122_1: # %rdx.loop
+; RV64-NEXT: .LBB122_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vx v9, v8, a1
@@ -2066,7 +2066,7 @@ define signext i32 @vreduce_mul_nxv4i32(<vscale x 4 x i32> %v) {
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mulw a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB122_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -2082,7 +2082,7 @@ define i64 @vreduce_mul_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-NEXT: srli a3, a3, 3
; RV32-NEXT: li a4, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT: .LBB123_1: # %rdx.loop
+; RV32-NEXT: .LBB123_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v9, v8, a2
; RV32-NEXT: addi a2, a2, 1
@@ -2096,7 +2096,7 @@ define i64 @vreduce_mul_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-NEXT: add a1, a1, a6
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: bne a2, a3, .LBB123_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv1i64:
@@ -2106,14 +2106,14 @@ define i64 @vreduce_mul_nxv1i64(<vscale x 1 x i64> %v) {
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a0, 1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT: .LBB123_1: # %rdx.loop
+; RV64-NEXT: .LBB123_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v9, v8, a1
; RV64-NEXT: vmv.x.s a3, v9
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB123_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.mul.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -2130,7 +2130,7 @@ define i64 @vreduce_mul_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-NEXT: li a0, 1
; RV32-NEXT: srli a3, a3, 3
; RV32-NEXT: li a4, 32
-; RV32-NEXT: .LBB124_1: # %rdx.loop
+; RV32-NEXT: .LBB124_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vx v9, v8, a2
@@ -2145,7 +2145,7 @@ define i64 @vreduce_mul_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-NEXT: add a1, a1, a6
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: bne a2, a3, .LBB124_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv2i64:
@@ -2156,7 +2156,7 @@ define i64 @vreduce_mul_nxv2i64(<vscale x 2 x i64> %v) {
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a0, 1
-; RV64-NEXT: .LBB124_1: # %rdx.loop
+; RV64-NEXT: .LBB124_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vx v9, v8, a1
@@ -2164,7 +2164,7 @@ define i64 @vreduce_mul_nxv2i64(<vscale x 2 x i64> %v) {
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB124_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.mul.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -2183,7 +2183,7 @@ define i64 @vreduce_mul_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: srli a3, a3, 3
; RV32-NEXT: li a4, 32
-; RV32-NEXT: .LBB125_1: # %rdx.loop
+; RV32-NEXT: .LBB125_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vx v9, v8, a2
@@ -2198,7 +2198,7 @@ define i64 @vreduce_mul_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-NEXT: add a1, a1, a6
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: bne a2, a3, .LBB125_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv4i64:
@@ -2211,7 +2211,7 @@ define i64 @vreduce_mul_nxv4i64(<vscale x 4 x i64> %v) {
; RV64-NEXT: vmul.vv v8, v8, v9
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: li a0, 1
-; RV64-NEXT: .LBB125_1: # %rdx.loop
+; RV64-NEXT: .LBB125_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vx v9, v8, a1
@@ -2219,7 +2219,7 @@ define i64 @vreduce_mul_nxv4i64(<vscale x 4 x i64> %v) {
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mul a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB125_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -2235,14 +2235,14 @@ define signext i32 @vreduce_mul_nxv6i32(<vscale x 6 x i32> %v) {
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetivli zero, 1, e32, m4, ta, ma
-; RV32-NEXT: .LBB126_1: # %rdx.loop
+; RV32-NEXT: .LBB126_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vslidedown.vx v12, v8, a1
; RV32-NEXT: vmv.x.s a3, v12
; RV32-NEXT: addi a1, a1, 1
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: bne a1, a2, .LBB126_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv6i32:
@@ -2253,14 +2253,14 @@ define signext i32 @vreduce_mul_nxv6i32(<vscale x 6 x i32> %v) {
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: li a0, 1
; RV64-NEXT: vsetivli zero, 1, e32, m4, ta, ma
-; RV64-NEXT: .LBB126_1: # %rdx.loop
+; RV64-NEXT: .LBB126_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vslidedown.vx v12, v8, a1
; RV64-NEXT: vmv.x.s a3, v12
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mulw a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB126_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %v)
ret i32 %red
@@ -2278,7 +2278,7 @@ define signext i31 @vreduce_mul_nxv8i31(<vscale x 8 x i31> %v) {
; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: li a1, 1
-; RV32-NEXT: .LBB127_1: # %rdx.loop
+; RV32-NEXT: .LBB127_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vslidedown.vx v9, v8, a0
@@ -2286,7 +2286,7 @@ define signext i31 @vreduce_mul_nxv8i31(<vscale x 8 x i31> %v) {
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: bne a0, a2, .LBB127_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: slli a0, a1, 1
; RV32-NEXT: srai a0, a0, 1
; RV32-NEXT: ret
@@ -2301,7 +2301,7 @@ define signext i31 @vreduce_mul_nxv8i31(<vscale x 8 x i31> %v) {
; RV64-NEXT: vmul.vv v8, v8, v9
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: li a1, 1
-; RV64-NEXT: .LBB127_1: # %rdx.loop
+; RV64-NEXT: .LBB127_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vx v9, v8, a0
@@ -2309,7 +2309,7 @@ define signext i31 @vreduce_mul_nxv8i31(<vscale x 8 x i31> %v) {
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: mul a1, a1, a3
; RV64-NEXT: bne a0, a2, .LBB127_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: slli a0, a1, 33
; RV64-NEXT: srai a0, a0, 33
; RV64-NEXT: ret
@@ -2340,7 +2340,7 @@ define signext i32 @vreduce_mul_nxv32i32(<vscale x 32 x i32> %v) {
; RV32-NEXT: vmul.vv v9, v10, v11
; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: li a0, 1
-; RV32-NEXT: .LBB128_1: # %rdx.loop
+; RV32-NEXT: .LBB128_1: # %ec.loop
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vslidedown.vx v9, v8, a1
@@ -2348,7 +2348,7 @@ define signext i32 @vreduce_mul_nxv32i32(<vscale x 32 x i32> %v) {
; RV32-NEXT: addi a1, a1, 1
; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: bne a1, a2, .LBB128_1
-; RV32-NEXT: # %bb.2: # %rdx.exit
+; RV32-NEXT: # %bb.2: # %ec.exit
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_mul_nxv32i32:
@@ -2373,7 +2373,7 @@ define signext i32 @vreduce_mul_nxv32i32(<vscale x 32 x i32> %v) {
; RV64-NEXT: vmul.vv v9, v10, v11
; RV64-NEXT: vmul.vv v8, v8, v9
; RV64-NEXT: li a0, 1
-; RV64-NEXT: .LBB128_1: # %rdx.loop
+; RV64-NEXT: .LBB128_1: # %ec.loop
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vx v9, v8, a1
@@ -2381,7 +2381,7 @@ define signext i32 @vreduce_mul_nxv32i32(<vscale x 32 x i32> %v) {
; RV64-NEXT: addi a1, a1, 1
; RV64-NEXT: mulw a0, a0, a3
; RV64-NEXT: bne a1, a2, .LBB128_1
-; RV64-NEXT: # %bb.2: # %rdx.exit
+; RV64-NEXT: # %bb.2: # %ec.exit
; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv32i32(<vscale x 32 x i32> %v)
ret i32 %red
diff --git a/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
index 4b50094162155..fb8c07cb9623c 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/RISCV/asan-rvv-intrinsics.ll
@@ -17,7 +17,7 @@ define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* a
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -30,7 +30,7 @@ define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* a
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 [[TMP1]])
@@ -60,7 +60,7 @@ define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i3
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
@@ -73,7 +73,7 @@ define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i3
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]], i64 1)
@@ -102,7 +102,7 @@ define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
@@ -115,7 +115,7 @@ define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]])
@@ -144,7 +144,7 @@ define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]
@@ -157,7 +157,7 @@ define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]])
@@ -186,7 +186,7 @@ define <vscale x 1 x i32> @test_vlseg2_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -199,7 +199,7 @@ define <vscale x 1 x i32> @test_vlseg2_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -222,7 +222,7 @@ define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -235,7 +235,7 @@ define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -262,7 +262,7 @@ define <vscale x 1 x i32> @test_vlseg3_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -275,7 +275,7 @@ define <vscale x 1 x i32> @test_vlseg3_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -298,7 +298,7 @@ define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -311,7 +311,7 @@ define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -338,7 +338,7 @@ define <vscale x 1 x i32> @test_vlseg4_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -351,7 +351,7 @@ define <vscale x 1 x i32> @test_vlseg4_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -374,7 +374,7 @@ define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -387,7 +387,7 @@ define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -414,7 +414,7 @@ define <vscale x 1 x i32> @test_vlseg5_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -427,7 +427,7 @@ define <vscale x 1 x i32> @test_vlseg5_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -450,7 +450,7 @@ define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -463,7 +463,7 @@ define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -490,7 +490,7 @@ define <vscale x 1 x i32> @test_vlseg6_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -503,7 +503,7 @@ define <vscale x 1 x i32> @test_vlseg6_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -526,7 +526,7 @@ define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -539,7 +539,7 @@ define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -566,7 +566,7 @@ define <vscale x 1 x i32> @test_vlseg7_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -579,7 +579,7 @@ define <vscale x 1 x i32> @test_vlseg7_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -602,7 +602,7 @@ define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -615,7 +615,7 @@ define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -642,7 +642,7 @@ define <vscale x 1 x i32> @test_vlseg8_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -655,7 +655,7 @@ define <vscale x 1 x i32> @test_vlseg8_nxv1i32(ptr %base, i64 %vl) sanitize_addr
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[VL]], i64 5)
@@ -678,7 +678,7 @@ define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -691,7 +691,7 @@ define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(ptr %base, i64 %vl, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -718,7 +718,7 @@ define void @test_vsseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -731,7 +731,7 @@ define void @test_vsseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -752,7 +752,7 @@ define void @test_vsseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -765,7 +765,7 @@ define void @test_vsseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -790,7 +790,7 @@ define void @test_vsseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -803,7 +803,7 @@ define void @test_vsseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -824,7 +824,7 @@ define void @test_vsseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -837,7 +837,7 @@ define void @test_vsseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -862,7 +862,7 @@ define void @test_vsseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -875,7 +875,7 @@ define void @test_vsseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -896,7 +896,7 @@ define void @test_vsseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -909,7 +909,7 @@ define void @test_vsseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -934,7 +934,7 @@ define void @test_vsseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -947,7 +947,7 @@ define void @test_vsseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -968,7 +968,7 @@ define void @test_vsseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -981,7 +981,7 @@ define void @test_vsseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -1006,7 +1006,7 @@ define void @test_vsseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1019,7 +1019,7 @@ define void @test_vsseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -1040,7 +1040,7 @@ define void @test_vsseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1053,7 +1053,7 @@ define void @test_vsseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -1078,7 +1078,7 @@ define void @test_vsseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1091,7 +1091,7 @@ define void @test_vsseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -1112,7 +1112,7 @@ define void @test_vsseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1125,7 +1125,7 @@ define void @test_vsseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -1150,7 +1150,7 @@ define void @test_vsseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1163,7 +1163,7 @@ define void @test_vsseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)
@@ -1184,7 +1184,7 @@ define void @test_vsseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -1197,7 +1197,7 @@ define void @test_vsseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -1226,7 +1226,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>*
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
@@ -1240,7 +1240,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>*
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])
@@ -1274,7 +1274,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]
@@ -1288,7 +1288,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP16]]
; CHECK: 16:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
@@ -1322,7 +1322,7 @@ define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP14]]
@@ -1336,7 +1336,7 @@ define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP15]]
; CHECK: 15:
; CHECK-NEXT: call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]])
@@ -1369,7 +1369,7 @@ define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscal
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]
@@ -1383,7 +1383,7 @@ define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscal
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP16]]
; CHECK: 16:
; CHECK-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
@@ -1414,7 +1414,7 @@ define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1428,7 +1428,7 @@ define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1451,7 +1451,7 @@ define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1465,7 +1465,7 @@ define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1492,7 +1492,7 @@ define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1506,7 +1506,7 @@ define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1529,7 +1529,7 @@ define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1543,7 +1543,7 @@ define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1570,7 +1570,7 @@ define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1584,7 +1584,7 @@ define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1607,7 +1607,7 @@ define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1621,7 +1621,7 @@ define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1648,7 +1648,7 @@ define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1662,7 +1662,7 @@ define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1685,7 +1685,7 @@ define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1699,7 +1699,7 @@ define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1726,7 +1726,7 @@ define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1740,7 +1740,7 @@ define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1763,7 +1763,7 @@ define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1777,7 +1777,7 @@ define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1804,7 +1804,7 @@ define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1818,7 +1818,7 @@ define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1841,7 +1841,7 @@ define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1855,7 +1855,7 @@ define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1882,7 +1882,7 @@ define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1896,7 +1896,7 @@ define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(ptr %base, i64 %offset, i64 %vl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1919,7 +1919,7 @@ define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1933,7 +1933,7 @@ define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(ptr %base, i64 %offset, i64
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -1960,7 +1960,7 @@ define void @test_vssseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -1974,7 +1974,7 @@ define void @test_vssseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -1995,7 +1995,7 @@ define void @test_vssseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2009,7 +2009,7 @@ define void @test_vssseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2034,7 +2034,7 @@ define void @test_vssseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2048,7 +2048,7 @@ define void @test_vssseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2069,7 +2069,7 @@ define void @test_vssseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2083,7 +2083,7 @@ define void @test_vssseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2108,7 +2108,7 @@ define void @test_vssseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2122,7 +2122,7 @@ define void @test_vssseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2143,7 +2143,7 @@ define void @test_vssseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2157,7 +2157,7 @@ define void @test_vssseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2182,7 +2182,7 @@ define void @test_vssseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2196,7 +2196,7 @@ define void @test_vssseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2217,7 +2217,7 @@ define void @test_vssseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2231,7 +2231,7 @@ define void @test_vssseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2256,7 +2256,7 @@ define void @test_vssseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2270,7 +2270,7 @@ define void @test_vssseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2291,7 +2291,7 @@ define void @test_vssseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2305,7 +2305,7 @@ define void @test_vssseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2330,7 +2330,7 @@ define void @test_vssseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2344,7 +2344,7 @@ define void @test_vssseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2365,7 +2365,7 @@ define void @test_vssseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2379,7 +2379,7 @@ define void @test_vssseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2404,7 +2404,7 @@ define void @test_vssseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2418,7 +2418,7 @@ define void @test_vssseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)
@@ -2439,7 +2439,7 @@ define void @test_vssseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]
@@ -2453,7 +2453,7 @@ define void @test_vssseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP11]]
; CHECK: 11:
; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -2476,7 +2476,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32_align(<vscale x 1 x
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
@@ -2490,7 +2490,7 @@ define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32_align(<vscale x 1 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 4, i64 [[TMP2]])
@@ -2524,7 +2524,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
@@ -2537,7 +2537,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP15]]
; CHECK: 15:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
@@ -2573,7 +2573,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vsca
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
@@ -2586,7 +2586,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vsca
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP17]]
; CHECK: 17:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
@@ -2621,7 +2621,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
@@ -2634,7 +2634,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP15]]
; CHECK: 15:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
@@ -2668,7 +2668,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]
@@ -2681,7 +2681,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP15]]
; CHECK: 15:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])
@@ -2717,7 +2717,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vsca
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
@@ -2730,7 +2730,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vsca
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP17]]
; CHECK: 17:
; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)
@@ -2765,7 +2765,7 @@ define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
@@ -2778,7 +2778,7 @@ define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP16]]
; CHECK: 16:
; CHECK-NEXT: call void @llvm.riscv.vsoxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])
@@ -2813,7 +2813,7 @@ define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
@@ -2826,7 +2826,7 @@ define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP17]]
; CHECK: 17:
; CHECK-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
@@ -2861,7 +2861,7 @@ define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <
; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]
@@ -2874,7 +2874,7 @@ define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP16]]
; CHECK: 16:
; CHECK-NEXT: call void @llvm.riscv.vsuxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])
@@ -2909,7 +2909,7 @@ define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>
; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]
@@ -2922,7 +2922,7 @@ define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP17]]
; CHECK: 17:
; CHECK-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])
@@ -2955,7 +2955,7 @@ define <vscale x 1 x i32> @test_vloxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -2968,7 +2968,7 @@ define <vscale x 1 x i32> @test_vloxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -2993,7 +2993,7 @@ define <vscale x 1 x i32> @test_vloxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3006,7 +3006,7 @@ define <vscale x 1 x i32> @test_vloxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3035,7 +3035,7 @@ define <vscale x 1 x i32> @test_vloxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3048,7 +3048,7 @@ define <vscale x 1 x i32> @test_vloxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3073,7 +3073,7 @@ define <vscale x 1 x i32> @test_vloxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3086,7 +3086,7 @@ define <vscale x 1 x i32> @test_vloxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3115,7 +3115,7 @@ define <vscale x 1 x i32> @test_vloxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3128,7 +3128,7 @@ define <vscale x 1 x i32> @test_vloxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3153,7 +3153,7 @@ define <vscale x 1 x i32> @test_vloxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3166,7 +3166,7 @@ define <vscale x 1 x i32> @test_vloxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3195,7 +3195,7 @@ define <vscale x 1 x i32> @test_vloxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3208,7 +3208,7 @@ define <vscale x 1 x i32> @test_vloxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3233,7 +3233,7 @@ define <vscale x 1 x i32> @test_vloxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3246,7 +3246,7 @@ define <vscale x 1 x i32> @test_vloxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3275,7 +3275,7 @@ define <vscale x 1 x i32> @test_vloxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3288,7 +3288,7 @@ define <vscale x 1 x i32> @test_vloxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3313,7 +3313,7 @@ define <vscale x 1 x i32> @test_vloxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3326,7 +3326,7 @@ define <vscale x 1 x i32> @test_vloxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3355,7 +3355,7 @@ define <vscale x 1 x i32> @test_vloxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3368,7 +3368,7 @@ define <vscale x 1 x i32> @test_vloxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3393,7 +3393,7 @@ define <vscale x 1 x i32> @test_vloxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3406,7 +3406,7 @@ define <vscale x 1 x i32> @test_vloxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3435,7 +3435,7 @@ define <vscale x 1 x i32> @test_vloxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3448,7 +3448,7 @@ define <vscale x 1 x i32> @test_vloxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3473,7 +3473,7 @@ define <vscale x 1 x i32> @test_vloxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3486,7 +3486,7 @@ define <vscale x 1 x i32> @test_vloxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3515,7 +3515,7 @@ define <vscale x 1 x i32> @test_vluxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3528,7 +3528,7 @@ define <vscale x 1 x i32> @test_vluxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3553,7 +3553,7 @@ define <vscale x 1 x i32> @test_vluxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3566,7 +3566,7 @@ define <vscale x 1 x i32> @test_vluxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3595,7 +3595,7 @@ define <vscale x 1 x i32> @test_vluxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3608,7 +3608,7 @@ define <vscale x 1 x i32> @test_vluxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3633,7 +3633,7 @@ define <vscale x 1 x i32> @test_vluxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3646,7 +3646,7 @@ define <vscale x 1 x i32> @test_vluxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3675,7 +3675,7 @@ define <vscale x 1 x i32> @test_vluxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3688,7 +3688,7 @@ define <vscale x 1 x i32> @test_vluxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3713,7 +3713,7 @@ define <vscale x 1 x i32> @test_vluxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3726,7 +3726,7 @@ define <vscale x 1 x i32> @test_vluxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3755,7 +3755,7 @@ define <vscale x 1 x i32> @test_vluxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3768,7 +3768,7 @@ define <vscale x 1 x i32> @test_vluxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3793,7 +3793,7 @@ define <vscale x 1 x i32> @test_vluxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3806,7 +3806,7 @@ define <vscale x 1 x i32> @test_vluxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3835,7 +3835,7 @@ define <vscale x 1 x i32> @test_vluxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3848,7 +3848,7 @@ define <vscale x 1 x i32> @test_vluxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3873,7 +3873,7 @@ define <vscale x 1 x i32> @test_vluxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3886,7 +3886,7 @@ define <vscale x 1 x i32> @test_vluxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3915,7 +3915,7 @@ define <vscale x 1 x i32> @test_vluxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3928,7 +3928,7 @@ define <vscale x 1 x i32> @test_vluxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -3953,7 +3953,7 @@ define <vscale x 1 x i32> @test_vluxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -3966,7 +3966,7 @@ define <vscale x 1 x i32> @test_vluxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -3995,7 +3995,7 @@ define <vscale x 1 x i32> @test_vluxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4008,7 +4008,7 @@ define <vscale x 1 x i32> @test_vluxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4033,7 +4033,7 @@ define <vscale x 1 x i32> @test_vluxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4046,7 +4046,7 @@ define <vscale x 1 x i32> @test_vluxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)
@@ -4075,7 +4075,7 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4088,7 +4088,7 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4111,7 +4111,7 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4124,7 +4124,7 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4151,7 +4151,7 @@ define void @test_vsoxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4164,7 +4164,7 @@ define void @test_vsoxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4187,7 +4187,7 @@ define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4200,7 +4200,7 @@ define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4227,7 +4227,7 @@ define void @test_vsoxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4240,7 +4240,7 @@ define void @test_vsoxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4263,7 +4263,7 @@ define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4276,7 +4276,7 @@ define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4303,7 +4303,7 @@ define void @test_vsoxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4316,7 +4316,7 @@ define void @test_vsoxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4339,7 +4339,7 @@ define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4352,7 +4352,7 @@ define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4379,7 +4379,7 @@ define void @test_vsoxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4392,7 +4392,7 @@ define void @test_vsoxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4415,7 +4415,7 @@ define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4428,7 +4428,7 @@ define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4455,7 +4455,7 @@ define void @test_vsoxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4468,7 +4468,7 @@ define void @test_vsoxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4491,7 +4491,7 @@ define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4504,7 +4504,7 @@ define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4531,7 +4531,7 @@ define void @test_vsoxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4544,7 +4544,7 @@ define void @test_vsoxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4567,7 +4567,7 @@ define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4580,7 +4580,7 @@ define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4607,7 +4607,7 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4620,7 +4620,7 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4643,7 +4643,7 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4656,7 +4656,7 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4683,7 +4683,7 @@ define void @test_vsuxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4696,7 +4696,7 @@ define void @test_vsuxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4719,7 +4719,7 @@ define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4732,7 +4732,7 @@ define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4759,7 +4759,7 @@ define void @test_vsuxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4772,7 +4772,7 @@ define void @test_vsuxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4795,7 +4795,7 @@ define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4808,7 +4808,7 @@ define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4835,7 +4835,7 @@ define void @test_vsuxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4848,7 +4848,7 @@ define void @test_vsuxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4871,7 +4871,7 @@ define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4884,7 +4884,7 @@ define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4911,7 +4911,7 @@ define void @test_vsuxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4924,7 +4924,7 @@ define void @test_vsuxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -4947,7 +4947,7 @@ define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -4960,7 +4960,7 @@ define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -4987,7 +4987,7 @@ define void @test_vsuxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -5000,7 +5000,7 @@ define void @test_vsuxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -5023,7 +5023,7 @@ define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -5036,7 +5036,7 @@ define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
@@ -5063,7 +5063,7 @@ define void @test_vsuxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -5076,7 +5076,7 @@ define void @test_vsuxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)
@@ -5099,7 +5099,7 @@ define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -5112,7 +5112,7 @@ define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)
diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
index 60a4f2225035f..db50e739ca727 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
@@ -317,7 +317,7 @@ define <vscale x 4 x float> @scalable.load.nxv4f32(ptr %p, <vscale x 4 x i1> %ma
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
@@ -330,7 +330,7 @@ define <vscale x 4 x float> @scalable.load.nxv4f32(ptr %p, <vscale x 4 x i1> %ma
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0(ptr align 4 [[P]], <vscale x 4 x i1> [[MASK]], <vscale x 4 x float> undef)
; CHECK-NEXT: ret <vscale x 4 x float> [[RES]]
;
@@ -347,7 +347,7 @@ define void @scalable.store.nxv4f32(ptr %p, <vscale x 4 x float> %arg, <vscale x
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
@@ -360,7 +360,7 @@ define void @scalable.store.nxv4f32(ptr %p, <vscale x 4 x float> %arg, <vscale x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: tail call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[ARG:%.*]], ptr align 4 [[P]], <vscale x 4 x i1> [[MASK]])
; CHECK-NEXT: ret void
;
@@ -381,7 +381,7 @@ define <vscale x 4 x float> @scalable.gather.nxv4f32(<vscale x 4 x ptr> %vp, <vs
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
@@ -394,7 +394,7 @@ define <vscale x 4 x float> @scalable.gather.nxv4f32(<vscale x 4 x ptr> %vp, <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr> align 4 [[VP]], <vscale x 4 x i1> [[MASK]], <vscale x 4 x float> undef)
; CHECK-NEXT: ret <vscale x 4 x float> [[RES]]
;
@@ -411,7 +411,7 @@ define void @scalable.scatter.nxv4f32(<vscale x 4 x float> %val, <vscale x 4 x p
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
@@ -424,7 +424,7 @@ define void @scalable.scatter.nxv4f32(<vscale x 4 x float> %val, <vscale x 4 x p
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: tail call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> [[VAL:%.*]], <vscale x 4 x ptr> align 4 [[VP]], <vscale x 4 x i1> [[MASK]])
; CHECK-NEXT: ret void
;
@@ -450,7 +450,7 @@ define <vscale x 4 x float> @scalable.expandload.nxv4f32(ptr align 4 %p, <vscale
; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 4 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
@@ -463,7 +463,7 @@ define <vscale x 4 x float> @scalable.expandload.nxv4f32(ptr align 4 %p, <vscale
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.masked.expandload.nxv4f32(ptr [[P]], <vscale x 4 x i1> [[MASK]], <vscale x 4 x float> undef)
@@ -488,7 +488,7 @@ define void @scalable.compressstore.nxv4f32(ptr align 4 %p, <vscale x 4 x float>
; CHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 4 x i1> splat (i1 true), i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]
@@ -501,7 +501,7 @@ define void @scalable.compressstore.nxv4f32(ptr align 4 %p, <vscale x 4 x float>
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: tail call void @llvm.masked.compressstore.nxv4f32(<vscale x 4 x float> [[ARG:%.*]], ptr [[P]], <vscale x 4 x i1> [[MASK]])
diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
index f53aa44c8c90f..a1682e51c2c95 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
@@ -17,7 +17,7 @@ define void @store.v4f32.variable(ptr align 4 %p, <4 x float> %arg, <4 x i1> %ma
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -30,7 +30,7 @@ define void @store.v4f32.variable(ptr align 4 %p, <4 x float> %arg, <4 x i1> %ma
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.vp.store.v4f32.p0(<4 x float> [[ARG:%.*]], ptr [[P]], <4 x i1> [[MASK]], i32 [[EVL]])
@@ -53,7 +53,7 @@ define void @store.v4f32.1010.split(ptr align 4 %p, <4 x float> %arg, i32 %evl)
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> <i1 false, i1 false, i1 true, i1 true>, i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -66,7 +66,7 @@ define void @store.v4f32.1010.split(ptr align 4 %p, <4 x float> %arg, i32 %evl)
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: tail call void @llvm.vp.store.v4f32.p0(<4 x float> [[ARG:%.*]], ptr [[P]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>, i32 [[EVL]])
@@ -76,7 +76,7 @@ define void @store.v4f32.1010.split(ptr align 4 %p, <4 x float> %arg, i32 %evl)
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP13]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
-; CHECK: .split1:
+; CHECK: ec.loop1:
; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP12]] ], [ [[IV2_NEXT:%.*]], [[TMP19:%.*]] ]
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> <i1 false, i1 false, i1 true, i1 false>, i64 [[IV2]]
; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP19]]
@@ -89,7 +89,7 @@ define void @store.v4f32.1010.split(ptr align 4 %p, <4 x float> %arg, i32 %evl)
; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP14]]
; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
-; CHECK: .split1.split:
+; CHECK: ec.exit2:
; CHECK-NEXT: br label [[TMP20]]
; CHECK: 20:
; CHECK-NEXT: tail call void @llvm.vp.store.v4f32.p0(<4 x float> [[ARG]], ptr [[P]], <4 x i1> <i1 false, i1 false, i1 true, i1 false>, i32 [[EVL]])
@@ -136,7 +136,7 @@ define <4 x float> @load.v4f32.variable(ptr align 4 %p, <4 x float> %arg, <4 x i
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -149,7 +149,7 @@ define <4 x float> @load.v4f32.variable(ptr align 4 %p, <4 x float> %arg, <4 x i
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[RES:%.*]] = tail call <4 x float> @llvm.vp.load.v4f32.p0(ptr [[P]], <4 x i1> [[MASK]], i32 [[EVL]])
@@ -172,7 +172,7 @@ define <4 x float> @load.v4f32.1001.split(ptr align 4 %p, i32 %evl) sanitize_add
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> <i1 true, i1 false, i1 false, i1 false>, i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]
@@ -185,7 +185,7 @@ define <4 x float> @load.v4f32.1001.split(ptr align 4 %p, i32 %evl) sanitize_add
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: [[RES:%.*]] = tail call <4 x float> @llvm.vp.load.v4f32.p0(ptr [[P]], <4 x i1> <i1 true, i1 false, i1 false, i1 false>, i32 [[EVL]])
@@ -195,7 +195,7 @@ define <4 x float> @load.v4f32.1001.split(ptr align 4 %p, i32 %evl) sanitize_add
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[EVL]] to i64
; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP13]], i64 4)
; CHECK-NEXT: br label [[DOTSPLIT1:%.*]]
-; CHECK: .split1:
+; CHECK: ec.loop1:
; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[TMP12]] ], [ [[IV2_NEXT:%.*]], [[TMP19:%.*]] ]
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> <i1 false, i1 false, i1 false, i1 true>, i64 [[IV2]]
; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP19]]
@@ -208,7 +208,7 @@ define <4 x float> @load.v4f32.1001.split(ptr align 4 %p, i32 %evl) sanitize_add
; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
; CHECK-NEXT: [[IV2_CHECK:%.*]] = icmp eq i64 [[IV2_NEXT]], [[TMP14]]
; CHECK-NEXT: br i1 [[IV2_CHECK]], label [[DOTSPLIT1_SPLIT:%.*]], label [[DOTSPLIT1]]
-; CHECK: .split1.split:
+; CHECK: ec.exit2:
; CHECK-NEXT: br label [[TMP20]]
; CHECK: 20:
; CHECK-NEXT: [[RES2:%.*]] = tail call <4 x float> @llvm.vp.load.v4f32.p0(ptr [[P]], <4 x i1> <i1 false, i1 false, i1 false, i1 true>, i32 [[EVL]])
@@ -258,7 +258,7 @@ define <vscale x 4 x float> @scalable.load.nxv4f32(ptr align 4 %p, <vscale x 4 x
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -271,7 +271,7 @@ define <vscale x 4 x float> @scalable.load.nxv4f32(ptr align 4 %p, <vscale x 4 x
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr [[P]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -295,7 +295,7 @@ define void @scalable.store.nxv4f32(ptr align 4 %p, <vscale x 4 x float> %arg, <
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -308,7 +308,7 @@ define void @scalable.store.nxv4f32(ptr align 4 %p, <vscale x 4 x float> %arg, <
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[ARG:%.*]], ptr [[P]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -337,7 +337,7 @@ define <vscale x 4 x float> @scalable.strided.load.nxv4f32(ptr align 4 %p, i32 %
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[STRIDE:%.*]] to i64
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
@@ -351,7 +351,7 @@ define <vscale x 4 x float> @scalable.strided.load.nxv4f32(ptr align 4 %p, i32 %
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.experimental.vp.strided.load.nxv4f32.p0.i32(ptr [[P]], i32 [[STRIDE]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -376,7 +376,7 @@ define void @scalable.strided.store.nxv4f32(<vscale x 4 x float> %arg, ptr align
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[STRIDE:%.*]] to i64
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]
@@ -390,7 +390,7 @@ define void @scalable.strided.store.nxv4f32(<vscale x 4 x float> %arg, ptr align
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP14]]
; CHECK: 14:
; CHECK-NEXT: tail call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> [[ARG:%.*]], ptr [[P]], i32 [[STRIDE]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -415,7 +415,7 @@ define <vscale x 4 x float> @scalable.strided.load.nxv4f32.align(ptr align 4 %p,
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP12]]
@@ -429,7 +429,7 @@ define <vscale x 4 x float> @scalable.strided.load.nxv4f32.align(ptr align 4 %p,
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.experimental.vp.strided.load.nxv4f32.p0.i32(ptr [[P]], i32 4, <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -457,7 +457,7 @@ define <vscale x 4 x float> @scalable.gather.nxv4f32(<vscale x 4 x ptr> %vp, <vs
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -470,7 +470,7 @@ define <vscale x 4 x float> @scalable.gather.nxv4f32(<vscale x 4 x ptr> %vp, <vs
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.vp.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr> align 4 [[VP]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
@@ -494,7 +494,7 @@ define void @scalable.scatter.nxv4f32(<vscale x 4 x float> %arg, <vscale x 4 x p
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP5]])
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
-; CHECK: .split:
+; CHECK: ec.loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]
@@ -507,7 +507,7 @@ define void @scalable.scatter.nxv4f32(<vscale x 4 x float> %arg, <vscale x 4 x p
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; CHECK: .split.split:
+; CHECK: ec.exit:
; CHECK-NEXT: br label [[TMP12]]
; CHECK: 12:
; CHECK-NEXT: tail call void @llvm.vp.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> [[ARG:%.*]], <vscale x 4 x ptr> align 4 [[VP]], <vscale x 4 x i1> [[MASK]], i32 [[EVL]])
diff --git a/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll b/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
index d01974016f6c9..f536e0a859b26 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
@@ -676,14 +676,14 @@ define void @store.nxv1i32(ptr %p) sanitize_memory {
; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4
; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGINS: .split:
+; ORIGINS: ec.loop:
; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4
; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGINS: .split.split:
+; ORIGINS: ec.exit:
; ORIGINS-NEXT: br label [[TMP13]]
; ORIGINS: 13:
; ORIGINS-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4
@@ -736,14 +736,14 @@ define void @store.nxv2i32(ptr %p) sanitize_memory {
; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4
; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGINS: .split:
+; ORIGINS: ec.loop:
; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4
; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGINS: .split.split:
+; ORIGINS: ec.exit:
; ORIGINS-NEXT: br label [[TMP13]]
; ORIGINS: 13:
; ORIGINS-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8
@@ -796,14 +796,14 @@ define void @store.nxv4i32(ptr %p) sanitize_memory {
; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4
; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGINS: .split:
+; ORIGINS: ec.loop:
; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4
; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGINS: .split.split:
+; ORIGINS: ec.exit:
; ORIGINS-NEXT: br label [[TMP13]]
; ORIGINS: 13:
; ORIGINS-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16
@@ -856,14 +856,14 @@ define void @store.nxv8i32(ptr %p) sanitize_memory {
; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4
; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGINS: .split:
+; ORIGINS: ec.loop:
; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4
; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGINS: .split.split:
+; ORIGINS: ec.exit:
; ORIGINS-NEXT: br label [[TMP13]]
; ORIGINS: 13:
; ORIGINS-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32
@@ -916,14 +916,14 @@ define void @store.nxv16i32(ptr %p) sanitize_memory {
; ORIGINS-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
; ORIGINS-NEXT: [[TMP11:%.*]] = udiv i64 [[TMP10]], 4
; ORIGINS-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGINS: .split:
+; ORIGINS: ec.loop:
; ORIGINS-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4
; ORIGINS-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGINS-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]
; ORIGINS-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGINS: .split.split:
+; ORIGINS: ec.exit:
; ORIGINS-NEXT: br label [[TMP13]]
; ORIGINS: 13:
; ORIGINS-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64
diff --git a/llvm/test/Instrumentation/MemorySanitizer/vscale.ll b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll
index 514abedf8fe1a..614a3ad581f21 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/vscale.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll
@@ -48,14 +48,14 @@ define void @test_load_store_i32(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 3
; ORIGIN-NEXT: [[TMP19:%.*]] = udiv i64 [[TMP18]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP12]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP15]], ptr [[TMP20]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP19]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP21]]
; ORIGIN: 21:
; ORIGIN-NEXT: store <vscale x 4 x i32> [[TMP1]], ptr [[B]], align 16
@@ -129,14 +129,14 @@ define void @test_load_store_add_int(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
; ORIGIN-NEXT: [[TMP30:%.*]] = udiv i64 [[TMP29]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP25]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP23]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP26]], ptr [[TMP31]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP30]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP32]]
; ORIGIN: 32:
; ORIGIN-NEXT: store <vscale x 8 x i64> [[TMP8]], ptr [[B]], align 64
@@ -192,14 +192,14 @@ define void @test_load_store_float(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 3
; ORIGIN-NEXT: [[TMP19:%.*]] = udiv i64 [[TMP18]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP14]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP12]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP15]], ptr [[TMP20]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP19]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP21]]
; ORIGIN: 21:
; ORIGIN-NEXT: store <vscale x 4 x float> [[TMP1]], ptr [[B]], align 16
@@ -273,14 +273,14 @@ define void @test_load_store_add_float(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
; ORIGIN-NEXT: [[TMP30:%.*]] = udiv i64 [[TMP29]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP25]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP23]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP26]], ptr [[TMP31]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP30]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP32]]
; ORIGIN: 32:
; ORIGIN-NEXT: store <vscale x 2 x float> [[TMP8]], ptr [[B]], align 8
@@ -367,14 +367,14 @@ define void @test_ret(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 3
; ORIGIN-NEXT: [[TMP16:%.*]] = udiv i64 [[TMP15]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP11]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP9]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP12]], ptr [[TMP17]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP16]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP18]]
; ORIGIN: 18:
; ORIGIN-NEXT: store <vscale x 2 x float> [[TMP3]], ptr [[B]], align 8
@@ -415,14 +415,14 @@ define void @fn_param(<vscale x 2 x float> %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], 3
; ORIGIN-NEXT: [[TMP12:%.*]] = udiv i64 [[TMP11]], 4
; ORIGIN-NEXT: br label [[DOTSPLIT:%.*]]
-; ORIGIN: .split:
+; ORIGIN: ec.loop:
; ORIGIN-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[DOTSPLIT]] ]
; ORIGIN-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[IV]]
; ORIGIN-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 4
; ORIGIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; ORIGIN-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP12]]
; ORIGIN-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
-; ORIGIN: .split.split:
+; ORIGIN: ec.exit:
; ORIGIN-NEXT: br label [[TMP14]]
; ORIGIN: 14:
; ORIGIN-NEXT: store <vscale x 2 x float> [[A]], ptr [[B]], align 8
@@ -447,7 +447,7 @@ define void @test_param(ptr %a, ptr %b) sanitize_memory {
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF1:![0-9]+]]
; CHECK: 7:
-; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]
+; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]]
; CHECK-NEXT: unreachable
; CHECK: 8:
; CHECK-NEXT: call void @fn_param(<vscale x 2 x float> [[TMP2]], ptr [[B]])
@@ -472,7 +472,7 @@ define void @test_param(ptr %a, ptr %b) sanitize_memory {
; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP10]], 0
; ORIGIN-NEXT: br i1 [[_MSCMP]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF1]]
; ORIGIN: 11:
-; ORIGIN-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP9]]) #[[ATTR5:[0-9]+]]
+; ORIGIN-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP9]]) #[[ATTR6:[0-9]+]]
; ORIGIN-NEXT: unreachable
; ORIGIN: 12:
; ORIGIN-NEXT: call void @fn_param(<vscale x 2 x float> [[TMP3]], ptr [[B]])
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
index ec88653145df6..b98b65c2cc461 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
@@ -15,7 +15,7 @@ define <vscale x 4 x float> @scalable_vec_exp(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.exp.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-fp-math.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-fp-math.ll
index 867d655ebf39c..24ff1d47def8c 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-fp-math.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-fp-math.ll
@@ -14,7 +14,7 @@ define <vscale x 4 x float> @scalable_vec_acos(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.acos.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -36,7 +36,7 @@ define <vscale x 4 x float> @scalable_vec_asin(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.asin.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -58,7 +58,7 @@ define <vscale x 4 x float> @scalable_vec_atan(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.atan.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -90,7 +90,7 @@ define <vscale x 4 x float> @scalable_vec_cos(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.cos.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -112,7 +112,7 @@ define <vscale x 4 x float> @scalable_vec_cosh(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.cosh.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -134,7 +134,7 @@ define <vscale x 4 x float> @scalable_vec_exp10(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.exp10.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -156,7 +156,7 @@ define <vscale x 4 x float> @scalable_vec_log2(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log2.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -178,7 +178,7 @@ define <vscale x 4 x float> @scalable_vec_log10(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log10.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -200,7 +200,7 @@ define <vscale x 4 x float> @scalable_vec_sin(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -222,7 +222,7 @@ define <vscale x 4 x float> @scalable_vec_sinh(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.sinh.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -244,7 +244,7 @@ define <vscale x 4 x float> @scalable_vec_tan(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.tan.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
@@ -266,7 +266,7 @@ define <vscale x 4 x float> @scalable_vec_tanh(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.tanh.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
index 4925011201aee..37ec2331718b1 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
@@ -14,7 +14,7 @@ define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll
index 439a74c18d1ee..7ae4a4329cdf4 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/expand-fp-math.ll
@@ -14,7 +14,7 @@ define <vscale x 4 x float> @scalable_vec_sin(<vscale x 4 x float> %input) {
; RV32-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT: [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; RV32-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
-; RV32-NEXT: [[TMP9]] = add i32 [[TMP4]], 1
+; RV32-NEXT: [[TMP9]] = add nuw nsw i32 [[TMP4]], 1
; RV32-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32: [[BB11]]:
@@ -31,7 +31,7 @@ define <vscale x 4 x float> @scalable_vec_sin(<vscale x 4 x float> %input) {
; RV64-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT: [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; RV64-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; RV64-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; RV64-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; RV64-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64: [[BB11]]:
@@ -53,7 +53,7 @@ define <vscale x 4 x float> @scalable_vec_exp(<vscale x 4 x float> %input) {
; RV32-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT: [[TMP7:%.*]] = call float @llvm.exp.f32(float [[TMP6]])
; RV32-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
-; RV32-NEXT: [[TMP9]] = add i32 [[TMP4]], 1
+; RV32-NEXT: [[TMP9]] = add nuw nsw i32 [[TMP4]], 1
; RV32-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32: [[BB11]]:
@@ -70,7 +70,7 @@ define <vscale x 4 x float> @scalable_vec_exp(<vscale x 4 x float> %input) {
; RV64-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT: [[TMP7:%.*]] = call float @llvm.exp.f32(float [[TMP6]])
; RV64-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; RV64-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; RV64-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; RV64-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64: [[BB11]]:
@@ -92,7 +92,7 @@ define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; RV32-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; RV32-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
-; RV32-NEXT: [[TMP9]] = add i32 [[TMP4]], 1
+; RV32-NEXT: [[TMP9]] = add nuw nsw i32 [[TMP4]], 1
; RV32-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32: [[BB11]]:
@@ -109,7 +109,7 @@ define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; RV64-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; RV64-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
-; RV64-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; RV64-NEXT: [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
; RV64-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64: [[BB11]]:
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