[llvm] [CodeGen] Disallow CSE for instructions with ignorable operands (PR #194863)

[Stanislav Mekhanoshin via llvm-commits]

================

----------------
rampitec wrote:

Like assume that is a normal vector add or something vector. It reads VGPRs in the same lane mask as it writes. You can rematerialize it, you can CSE it, it is all within the same exec mask. The moment we cross the VALU domain to SALU it breaks, the implicit use of exec is not ignorable now.

https://github.com/llvm/llvm-project/pull/194863