[llvm] [CodeGen] Disallow CSE for instructions with ignorable operands (PR #194863)

[Stanislav Mekhanoshin via llvm-commits]

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rampitec wrote:

Yes, it would. I was looking at the test case and my thoughts about it was: we are crossing scalar and vector domains in a way, where VALU really produces a scalar mask used to be applied to exec. That is not normal for VALU to generate a scalar output, it is most likely to be used as a lane mask in this case. I do not see a comment about a 'fewer lanes' applied here in fact, what happens is that it reads exec, compares VGPR and produces SGPR which is then applied to exec. We do not want to analyze uses of the def, so we'd better just disable any cross-domain defs.

https://github.com/llvm/llvm-project/pull/194863