[llvm] [CodeGen] Disallow CSE for instructions with ignorable operands (PR #194863)

[Jay Foad via llvm-commits]

jayfoad wrote:

If you were doing CSE in a "normal" case without do-while loops then the first (dominating) definition would naturally have more lanes enabled than the second definition, and it should be OK to do the CSE.

The odd thing about this do-while looping case is that the dominating definition has fewer lanes enabled than the second definition. I don't have any great ideas about how to handle this.

https://github.com/llvm/llvm-project/pull/194863