[llvm] [CodeGen] Disallow CSE for instructions with ignorable operands (PR #194863)
Igor Wodiany via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 08:47:24 PDT 2026
https://github.com/IgWod updated https://github.com/llvm/llvm-project/pull/194863
>From 34933ad6f8501527dcd302bfe0d64f120e755418 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 27 Apr 2026 15:35:43 +0100
Subject: [PATCH] [CodeGen] Disallow CSE for instructions with ignorable
operands
This reverts 11e8686 that allowed to CSE when a use was deemed
ignorable. However, in the context of CSE `isIgnorableUse` is
not always reliable and can casue mis-compilation.
In the case of the AMDGPU target this could cause an issue when
a V_CMP_* instruction was replaced despite being no guarantee
that the execution mask for both instructions is the same.
Looking at the example below. The second V_CMP_GT cannot be
replaced with %3, despite both having the same operands as there
is no guarantee the execution mask is the same at the last loop
iteration and after the loop finishes.
```
bb.1
%3:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
%4:sreg_64 = SI_IF_BREAK killed %3:sreg_64, %2:sreg_64, implicit-def dead $scc
SI_LOOP %4:sreg_64, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.2
bb.2:
SI_END_CF %4:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%5:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
%6:sreg_64 = S_AND_B64 %5:sreg_64, $exec, implicit-def $scc
```
A test to catch this particular scenario is added in
`preserve-second-cmp-cse.mir`.
---
llvm/lib/CodeGen/MachineCSE.cpp | 9 +-
.../divergence-temporal-divergent-i1.ll | 1 +
.../CodeGen/AMDGPU/GlobalISel/localizer.ll | 6 +-
.../AMDGPU/GlobalISel/regbankselect-mui.ll | 26 +-
.../CodeGen/AMDGPU/GlobalISel/udiv.i64.ll | 406 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 406 +-
.../AMDGPU/GlobalISel/vni8-across-blocks.ll | 228 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 48805 ++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 2005 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll | 178 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll | 35 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll | 355 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll | 283 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 6008 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll | 368 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 4983 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 329 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll | 463 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll | 796 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll | 926 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll | 99 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 17926 +++---
.../CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll | 2635 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 2766 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 878 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll | 3420 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 3709 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 3640 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 4535 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 4897 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 1105 +-
.../atomic_optimizations_local_pointer.ll | 2173 +-
.../AMDGPU/atomicrmw-bf16-gfx11plus.ll | 25 +-
.../branch-folding-implicit-def-subreg.ll | 406 +-
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 16 +-
llvm/test/CodeGen/AMDGPU/div_i128.ll | 210 +-
llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 985 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 1027 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 1027 +-
llvm/test/CodeGen/AMDGPU/fptoi.i128.ll | 204 +-
.../AMDGPU/global_atomics_scan_fadd.ll | 155 +-
.../AMDGPU/global_atomics_scan_fmax.ll | 96 +-
.../AMDGPU/global_atomics_scan_fmin.ll | 96 +-
.../AMDGPU/global_atomics_scan_fsub.ll | 155 +-
.../identical-subrange-spill-infloop.ll | 330 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 367 +-
...ne-sink-temporal-divergence-swdev407790.ll | 66 +-
.../CodeGen/AMDGPU/masked-load-vectortypes.ll | 21 +-
.../CodeGen/AMDGPU/memcpy-crash-issue63986.ll | 133 +-
.../AMDGPU/memset-param-combinations.ll | 8 +-
.../AMDGPU/preserve-second-cmp-cse.mir | 66 +
llvm/test/CodeGen/AMDGPU/rem_i128.ll | 256 +-
llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll | 3 +-
.../CodeGen/AMDGPU/spill-scavenge-offset.ll | 480 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 10 +-
.../AMDGPU/undef-handling-crash-in-ra.ll | 27 +-
llvm/test/CodeGen/AMDGPU/valu-i1.ll | 79 +-
.../test/CodeGen/AMDGPU/vni8-across-blocks.ll | 191 +-
...dgpu_generated_funcs.ll.generated.expected | 24 +-
...pu_generated_funcs.ll.nogenerated.expected | 24 +-
60 files changed, 65492 insertions(+), 55394 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/preserve-second-cmp-cse.mir
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 67ecb80bc3ee0..b3bce75b7e12a 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -259,10 +259,8 @@ bool MachineCSEImpl::isPhysDefTriviallyDead(
}
static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
- const MachineOperand &MO,
const MachineFunction &MF,
- const TargetRegisterInfo &TRI,
- const TargetInstrInfo &TII) {
+ const TargetRegisterInfo &TRI) {
// MachineRegisterInfo::isConstantPhysReg directly called by
// MachineRegisterInfo::isCallerPreservedOrConstPhysReg expects the
// reserved registers to be frozen. That doesn't cause a problem post-ISel as
@@ -271,7 +269,7 @@ static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
// It does cause issues mid-GlobalISel, however, hence the additional
// reservedRegsFrozen check.
const MachineRegisterInfo &MRI = MF.getRegInfo();
- return TRI.isCallerPreservedPhysReg(Reg, MF) || TII.isIgnorableUse(MO) ||
+ return TRI.isCallerPreservedPhysReg(Reg, MF) ||
(MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
}
@@ -292,8 +290,7 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
if (Reg.isVirtual())
continue;
// Reading either caller preserved or constant physregs is ok.
- if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), MO, *MI->getMF(), *TRI,
- *TII))
+ if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), *MI->getMF(), *TRI))
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
PhysRefs.insert(*AI);
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
index a8b27ecd7e9fc..701a1bcebb14a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
@@ -428,6 +428,7 @@ define void @nested_loops_temporal_divergence_both(float %pre.cond.val, i32 %n.i
; GFX10-NEXT: s_cbranch_execnz .LBB5_1
; GFX10-NEXT: ; %bb.4: ; %exit
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s9
; GFX10-NEXT: flat_store_byte v[6:7], v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
index 06801e6056033..1b374924f0520 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
@@ -166,10 +166,9 @@ define void @localize_internal_globals(i1 %cond) {
; GFX9-LABEL: localize_internal_globals:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v1, 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: s_mov_b64 s[4:5], exec
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
@@ -184,6 +183,7 @@ define void @localize_internal_globals(i1 %cond) {
; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv2 at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2 at rel32@hi+12
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getpc_b64 s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
index fa280a852383b..61c4c978cd215 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
@@ -506,33 +506,35 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; OLD_RBS-NEXT: s_andn2_b32 s1, s1, exec_lo
; OLD_RBS-NEXT: s_and_b32 s2, exec_lo, -1
; OLD_RBS-NEXT: s_or_b32 s1, s1, s2
-; OLD_RBS-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7]
-; OLD_RBS-NEXT: v_add_co_u32 v9, vcc_lo, v2, v7
-; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo
-; OLD_RBS-NEXT: global_load_dword v9, v[9:10], off
+; OLD_RBS-NEXT: v_lshlrev_b64 v[8:9], 2, v[6:7]
+; OLD_RBS-NEXT: v_add_co_u32 v8, vcc_lo, v2, v8
+; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v3, v9, vcc_lo
+; OLD_RBS-NEXT: global_load_dword v8, v[8:9], off
; OLD_RBS-NEXT: s_waitcnt vmcnt(0)
-; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; OLD_RBS-NEXT: s_and_saveexec_b32 s2, vcc_lo
; OLD_RBS-NEXT: s_cbranch_execz .LBB16_2
; OLD_RBS-NEXT: ; %bb.4: ; %B
; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1
-; OLD_RBS-NEXT: v_add_co_u32 v9, vcc_lo, v4, v7
-; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v5, v8, vcc_lo
+; OLD_RBS-NEXT: v_lshlrev_b64 v[8:9], 2, v[6:7]
; OLD_RBS-NEXT: s_mov_b32 s4, -1
-; OLD_RBS-NEXT: global_load_dword v9, v[9:10], off
+; OLD_RBS-NEXT: v_add_co_u32 v8, vcc_lo, v4, v8
+; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v5, v9, vcc_lo
+; OLD_RBS-NEXT: global_load_dword v8, v[8:9], off
; OLD_RBS-NEXT: s_waitcnt vmcnt(0)
-; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; OLD_RBS-NEXT: s_and_saveexec_b32 s3, vcc_lo
; OLD_RBS-NEXT: s_cbranch_execz .LBB16_1
; OLD_RBS-NEXT: ; %bb.5: ; %loop.body
; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1
+; OLD_RBS-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7]
+; OLD_RBS-NEXT: v_add_nc_u32_e32 v10, 1, v6
+; OLD_RBS-NEXT: s_andn2_b32 s4, -1, exec_lo
; OLD_RBS-NEXT: v_add_co_u32 v7, vcc_lo, v0, v7
; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v1, v8, vcc_lo
-; OLD_RBS-NEXT: v_add_nc_u32_e32 v10, 1, v6
; OLD_RBS-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v6
-; OLD_RBS-NEXT: s_andn2_b32 s4, -1, exec_lo
-; OLD_RBS-NEXT: global_load_dword v9, v[7:8], off
; OLD_RBS-NEXT: v_mov_b32_e32 v6, v10
+; OLD_RBS-NEXT: global_load_dword v9, v[7:8], off
; OLD_RBS-NEXT: s_and_b32 s5, exec_lo, vcc_lo
; OLD_RBS-NEXT: s_or_b32 s4, s4, s5
; OLD_RBS-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
index ded985ec3a1ec..171a2c5bee7d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
@@ -13,7 +13,6 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -21,34 +20,35 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: ; %bb.1: ; %Flow
; CHECK-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_cbranch_execnz .LBB0_4
-; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: .LBB0_2: ; %.split
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .LBB0_3:
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v3
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
-; CHECK-NEXT: v_mac_f32_e32 v6, 0x4f800000, v0
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v6
+; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v0
-; CHECK-NEXT: v_trunc_f32_e32 v6, v6
-; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v6
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v6
-; CHECK-NEXT: v_mul_lo_u32 v9, v1, v0
+; CHECK-NEXT: v_mul_lo_u32 v8, v6, v1
+; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v11, v1, v0
+; CHECK-NEXT: v_mul_hi_u32 v11, v6, v0
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; CHECK-NEXT: v_mul_lo_u32 v10, v6, v9
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v9
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT: v_mul_hi_u32 v9, v1, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_mul_lo_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_lo_u32 v13, v6, v8
+; CHECK-NEXT: v_mul_lo_u32 v13, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v14, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
@@ -64,20 +64,20 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v0
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v9, v1, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v1, v6
-; CHECK-NEXT: v_mul_lo_u32 v10, v6, v8
+; CHECK-NEXT: v_mul_hi_u32 v9, v6, v0
+; CHECK-NEXT: v_mul_lo_u32 v6, v6, v1
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v7, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v1
-; CHECK-NEXT: v_mul_lo_u32 v9, v6, v1
-; CHECK-NEXT: v_mul_hi_u32 v12, v0, v1
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v1
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6
+; CHECK-NEXT: v_mul_lo_u32 v9, v1, v6
+; CHECK-NEXT: v_mul_hi_u32 v12, v0, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
@@ -91,9 +91,9 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
@@ -149,15 +149,15 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CHECK-NEXT: ; implicit-def: $vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v6
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v3, v3, v0
@@ -342,7 +342,7 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: .LBB1_5:
+; CHECK-NEXT: .LBB1_5: ; %.split
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog
@@ -624,36 +624,36 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v4
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1:
-; CGP-NEXT: v_cvt_f32_u32_e32 v0, v5
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc
-; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v0
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CGP-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v2, v2
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
-; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
+; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CGP-NEXT: v_trunc_f32_e32 v1, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CGP-NEXT: v_cvt_u32_f32_e32 v1, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CGP-NEXT: v_mul_lo_u32 v12, v1, v2
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v12, v2, v1
+; CGP-NEXT: v_mul_lo_u32 v13, v2, v0
; CGP-NEXT: v_mul_lo_u32 v14, v3, v0
-; CGP-NEXT: v_mul_hi_u32 v15, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v15, v2, v0
; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12
-; CGP-NEXT: v_mul_lo_u32 v14, v2, v13
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v13
; CGP-NEXT: v_mul_hi_u32 v16, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v2, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_mul_lo_u32 v15, v0, v12
-; CGP-NEXT: v_mul_lo_u32 v17, v2, v12
+; CGP-NEXT: v_mul_lo_u32 v17, v1, v12
; CGP-NEXT: v_mul_hi_u32 v18, v0, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v2, v12
+; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v17, v13
@@ -669,20 +669,20 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
-; CGP-NEXT: v_addc_u32_e32 v2, vcc, v2, v12, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, v1, v0
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
+; CGP-NEXT: v_mul_lo_u32 v12, v2, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
-; CGP-NEXT: v_mul_hi_u32 v13, v1, v0
-; CGP-NEXT: v_mul_lo_u32 v1, v1, v2
-; CGP-NEXT: v_mul_lo_u32 v14, v2, v12
+; CGP-NEXT: v_mul_hi_u32 v13, v2, v0
+; CGP-NEXT: v_mul_lo_u32 v2, v2, v1
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v2, v12
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v13
-; CGP-NEXT: v_mul_lo_u32 v3, v0, v1
-; CGP-NEXT: v_mul_lo_u32 v13, v2, v1
-; CGP-NEXT: v_mul_hi_u32 v16, v0, v1
-; CGP-NEXT: v_mul_hi_u32 v1, v2, v1
+; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v13
+; CGP-NEXT: v_mul_lo_u32 v3, v0, v2
+; CGP-NEXT: v_mul_lo_u32 v13, v1, v2
+; CGP-NEXT: v_mul_hi_u32 v16, v0, v2
+; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
@@ -696,9 +696,9 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v3, vcc, v12, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v12
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v2, v11, v0
; CGP-NEXT: v_mul_hi_u32 v3, v10, v0
; CGP-NEXT: v_mul_hi_u32 v0, v11, v0
@@ -754,16 +754,16 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CGP-NEXT: ; implicit-def: $vgpr2
; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: .LBB2_2: ; %Flow1
; CGP-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_mov_b32_e32 v1, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v2, v2, v0
@@ -780,12 +780,11 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; CGP-NEXT: .LBB2_4:
+; CGP-NEXT: .LBB2_4: ; %.split
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -793,34 +792,35 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; %bb.5: ; %Flow
; CGP-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_cbranch_execnz .LBB2_8
-; CGP-NEXT: .LBB2_6:
+; CGP-NEXT: .LBB2_6: ; %.split.split
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31]
; CGP-NEXT: .LBB2_7:
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v7
-; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
+; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v2
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; CGP-NEXT: v_trunc_f32_e32 v3, v3
+; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CGP-NEXT: v_mul_lo_u32 v10, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v11, v3, v2
+; CGP-NEXT: v_mul_lo_u32 v10, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v12, v5, v2
-; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v13, v4, v2
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v11
; CGP-NEXT: v_mul_hi_u32 v14, v2, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v4, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v3, v11
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_mul_lo_u32 v13, v2, v10
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v10
+; CGP-NEXT: v_mul_lo_u32 v15, v3, v10
; CGP-NEXT: v_mul_hi_u32 v16, v2, v10
-; CGP-NEXT: v_mul_hi_u32 v10, v4, v10
+; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v15, v11
@@ -836,20 +836,20 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v10, vcc
-; CGP-NEXT: v_mul_lo_u32 v10, v3, v2
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT: v_mul_lo_u32 v10, v4, v2
; CGP-NEXT: v_mul_lo_u32 v5, v5, v2
-; CGP-NEXT: v_mul_hi_u32 v11, v3, v2
-; CGP-NEXT: v_mul_lo_u32 v3, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v10
+; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v10
; CGP-NEXT: v_mul_hi_u32 v13, v2, v10
-; CGP-NEXT: v_mul_hi_u32 v10, v4, v10
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v11
-; CGP-NEXT: v_mul_lo_u32 v5, v2, v3
-; CGP-NEXT: v_mul_lo_u32 v11, v4, v3
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v3, v4, v3
+; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v5, v2, v4
+; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
+; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
@@ -863,9 +863,9 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v2
; CGP-NEXT: v_mul_hi_u32 v5, v8, v2
; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
@@ -921,15 +921,15 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: .LBB2_8:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_mov_b32_e32 v3, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v2
@@ -1069,11 +1069,10 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_mov_b32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v0, 0x1000
; CHECK-NEXT: v_mov_b32_e32 v1, 0
-; CHECK-NEXT: v_mov_b32_e32 v7, 0
; CHECK-NEXT: v_lshl_b64 v[5:6], v[0:1], v2
-; CHECK-NEXT: v_or_b32_e32 v8, v4, v6
-; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v5
+; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -1081,34 +1080,35 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: ; %bb.1: ; %Flow
; CHECK-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_cbranch_execnz .LBB7_4
-; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: .LBB7_2: ; %.split
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .LBB7_3:
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v6
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6
+; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v0
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
-; CHECK-NEXT: v_trunc_f32_e32 v2, v2
-; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
-; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
+; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v2
-; CHECK-NEXT: v_mul_lo_u32 v9, v1, v0
+; CHECK-NEXT: v_mul_lo_u32 v8, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v9, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v11, v1, v0
+; CHECK-NEXT: v_mul_hi_u32 v11, v2, v0
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; CHECK-NEXT: v_mul_lo_u32 v10, v2, v9
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v9
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v9, v2, v9
+; CHECK-NEXT: v_mul_hi_u32 v9, v1, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_mul_lo_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_lo_u32 v13, v2, v8
+; CHECK-NEXT: v_mul_lo_u32 v13, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v14, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v2, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
@@ -1124,20 +1124,20 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v0
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v9, v1, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2
-; CHECK-NEXT: v_mul_lo_u32 v10, v2, v8
+; CHECK-NEXT: v_mul_hi_u32 v9, v2, v0
+; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v2, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v7, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v1
-; CHECK-NEXT: v_mul_lo_u32 v9, v2, v1
-; CHECK-NEXT: v_mul_hi_u32 v12, v0, v1
-; CHECK-NEXT: v_mul_hi_u32 v1, v2, v1
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v9
+; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
+; CHECK-NEXT: v_mul_lo_u32 v9, v1, v2
+; CHECK-NEXT: v_mul_hi_u32 v12, v0, v2
+; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
@@ -1151,9 +1151,9 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
@@ -1209,15 +1209,15 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: .LBB7_4:
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v0
@@ -1510,40 +1510,40 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_mov_b32_e32 v7, v3
; CGP-NEXT: v_mov_b32_e32 v10, 0x1000
; CGP-NEXT: v_mov_b32_e32 v11, 0
-; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_lshl_b64 v[2:3], v[10:11], v4
; CGP-NEXT: v_or_b32_e32 v1, v9, v3
+; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1:
-; CGP-NEXT: v_cvt_f32_u32_e32 v0, v3
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v3, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v0
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v4
+; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CGP-NEXT: v_trunc_f32_e32 v1, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CGP-NEXT: v_cvt_u32_f32_e32 v1, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v4
-; CGP-NEXT: v_mul_lo_u32 v14, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v13, v4, v1
+; CGP-NEXT: v_mul_lo_u32 v14, v4, v0
; CGP-NEXT: v_mul_lo_u32 v15, v12, v0
-; CGP-NEXT: v_mul_hi_u32 v16, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v16, v4, v0
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v14
+; CGP-NEXT: v_mul_lo_u32 v15, v1, v14
; CGP-NEXT: v_mul_hi_u32 v17, v0, v14
-; CGP-NEXT: v_mul_hi_u32 v14, v4, v14
+; CGP-NEXT: v_mul_hi_u32 v14, v1, v14
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_mul_lo_u32 v16, v0, v13
-; CGP-NEXT: v_mul_lo_u32 v18, v4, v13
+; CGP-NEXT: v_mul_lo_u32 v18, v1, v13
; CGP-NEXT: v_mul_hi_u32 v19, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v4, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v18, v14
@@ -1559,20 +1559,20 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v13, vcc
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v0
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CGP-NEXT: v_mul_lo_u32 v13, v4, v0
; CGP-NEXT: v_mul_lo_u32 v12, v12, v0
-; CGP-NEXT: v_mul_hi_u32 v14, v1, v0
-; CGP-NEXT: v_mul_lo_u32 v1, v1, v4
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v13
+; CGP-NEXT: v_mul_hi_u32 v14, v4, v0
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v1
+; CGP-NEXT: v_mul_lo_u32 v15, v1, v13
; CGP-NEXT: v_mul_hi_u32 v16, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v4, v13
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v14
-; CGP-NEXT: v_mul_lo_u32 v12, v0, v1
-; CGP-NEXT: v_mul_lo_u32 v14, v4, v1
-; CGP-NEXT: v_mul_hi_u32 v17, v0, v1
-; CGP-NEXT: v_mul_hi_u32 v1, v4, v1
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v12, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v14
+; CGP-NEXT: v_mul_lo_u32 v12, v0, v4
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v4
+; CGP-NEXT: v_mul_hi_u32 v17, v0, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
@@ -1586,9 +1586,9 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v13
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v13
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v12
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v0
; CGP-NEXT: v_mul_hi_u32 v12, v8, v0
; CGP-NEXT: v_mul_hi_u32 v0, v9, v0
@@ -1644,7 +1644,6 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: .LBB8_2: ; %Flow1
@@ -1653,9 +1652,10 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: s_xor_b64 exec, exec, s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; CGP-NEXT: v_mov_b32_e32 v1, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
@@ -1672,12 +1672,11 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v3, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; CGP-NEXT: .LBB8_4:
+; CGP-NEXT: .LBB8_4: ; %.split
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: v_or_b32_e32 v3, v7, v10
; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v9
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -1685,34 +1684,35 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; %bb.5: ; %Flow
; CGP-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_cbranch_execnz .LBB8_8
-; CGP-NEXT: .LBB8_6:
+; CGP-NEXT: .LBB8_6: ; %.split.split
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
; CGP-NEXT: s_setpc_b64 s[30:31]
; CGP-NEXT: .LBB8_7:
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
-; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v9
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v9
+; CGP-NEXT: v_cvt_f32_u32_e32 v3, v10
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v9
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v10, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v2
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; CGP-NEXT: v_trunc_f32_e32 v3, v3
+; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CGP-NEXT: v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v11, v3, v2
+; CGP-NEXT: v_mul_lo_u32 v8, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v12, v6, v2
-; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v13, v4, v2
; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v11
; CGP-NEXT: v_mul_hi_u32 v14, v2, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v4, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v3, v11
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; CGP-NEXT: v_mul_lo_u32 v13, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v8
+; CGP-NEXT: v_mul_lo_u32 v15, v3, v8
; CGP-NEXT: v_mul_hi_u32 v16, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v8, v4, v8
+; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v15, v11
@@ -1728,20 +1728,20 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
-; CGP-NEXT: v_mul_lo_u32 v8, v3, v2
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_mul_lo_u32 v8, v4, v2
; CGP-NEXT: v_mul_lo_u32 v6, v6, v2
-; CGP-NEXT: v_mul_hi_u32 v11, v3, v2
-; CGP-NEXT: v_mul_lo_u32 v3, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v8
+; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v8
; CGP-NEXT: v_mul_hi_u32 v13, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v8, v4, v8
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v11
-; CGP-NEXT: v_mul_lo_u32 v6, v2, v3
-; CGP-NEXT: v_mul_lo_u32 v11, v4, v3
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v3, v4, v3
+; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v6, v2, v4
+; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
+; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v11, v8
@@ -1755,9 +1755,9 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v11, v8
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v7, v2
; CGP-NEXT: v_mul_hi_u32 v6, v5, v2
; CGP-NEXT: v_mul_hi_u32 v2, v7, v2
@@ -1813,15 +1813,15 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr9_vgpr10
; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: .LBB8_8:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v9
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v9
; CGP-NEXT: v_mov_b32_e32 v3, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
index be5543b9b5b7f..a1db891c5703c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
@@ -13,7 +13,6 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_or_b32_e32 v1, v5, v3
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v2
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -21,34 +20,35 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: ; %bb.1: ; %Flow
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_cbranch_execnz .LBB0_4
-; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: .LBB0_2: ; %.split
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .LBB0_3:
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v3
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v3
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
-; CHECK-NEXT: v_mac_f32_e32 v6, 0x4f800000, v0
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v6
+; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v0
-; CHECK-NEXT: v_trunc_f32_e32 v6, v6
-; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v6
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v6
-; CHECK-NEXT: v_mul_lo_u32 v9, v1, v0
+; CHECK-NEXT: v_mul_lo_u32 v8, v6, v1
+; CHECK-NEXT: v_mul_lo_u32 v9, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v11, v1, v0
+; CHECK-NEXT: v_mul_hi_u32 v11, v6, v0
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; CHECK-NEXT: v_mul_lo_u32 v10, v6, v9
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v9
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT: v_mul_hi_u32 v9, v1, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_mul_lo_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_lo_u32 v13, v6, v8
+; CHECK-NEXT: v_mul_lo_u32 v13, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v14, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
@@ -64,20 +64,20 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v0
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v9, v1, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v1, v6
-; CHECK-NEXT: v_mul_lo_u32 v10, v6, v8
+; CHECK-NEXT: v_mul_hi_u32 v9, v6, v0
+; CHECK-NEXT: v_mul_lo_u32 v6, v6, v1
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v7, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v1
-; CHECK-NEXT: v_mul_lo_u32 v9, v6, v1
-; CHECK-NEXT: v_mul_hi_u32 v12, v0, v1
-; CHECK-NEXT: v_mul_hi_u32 v1, v6, v1
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6
+; CHECK-NEXT: v_mul_lo_u32 v9, v1, v6
+; CHECK-NEXT: v_mul_hi_u32 v12, v0, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
@@ -91,9 +91,9 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
@@ -148,15 +148,15 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; CHECK-NEXT: ; implicit-def: $vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v6
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
; CHECK-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v3, v3, v0
@@ -336,7 +336,7 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: .LBB1_5:
+; CHECK-NEXT: .LBB1_5: ; %.split
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: ; return to shader part epilog
@@ -616,36 +616,36 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_or_b32_e32 v1, v11, v5
; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v4
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz .LBB2_2
; CGP-NEXT: ; %bb.1:
-; CGP-NEXT: v_cvt_f32_u32_e32 v0, v5
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc
-; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v0
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CGP-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v2, v2
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
-; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
+; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CGP-NEXT: v_trunc_f32_e32 v1, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CGP-NEXT: v_cvt_u32_f32_e32 v1, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CGP-NEXT: v_mul_lo_u32 v12, v1, v2
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v12, v2, v1
+; CGP-NEXT: v_mul_lo_u32 v13, v2, v0
; CGP-NEXT: v_mul_lo_u32 v14, v3, v0
-; CGP-NEXT: v_mul_hi_u32 v15, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v15, v2, v0
; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12
-; CGP-NEXT: v_mul_lo_u32 v14, v2, v13
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v13
; CGP-NEXT: v_mul_hi_u32 v16, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v2, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_mul_lo_u32 v15, v0, v12
-; CGP-NEXT: v_mul_lo_u32 v17, v2, v12
+; CGP-NEXT: v_mul_lo_u32 v17, v1, v12
; CGP-NEXT: v_mul_hi_u32 v18, v0, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v2, v12
+; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v17, v13
@@ -661,20 +661,20 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
-; CGP-NEXT: v_addc_u32_e32 v2, vcc, v2, v12, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, v1, v0
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
+; CGP-NEXT: v_mul_lo_u32 v12, v2, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
-; CGP-NEXT: v_mul_hi_u32 v13, v1, v0
-; CGP-NEXT: v_mul_lo_u32 v1, v1, v2
-; CGP-NEXT: v_mul_lo_u32 v14, v2, v12
+; CGP-NEXT: v_mul_hi_u32 v13, v2, v0
+; CGP-NEXT: v_mul_lo_u32 v2, v2, v1
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v2, v12
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v13
-; CGP-NEXT: v_mul_lo_u32 v3, v0, v1
-; CGP-NEXT: v_mul_lo_u32 v13, v2, v1
-; CGP-NEXT: v_mul_hi_u32 v16, v0, v1
-; CGP-NEXT: v_mul_hi_u32 v1, v2, v1
+; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v13
+; CGP-NEXT: v_mul_lo_u32 v3, v0, v2
+; CGP-NEXT: v_mul_lo_u32 v13, v1, v2
+; CGP-NEXT: v_mul_hi_u32 v16, v0, v2
+; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
@@ -688,9 +688,9 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v3, vcc, v12, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v12
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v2, v11, v0
; CGP-NEXT: v_mul_hi_u32 v3, v10, v0
; CGP-NEXT: v_mul_hi_u32 v0, v11, v0
@@ -745,16 +745,16 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; CGP-NEXT: ; implicit-def: $vgpr2
; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: .LBB2_2: ; %Flow1
; CGP-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB2_4
; CGP-NEXT: ; %bb.3:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; CGP-NEXT: v_mov_b32_e32 v1, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v2, v2, v0
@@ -769,12 +769,11 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CGP-NEXT: .LBB2_4:
+; CGP-NEXT: .LBB2_4: ; %.split
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v9, v7
; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -782,34 +781,35 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; %bb.5: ; %Flow
; CGP-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_cbranch_execnz .LBB2_8
-; CGP-NEXT: .LBB2_6:
+; CGP-NEXT: .LBB2_6: ; %.split.split
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31]
; CGP-NEXT: .LBB2_7:
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v7
-; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v6
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
+; CGP-NEXT: v_cvt_f32_u32_e32 v3, v7
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_subb_u32_e32 v5, vcc, 0, v7, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v2
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; CGP-NEXT: v_trunc_f32_e32 v3, v3
+; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CGP-NEXT: v_mul_lo_u32 v10, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v11, v3, v2
+; CGP-NEXT: v_mul_lo_u32 v10, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v12, v5, v2
-; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v13, v4, v2
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v11
; CGP-NEXT: v_mul_hi_u32 v14, v2, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v4, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v3, v11
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_mul_lo_u32 v13, v2, v10
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v10
+; CGP-NEXT: v_mul_lo_u32 v15, v3, v10
; CGP-NEXT: v_mul_hi_u32 v16, v2, v10
-; CGP-NEXT: v_mul_hi_u32 v10, v4, v10
+; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v15, v11
@@ -825,20 +825,20 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v10, vcc
-; CGP-NEXT: v_mul_lo_u32 v10, v3, v2
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT: v_mul_lo_u32 v10, v4, v2
; CGP-NEXT: v_mul_lo_u32 v5, v5, v2
-; CGP-NEXT: v_mul_hi_u32 v11, v3, v2
-; CGP-NEXT: v_mul_lo_u32 v3, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v10
+; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v10
; CGP-NEXT: v_mul_hi_u32 v13, v2, v10
-; CGP-NEXT: v_mul_hi_u32 v10, v4, v10
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v11
-; CGP-NEXT: v_mul_lo_u32 v5, v2, v3
-; CGP-NEXT: v_mul_lo_u32 v11, v4, v3
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v3, v4, v3
+; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v5, v2, v4
+; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
+; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
@@ -852,9 +852,9 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v10
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v2
; CGP-NEXT: v_mul_hi_u32 v5, v8, v2
; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
@@ -909,15 +909,15 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB2_6
; CGP-NEXT: .LBB2_8:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v6
; CGP-NEXT: v_mov_b32_e32 v3, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v2
@@ -1078,11 +1078,10 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_mov_b32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v0, 0x1000
; CHECK-NEXT: v_mov_b32_e32 v1, 0
-; CHECK-NEXT: v_mov_b32_e32 v7, 0
; CHECK-NEXT: v_lshl_b64 v[5:6], v[0:1], v2
-; CHECK-NEXT: v_or_b32_e32 v8, v4, v6
-; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8]
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v5
+; CHECK-NEXT: v_or_b32_e32 v1, v4, v6
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -1090,34 +1089,35 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: ; %bb.1: ; %Flow
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_cbranch_execnz .LBB7_4
-; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: .LBB7_2: ; %.split
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_setpc_b64 s[30:31]
; CHECK-NEXT: .LBB7_3:
-; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v6
-; CHECK-NEXT: v_sub_i32_e32 v1, vcc, 0, v5
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
+; CHECK-NEXT: v_cvt_f32_u32_e32 v1, v6
+; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v6, vcc
-; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v0
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
-; CHECK-NEXT: v_trunc_f32_e32 v2, v2
-; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
-; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
+; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CHECK-NEXT: v_trunc_f32_e32 v1, v1
+; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v2
-; CHECK-NEXT: v_mul_lo_u32 v9, v1, v0
+; CHECK-NEXT: v_mul_lo_u32 v8, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v9, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v11, v1, v0
+; CHECK-NEXT: v_mul_hi_u32 v11, v2, v0
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; CHECK-NEXT: v_mul_lo_u32 v10, v2, v9
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v9
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v9
-; CHECK-NEXT: v_mul_hi_u32 v9, v2, v9
+; CHECK-NEXT: v_mul_hi_u32 v9, v1, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_mul_lo_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_lo_u32 v13, v2, v8
+; CHECK-NEXT: v_mul_lo_u32 v13, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v14, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v2, v8
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
@@ -1133,20 +1133,20 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
-; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc
-; CHECK-NEXT: v_mul_lo_u32 v8, v1, v0
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
-; CHECK-NEXT: v_mul_hi_u32 v9, v1, v0
-; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2
-; CHECK-NEXT: v_mul_lo_u32 v10, v2, v8
+; CHECK-NEXT: v_mul_hi_u32 v9, v2, v0
+; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
+; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v2, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v7, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v9
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v1
-; CHECK-NEXT: v_mul_lo_u32 v9, v2, v1
-; CHECK-NEXT: v_mul_hi_u32 v12, v0, v1
-; CHECK-NEXT: v_mul_hi_u32 v1, v2, v1
+; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v9
+; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
+; CHECK-NEXT: v_mul_lo_u32 v9, v1, v2
+; CHECK-NEXT: v_mul_hi_u32 v12, v0, v2
+; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
@@ -1160,9 +1160,9 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v8
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
@@ -1217,15 +1217,15 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB7_2
; CHECK-NEXT: .LBB7_4:
-; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v2
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, 0, v5
; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v0
@@ -1514,40 +1514,40 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_mov_b32_e32 v7, v3
; CGP-NEXT: v_mov_b32_e32 v10, 0x1000
; CGP-NEXT: v_mov_b32_e32 v11, 0
-; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_lshl_b64 v[2:3], v[10:11], v4
; CGP-NEXT: v_or_b32_e32 v1, v9, v3
+; CGP-NEXT: v_mov_b32_e32 v0, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz .LBB8_2
; CGP-NEXT: ; %bb.1:
-; CGP-NEXT: v_cvt_f32_u32_e32 v0, v3
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
+; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v3, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v0
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v4
+; CGP-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; CGP-NEXT: v_trunc_f32_e32 v1, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; CGP-NEXT: v_cvt_u32_f32_e32 v1, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v4
-; CGP-NEXT: v_mul_lo_u32 v14, v1, v0
+; CGP-NEXT: v_mul_lo_u32 v13, v4, v1
+; CGP-NEXT: v_mul_lo_u32 v14, v4, v0
; CGP-NEXT: v_mul_lo_u32 v15, v12, v0
-; CGP-NEXT: v_mul_hi_u32 v16, v1, v0
+; CGP-NEXT: v_mul_hi_u32 v16, v4, v0
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v14
+; CGP-NEXT: v_mul_lo_u32 v15, v1, v14
; CGP-NEXT: v_mul_hi_u32 v17, v0, v14
-; CGP-NEXT: v_mul_hi_u32 v14, v4, v14
+; CGP-NEXT: v_mul_hi_u32 v14, v1, v14
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_mul_lo_u32 v16, v0, v13
-; CGP-NEXT: v_mul_lo_u32 v18, v4, v13
+; CGP-NEXT: v_mul_lo_u32 v18, v1, v13
; CGP-NEXT: v_mul_hi_u32 v19, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v4, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v18, v14
@@ -1563,20 +1563,20 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v13, vcc
-; CGP-NEXT: v_mul_lo_u32 v13, v1, v0
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CGP-NEXT: v_mul_lo_u32 v13, v4, v0
; CGP-NEXT: v_mul_lo_u32 v12, v12, v0
-; CGP-NEXT: v_mul_hi_u32 v14, v1, v0
-; CGP-NEXT: v_mul_lo_u32 v1, v1, v4
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v13
+; CGP-NEXT: v_mul_hi_u32 v14, v4, v0
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v1
+; CGP-NEXT: v_mul_lo_u32 v15, v1, v13
; CGP-NEXT: v_mul_hi_u32 v16, v0, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v4, v13
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v14
-; CGP-NEXT: v_mul_lo_u32 v12, v0, v1
-; CGP-NEXT: v_mul_lo_u32 v14, v4, v1
-; CGP-NEXT: v_mul_hi_u32 v17, v0, v1
-; CGP-NEXT: v_mul_hi_u32 v1, v4, v1
+; CGP-NEXT: v_mul_hi_u32 v13, v1, v13
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v12, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v14
+; CGP-NEXT: v_mul_lo_u32 v12, v0, v4
+; CGP-NEXT: v_mul_lo_u32 v14, v1, v4
+; CGP-NEXT: v_mul_hi_u32 v17, v0, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
@@ -1590,9 +1590,9 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v13
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v13
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v12
-; CGP-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
+; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v0
; CGP-NEXT: v_mul_hi_u32 v12, v8, v0
; CGP-NEXT: v_mul_hi_u32 v0, v9, v0
@@ -1647,7 +1647,6 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: .LBB8_2: ; %Flow1
@@ -1656,9 +1655,10 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz .LBB8_4
; CGP-NEXT: ; %bb.3:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; CGP-NEXT: v_mov_b32_e32 v1, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
@@ -1673,12 +1673,11 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v0, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; CGP-NEXT: .LBB8_4:
+; CGP-NEXT: .LBB8_4: ; %.split
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: v_or_b32_e32 v3, v7, v10
; CGP-NEXT: v_mov_b32_e32 v2, 0
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; CGP-NEXT: v_cvt_f32_u32_e32 v4, v9
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
@@ -1686,34 +1685,35 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; %bb.5: ; %Flow
; CGP-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_cbranch_execnz .LBB8_8
-; CGP-NEXT: .LBB8_6:
+; CGP-NEXT: .LBB8_6: ; %.split.split
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31]
; CGP-NEXT: .LBB8_7:
-; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
-; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v9
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v9
+; CGP-NEXT: v_cvt_f32_u32_e32 v3, v10
+; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v9
; CGP-NEXT: v_subb_u32_e32 v6, vcc, 0, v10, vcc
-; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v2
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CGP-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
-; CGP-NEXT: v_trunc_f32_e32 v4, v4
-; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
-; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; CGP-NEXT: v_trunc_f32_e32 v3, v3
+; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CGP-NEXT: v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v11, v3, v2
+; CGP-NEXT: v_mul_lo_u32 v8, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v12, v6, v2
-; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
+; CGP-NEXT: v_mul_hi_u32 v13, v4, v2
; CGP-NEXT: v_add_i32_e32 v8, vcc, v12, v8
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v11
; CGP-NEXT: v_mul_hi_u32 v14, v2, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v4, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v3, v11
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; CGP-NEXT: v_mul_lo_u32 v13, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v15, v4, v8
+; CGP-NEXT: v_mul_lo_u32 v15, v3, v8
; CGP-NEXT: v_mul_hi_u32 v16, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v8, v4, v8
+; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v15, v11
@@ -1729,20 +1729,20 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
-; CGP-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
-; CGP-NEXT: v_mul_lo_u32 v8, v3, v2
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_mul_lo_u32 v8, v4, v2
; CGP-NEXT: v_mul_lo_u32 v6, v6, v2
-; CGP-NEXT: v_mul_hi_u32 v11, v3, v2
-; CGP-NEXT: v_mul_lo_u32 v3, v3, v4
-; CGP-NEXT: v_mul_lo_u32 v12, v4, v8
+; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
+; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
+; CGP-NEXT: v_mul_lo_u32 v12, v3, v8
; CGP-NEXT: v_mul_hi_u32 v13, v2, v8
-; CGP-NEXT: v_mul_hi_u32 v8, v4, v8
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v11
-; CGP-NEXT: v_mul_lo_u32 v6, v2, v3
-; CGP-NEXT: v_mul_lo_u32 v11, v4, v3
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v3
-; CGP-NEXT: v_mul_hi_u32 v3, v4, v3
+; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT: v_mul_lo_u32 v6, v2, v4
+; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
+; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
+; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v11, v8
@@ -1756,9 +1756,9 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v11, v8
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v7, v2
; CGP-NEXT: v_mul_hi_u32 v6, v5, v2
; CGP-NEXT: v_mul_hi_u32 v2, v7, v2
@@ -1813,15 +1813,15 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
-; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr9_vgpr10
; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_cbranch_execz .LBB8_6
; CGP-NEXT: .LBB8_8:
-; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; CGP-NEXT: v_cvt_f32_u32_e32 v2, v9
; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v9
; CGP-NEXT: v_mov_b32_e32 v3, 0
+; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
index e677bbf680ab4..d63b29be67366 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
@@ -6,34 +6,37 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX906-NEXT: v_mov_b32_e32 v3, 8
-; GFX906-NEXT: v_mov_b32_e32 v5, 16
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; GFX906-NEXT: v_mov_b32_e32 v2, 8
+; GFX906-NEXT: v_mov_b32_e32 v3, 16
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dword v4, v2, s[0:1]
-; GFX906-NEXT: v_mov_b32_e32 v1, 0xff
+; GFX906-NEXT: global_load_dword v1, v1, s[0:1]
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: v_and_b32_e32 v6, 0xff, v4
-; GFX906-NEXT: v_lshlrev_b32_sdwa v7, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX906-NEXT: v_lshlrev_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX906-NEXT: v_or3_b32 v4, v6, v7, v4
+; GFX906-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX906-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX906-NEXT: v_or3_b32 v1, v4, v2, v1
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB0_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dword v0, v2, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX906-NEXT: global_load_dword v0, v0, s[2:3]
+; GFX906-NEXT: v_mov_b32_e32 v1, 8
+; GFX906-NEXT: v_mov_b32_e32 v2, 16
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX906-NEXT: v_lshlrev_b32_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX906-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX906-NEXT: v_or3_b32 v4, v2, v3, v0
+; GFX906-NEXT: v_and_b32_e32 v3, 0xff, v0
+; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX906-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX906-NEXT: v_or3_b32 v1, v3, v1, v0
; GFX906-NEXT: .LBB0_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX906-NEXT: v_lshrrev_b32_e32 v0, 8, v4
+; GFX906-NEXT: v_lshrrev_b32_e32 v0, 8, v1
; GFX906-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xff
; GFX906-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX906-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX906-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX906-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX906-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
@@ -63,14 +66,15 @@ define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dword v1, v2, s[0:1]
+; GFX906-NEXT: global_load_dword v1, v1, s[0:1]
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB1_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dword v1, v2, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX906-NEXT: global_load_dword v1, v0, s[2:3]
; GFX906-NEXT: .LBB1_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: v_mov_b32_e32 v0, 0
@@ -99,16 +103,17 @@ define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v3, 3, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[0:1]
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v1, s[0:1]
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB2_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v0, s[2:3]
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX906-NEXT: .LBB2_2: ; %bb.2
@@ -144,14 +149,15 @@ define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v3, 3, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[0:1]
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v1, s[0:1]
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB3_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v0, s[2:3]
; GFX906-NEXT: .LBB3_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: v_mov_b32_e32 v0, 0
@@ -180,14 +186,15 @@ define amdgpu_kernel void @v16i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v5, 4, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 4, v0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx4 v[1:4], v5, s[0:1]
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v1, s[0:1]
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB4_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx4 v[1:4], v5, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v0, s[2:3]
; GFX906-NEXT: .LBB4_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: v_mov_b32_e32 v0, 0
@@ -224,8 +231,9 @@ define amdgpu_kernel void @v32i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB5_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx4 v[1:4], v9, s[2:3]
-; GFX906-NEXT: global_load_dwordx4 v[5:8], v9, s[2:3] offset:16
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v0, s[2:3]
+; GFX906-NEXT: global_load_dwordx4 v[5:8], v0, s[2:3] offset:16
; GFX906-NEXT: .LBB5_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: v_mov_b32_e32 v0, 0
@@ -256,74 +264,77 @@ define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX906-NEXT: v_lshlrev_b32_e32 v4, 3, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GFX906-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX906-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx4 v[5:8], v4, s[0:1]
+; GFX906-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1]
; GFX906-NEXT: s_mov_b32 s14, -1
; GFX906-NEXT: s_mov_b32 s15, 0xe00000
; GFX906-NEXT: s_add_u32 s12, s12, s11
; GFX906-NEXT: s_addc_u32 s13, s13, 0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: buffer_store_dword v5, off, s[12:15], 0 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v2, off, s[12:15], 0 ; 4-byte Folded Spill
+; GFX906-NEXT: s_nop 0
+; GFX906-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v4, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v5, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
+; GFX906-NEXT: global_load_dwordx4 v[5:8], v1, s[0:1] offset:16
+; GFX906-NEXT: s_nop 0
+; GFX906-NEXT: global_load_dwordx4 v[9:12], v1, s[0:1] offset:32
+; GFX906-NEXT: global_load_dwordx4 v[13:16], v1, s[0:1] offset:48
+; GFX906-NEXT: global_load_dwordx4 v[17:20], v1, s[0:1] offset:64
+; GFX906-NEXT: global_load_dwordx4 v[21:24], v1, s[0:1] offset:80
+; GFX906-NEXT: global_load_dwordx4 v[25:28], v1, s[0:1] offset:96
+; GFX906-NEXT: global_load_dwordx4 v[29:32], v1, s[0:1] offset:112
+; GFX906-NEXT: global_load_dwordx4 v[33:36], v1, s[0:1] offset:128
+; GFX906-NEXT: global_load_dwordx4 v[37:40], v1, s[0:1] offset:144
+; GFX906-NEXT: global_load_dwordx4 v[41:44], v1, s[0:1] offset:160
+; GFX906-NEXT: global_load_dwordx4 v[45:48], v1, s[0:1] offset:176
+; GFX906-NEXT: global_load_dwordx4 v[49:52], v1, s[0:1] offset:192
+; GFX906-NEXT: global_load_dwordx4 v[53:56], v1, s[0:1] offset:208
+; GFX906-NEXT: global_load_dwordx4 v[57:60], v1, s[0:1] offset:224
; GFX906-NEXT: s_nop 0
-; GFX906-NEXT: buffer_store_dword v6, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v7, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v8, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
-; GFX906-NEXT: global_load_dwordx4 v[17:20], v4, s[0:1] offset:64
-; GFX906-NEXT: global_load_dwordx4 v[21:24], v4, s[0:1] offset:80
-; GFX906-NEXT: global_load_dwordx4 v[25:28], v4, s[0:1] offset:96
-; GFX906-NEXT: global_load_dwordx4 v[29:32], v4, s[0:1] offset:112
-; GFX906-NEXT: global_load_dwordx4 v[33:36], v4, s[0:1] offset:128
-; GFX906-NEXT: global_load_dwordx4 v[37:40], v4, s[0:1] offset:144
-; GFX906-NEXT: global_load_dwordx4 v[41:44], v4, s[0:1] offset:160
-; GFX906-NEXT: global_load_dwordx4 v[45:48], v4, s[0:1] offset:176
-; GFX906-NEXT: global_load_dwordx4 v[49:52], v4, s[0:1] offset:192
-; GFX906-NEXT: global_load_dwordx4 v[53:56], v4, s[0:1] offset:208
-; GFX906-NEXT: global_load_dwordx4 v[57:60], v4, s[0:1] offset:224
-; GFX906-NEXT: global_load_dwordx4 v[0:3], v4, s[0:1] offset:240
-; GFX906-NEXT: global_load_dwordx4 v[5:8], v4, s[0:1] offset:16
-; GFX906-NEXT: global_load_dwordx4 v[9:12], v4, s[0:1] offset:32
-; GFX906-NEXT: global_load_dwordx4 v[13:16], v4, s[0:1] offset:48
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v1, s[0:1] offset:240
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB6_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
+; GFX906-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v0, s[2:3]
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v1, off, s[12:15], 0 ; 4-byte Folded Spill
; GFX906-NEXT: s_nop 0
-; GFX906-NEXT: buffer_store_dword v1, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v2, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
-; GFX906-NEXT: global_load_dwordx4 v[5:8], v4, s[2:3] offset:16
-; GFX906-NEXT: global_load_dwordx4 v[9:12], v4, s[2:3] offset:32
-; GFX906-NEXT: global_load_dwordx4 v[13:16], v4, s[2:3] offset:48
-; GFX906-NEXT: global_load_dwordx4 v[17:20], v4, s[2:3] offset:64
-; GFX906-NEXT: global_load_dwordx4 v[21:24], v4, s[2:3] offset:80
-; GFX906-NEXT: global_load_dwordx4 v[25:28], v4, s[2:3] offset:96
-; GFX906-NEXT: global_load_dwordx4 v[29:32], v4, s[2:3] offset:112
-; GFX906-NEXT: global_load_dwordx4 v[33:36], v4, s[2:3] offset:128
-; GFX906-NEXT: global_load_dwordx4 v[37:40], v4, s[2:3] offset:144
-; GFX906-NEXT: global_load_dwordx4 v[41:44], v4, s[2:3] offset:160
-; GFX906-NEXT: global_load_dwordx4 v[45:48], v4, s[2:3] offset:176
-; GFX906-NEXT: global_load_dwordx4 v[49:52], v4, s[2:3] offset:192
-; GFX906-NEXT: global_load_dwordx4 v[53:56], v4, s[2:3] offset:208
-; GFX906-NEXT: global_load_dwordx4 v[57:60], v4, s[2:3] offset:224
-; GFX906-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3] offset:240
+; GFX906-NEXT: buffer_store_dword v2, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:8 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v4, off, s[12:15], 0 offset:12 ; 4-byte Folded Spill
+; GFX906-NEXT: global_load_dwordx4 v[5:8], v0, s[2:3] offset:16
+; GFX906-NEXT: global_load_dwordx4 v[9:12], v0, s[2:3] offset:32
+; GFX906-NEXT: global_load_dwordx4 v[13:16], v0, s[2:3] offset:48
+; GFX906-NEXT: global_load_dwordx4 v[17:20], v0, s[2:3] offset:64
+; GFX906-NEXT: global_load_dwordx4 v[21:24], v0, s[2:3] offset:80
+; GFX906-NEXT: global_load_dwordx4 v[25:28], v0, s[2:3] offset:96
+; GFX906-NEXT: global_load_dwordx4 v[29:32], v0, s[2:3] offset:112
+; GFX906-NEXT: global_load_dwordx4 v[33:36], v0, s[2:3] offset:128
+; GFX906-NEXT: global_load_dwordx4 v[37:40], v0, s[2:3] offset:144
+; GFX906-NEXT: global_load_dwordx4 v[41:44], v0, s[2:3] offset:160
+; GFX906-NEXT: global_load_dwordx4 v[45:48], v0, s[2:3] offset:176
+; GFX906-NEXT: global_load_dwordx4 v[49:52], v0, s[2:3] offset:192
+; GFX906-NEXT: global_load_dwordx4 v[53:56], v0, s[2:3] offset:208
+; GFX906-NEXT: global_load_dwordx4 v[57:60], v0, s[2:3] offset:224
+; GFX906-NEXT: global_load_dwordx4 v[1:4], v0, s[2:3] offset:240
; GFX906-NEXT: .LBB6_2: ; %bb.2
; GFX906-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: buffer_store_dword v0, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v1, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill
; GFX906-NEXT: s_nop 0
-; GFX906-NEXT: buffer_store_dword v1, off, s[12:15], 0 offset:20 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v2, off, s[12:15], 0 offset:24 ; 4-byte Folded Spill
-; GFX906-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:28 ; 4-byte Folded Spill
-; GFX906-NEXT: v_mov_b32_e32 v0, v57
-; GFX906-NEXT: v_mov_b32_e32 v1, v58
-; GFX906-NEXT: v_mov_b32_e32 v2, v59
-; GFX906-NEXT: v_mov_b32_e32 v3, v60
+; GFX906-NEXT: buffer_store_dword v2, off, s[12:15], 0 offset:20 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v3, off, s[12:15], 0 offset:24 ; 4-byte Folded Spill
+; GFX906-NEXT: buffer_store_dword v4, off, s[12:15], 0 offset:28 ; 4-byte Folded Spill
+; GFX906-NEXT: v_mov_b32_e32 v1, v57
+; GFX906-NEXT: v_mov_b32_e32 v2, v58
+; GFX906-NEXT: v_mov_b32_e32 v3, v59
+; GFX906-NEXT: v_mov_b32_e32 v4, v60
; GFX906-NEXT: v_mov_b32_e32 v60, v56
; GFX906-NEXT: v_mov_b32_e32 v59, v55
; GFX906-NEXT: v_mov_b32_e32 v58, v54
@@ -380,30 +391,30 @@ define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(
; GFX906-NEXT: buffer_load_dword v6, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
; GFX906-NEXT: buffer_load_dword v7, off, s[12:15], 0 offset:8 ; 4-byte Folded Reload
; GFX906-NEXT: buffer_load_dword v8, off, s[12:15], 0 offset:12 ; 4-byte Folded Reload
-; GFX906-NEXT: v_mov_b32_e32 v4, 0
+; GFX906-NEXT: v_mov_b32_e32 v0, 0
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: global_store_dwordx4 v4, v[5:8], s[6:7]
-; GFX906-NEXT: global_store_dwordx4 v4, v[9:12], s[6:7] offset:16
-; GFX906-NEXT: global_store_dwordx4 v4, v[13:16], s[6:7] offset:32
-; GFX906-NEXT: global_store_dwordx4 v4, v[17:20], s[6:7] offset:48
-; GFX906-NEXT: global_store_dwordx4 v4, v[21:24], s[6:7] offset:64
-; GFX906-NEXT: global_store_dwordx4 v4, v[25:28], s[6:7] offset:80
-; GFX906-NEXT: global_store_dwordx4 v4, v[29:32], s[6:7] offset:96
-; GFX906-NEXT: global_store_dwordx4 v4, v[33:36], s[6:7] offset:112
-; GFX906-NEXT: global_store_dwordx4 v4, v[37:40], s[6:7] offset:128
-; GFX906-NEXT: global_store_dwordx4 v4, v[41:44], s[6:7] offset:144
-; GFX906-NEXT: global_store_dwordx4 v4, v[45:48], s[6:7] offset:160
-; GFX906-NEXT: global_store_dwordx4 v4, v[49:52], s[6:7] offset:176
-; GFX906-NEXT: global_store_dwordx4 v4, v[53:56], s[6:7] offset:192
-; GFX906-NEXT: global_store_dwordx4 v4, v[57:60], s[6:7] offset:208
-; GFX906-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] offset:224
-; GFX906-NEXT: buffer_load_dword v0, off, s[12:15], 0 offset:16 ; 4-byte Folded Reload
+; GFX906-NEXT: global_store_dwordx4 v0, v[5:8], s[6:7]
+; GFX906-NEXT: global_store_dwordx4 v0, v[9:12], s[6:7] offset:16
+; GFX906-NEXT: global_store_dwordx4 v0, v[13:16], s[6:7] offset:32
+; GFX906-NEXT: global_store_dwordx4 v0, v[17:20], s[6:7] offset:48
+; GFX906-NEXT: global_store_dwordx4 v0, v[21:24], s[6:7] offset:64
+; GFX906-NEXT: global_store_dwordx4 v0, v[25:28], s[6:7] offset:80
+; GFX906-NEXT: global_store_dwordx4 v0, v[29:32], s[6:7] offset:96
+; GFX906-NEXT: global_store_dwordx4 v0, v[33:36], s[6:7] offset:112
+; GFX906-NEXT: global_store_dwordx4 v0, v[37:40], s[6:7] offset:128
+; GFX906-NEXT: global_store_dwordx4 v0, v[41:44], s[6:7] offset:144
+; GFX906-NEXT: global_store_dwordx4 v0, v[45:48], s[6:7] offset:160
+; GFX906-NEXT: global_store_dwordx4 v0, v[49:52], s[6:7] offset:176
+; GFX906-NEXT: global_store_dwordx4 v0, v[53:56], s[6:7] offset:192
+; GFX906-NEXT: global_store_dwordx4 v0, v[57:60], s[6:7] offset:208
+; GFX906-NEXT: global_store_dwordx4 v0, v[1:4], s[6:7] offset:224
+; GFX906-NEXT: buffer_load_dword v1, off, s[12:15], 0 offset:16 ; 4-byte Folded Reload
; GFX906-NEXT: s_nop 0
-; GFX906-NEXT: buffer_load_dword v1, off, s[12:15], 0 offset:20 ; 4-byte Folded Reload
-; GFX906-NEXT: buffer_load_dword v2, off, s[12:15], 0 offset:24 ; 4-byte Folded Reload
-; GFX906-NEXT: buffer_load_dword v3, off, s[12:15], 0 offset:28 ; 4-byte Folded Reload
+; GFX906-NEXT: buffer_load_dword v2, off, s[12:15], 0 offset:20 ; 4-byte Folded Reload
+; GFX906-NEXT: buffer_load_dword v3, off, s[12:15], 0 offset:24 ; 4-byte Folded Reload
+; GFX906-NEXT: buffer_load_dword v4, off, s[12:15], 0 offset:28 ; 4-byte Folded Reload
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] offset:240
+; GFX906-NEXT: global_store_dwordx4 v0, v[1:4], s[6:7] offset:240
; GFX906-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -479,16 +490,18 @@ define amdgpu_kernel void @v8i8_phi_chain(ptr addrspace(1) %src1, ptr addrspace(
; GFX906-LABEL: v8i8_phi_chain:
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX906-NEXT: v_lshlrev_b32_e32 v3, 3, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GFX906-NEXT: s_mov_b64 s[0:1], exec
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[8:9]
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v1, s[8:9]
; GFX906-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX906-NEXT: s_cbranch_execz .LBB8_2
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v3, s[10:11]
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v1, s[10:11]
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0
; GFX906-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX906-NEXT: s_and_b64 s[4:5], exec, vcc
@@ -534,17 +547,18 @@ define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspac
; GFX906-LABEL: v8i8_multi_block:
; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX906-NEXT: v_lshlrev_b32_e32 v5, 3, v0
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
-; GFX906-NEXT: global_load_dwordx2 v[3:4], v5, s[8:9]
+; GFX906-NEXT: global_load_dwordx2 v[3:4], v1, s[8:9]
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, v3
; GFX906-NEXT: v_mov_b32_e32 v2, v4
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX906-NEXT: s_cbranch_execz .LBB9_4
; GFX906-NEXT: ; %bb.1: ; %bb.1
-; GFX906-NEXT: global_load_dwordx2 v[1:2], v5, s[10:11]
+; GFX906-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GFX906-NEXT: global_load_dwordx2 v[1:2], v1, s[10:11]
; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0
; GFX906-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX906-NEXT: s_cbranch_execz .LBB9_3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index e06731d16b64b..ef649172f275c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -11630,606 +11630,668 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v29
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v1
+; SI-NEXT: v_mov_b32_e32 v62, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:380
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:196
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:364
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:372
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v59
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v56
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_or_b32_e32 v3, v40, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v47
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v43
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v52
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v50
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v62
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v56
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v46
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v44
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v52
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v33
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v51
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v57
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v50
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v45
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
@@ -12238,50 +12300,54 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -12290,78 +12356,84 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -12369,769 +12441,848 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v30, v31, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v31, v31, v43
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: .LBB14_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v47
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v43
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v63
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v46, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v49
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v44, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v54
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v52
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v50
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_or_b32_e32 v23, v24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v27, v28, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: v_or_b32_e32 v28, v29, v28
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v30
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v31, v43, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
; SI-NEXT: .LBB14_4: ; %end
@@ -23080,8 +23231,6 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v32i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -23098,230 +23247,349 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v0
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v63
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v53
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v37
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v8
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v14
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v10
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v9
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v6
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v4
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v3
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v2
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v1
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v4
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB18_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v59
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v56
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v57
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v47
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v43
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v41
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v55
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v53
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v49
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v32
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
@@ -23387,393 +23655,329 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v34
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_alignbit_b32 v19, v19, v59, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v57, 16
-; SI-NEXT: v_alignbit_b32 v21, v21, v46, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v44, 16
-; SI-NEXT: v_alignbit_b32 v23, v23, v42, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v40, 16
-; SI-NEXT: v_alignbit_b32 v25, v25, v54, 16
-; SI-NEXT: v_alignbit_b32 v26, v26, v52, 16
-; SI-NEXT: v_alignbit_b32 v27, v27, v50, 16
-; SI-NEXT: v_alignbit_b32 v28, v28, v48, 16
-; SI-NEXT: v_alignbit_b32 v29, v29, v38, 16
-; SI-NEXT: v_alignbit_b32 v30, v30, v35, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v33, 16
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v62
-; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v60
-; SI-NEXT: v_alignbit_b32 v18, v18, v61, 16
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB18_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB18_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v60
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v56
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v46
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v44
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v42
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v40
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v54
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v52
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v48
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v38
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v36
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v34
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v61
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v59
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v57
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v46
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v42
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v40
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v54
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v48
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v38
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v35
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
; SI-NEXT: .LBB18_4: ; %end
@@ -34120,200 +34324,161 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v45, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
-; SI-NEXT: v_mov_b32_e32 v46, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_mov_b32_e32 v47, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v21
-; SI-NEXT: v_mov_b32_e32 v56, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_mov_b32_e32 v57, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v23
-; SI-NEXT: v_mov_b32_e32 v58, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v24
-; SI-NEXT: v_mov_b32_e32 v59, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; SI-NEXT: v_mov_b32_e32 v60, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
; SI-NEXT: v_mov_b32_e32 v61, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
-; SI-NEXT: v_mov_b32_e32 v43, v11
-; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_mov_b32_e32 v51, v19
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v17
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
+; SI-NEXT: v_mov_b32_e32 v52, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v61
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_mov_b32_e32 v53, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
+; SI-NEXT: v_mov_b32_e32 v54, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v53
+; SI-NEXT: v_mov_b32_e32 v55, v15
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
+; SI-NEXT: v_mov_b32_e32 v40, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v55
+; SI-NEXT: v_mov_b32_e32 v41, v13
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_mov_b32_e32 v42, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v41
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v62
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
-; SI-NEXT: v_or_b32_e32 v8, v8, v32
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v62
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v44
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_or_b32_e32 v1, v1, v42
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
-; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v55
-; SI-NEXT: v_or_b32_e32 v9, v9, v54
-; SI-NEXT: v_or_b32_e32 v10, v10, v39
-; SI-NEXT: v_or_b32_e32 v11, v11, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -34325,27 +34490,89 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v52
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v51
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
@@ -34362,183 +34589,268 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v37
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v51
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v36
-; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v18, v35
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: .LBB26_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v32, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
-; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v55, v7
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
-; SI-NEXT: v_or_b32_e32 v10, v39, v10
-; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v53
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v52
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -34556,70 +34868,42 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -47370,606 +47654,668 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v29
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v1
+; SI-NEXT: v_mov_b32_e32 v62, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:380
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:196
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:364
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:372
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v59
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v56
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_or_b32_e32 v3, v40, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v47
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v43
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v52
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v50
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v62
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v56
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v46
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v44
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v52
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v33
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v51
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v57
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v50
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v45
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
@@ -47978,50 +48324,54 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -48030,78 +48380,84 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -48109,769 +48465,848 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v30, v31, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v31, v31, v43
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: .LBB38_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v47
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v43
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v63
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v46, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v49
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v44, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v54
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v52
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v50
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_or_b32_e32 v23, v24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v27, v28, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: v_or_b32_e32 v28, v29, v28
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v30
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v31, v43, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
; SI-NEXT: .LBB38_4: ; %end
@@ -59012,8 +59447,6 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v32f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -59030,230 +59463,349 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v0
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v63
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v53
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v37
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v8
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v14
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v10
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v9
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v6
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v4
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v3
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v2
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v1
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v4
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v59
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v56
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v57
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v47
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v43
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v41
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v55
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v53
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v49
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v32
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
@@ -59319,393 +59871,329 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v34
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_alignbit_b32 v19, v19, v59, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v57, 16
-; SI-NEXT: v_alignbit_b32 v21, v21, v46, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v44, 16
-; SI-NEXT: v_alignbit_b32 v23, v23, v42, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v40, 16
-; SI-NEXT: v_alignbit_b32 v25, v25, v54, 16
-; SI-NEXT: v_alignbit_b32 v26, v26, v52, 16
-; SI-NEXT: v_alignbit_b32 v27, v27, v50, 16
-; SI-NEXT: v_alignbit_b32 v28, v28, v48, 16
-; SI-NEXT: v_alignbit_b32 v29, v29, v38, 16
-; SI-NEXT: v_alignbit_b32 v30, v30, v35, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v33, 16
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v62
-; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v60
-; SI-NEXT: v_alignbit_b32 v18, v18, v61, 16
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB42_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v60
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v56
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v46
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v44
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v42
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v40
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v54
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v52
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v48
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v38
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v36
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v34
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v61
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v59
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v57
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v46
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v42
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v40
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v54
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v48
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v38
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v35
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
; SI-NEXT: .LBB42_4: ; %end
@@ -70348,200 +70836,161 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v45, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
-; SI-NEXT: v_mov_b32_e32 v46, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_mov_b32_e32 v47, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v21
-; SI-NEXT: v_mov_b32_e32 v56, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_mov_b32_e32 v57, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v23
-; SI-NEXT: v_mov_b32_e32 v58, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v24
-; SI-NEXT: v_mov_b32_e32 v59, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; SI-NEXT: v_mov_b32_e32 v60, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
; SI-NEXT: v_mov_b32_e32 v61, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
-; SI-NEXT: v_mov_b32_e32 v43, v11
-; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_mov_b32_e32 v51, v19
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v17
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
+; SI-NEXT: v_mov_b32_e32 v52, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v61
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_mov_b32_e32 v53, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
+; SI-NEXT: v_mov_b32_e32 v54, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v53
+; SI-NEXT: v_mov_b32_e32 v55, v15
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
+; SI-NEXT: v_mov_b32_e32 v40, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v55
+; SI-NEXT: v_mov_b32_e32 v41, v13
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_mov_b32_e32 v42, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v41
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v62
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
-; SI-NEXT: v_or_b32_e32 v8, v8, v32
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v62
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v44
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_or_b32_e32 v1, v1, v42
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
-; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v55
-; SI-NEXT: v_or_b32_e32 v9, v9, v54
-; SI-NEXT: v_or_b32_e32 v10, v10, v39
-; SI-NEXT: v_or_b32_e32 v11, v11, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -70553,27 +71002,89 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v52
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v51
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
@@ -70590,183 +71101,268 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v37
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v51
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v36
-; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v18, v35
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: .LBB50_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v32, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
-; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v55, v7
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
-; SI-NEXT: v_or_b32_e32 v10, v39, v10
-; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v53
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v52
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -70784,70 +71380,42 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -81116,606 +81684,668 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v29
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v1
+; SI-NEXT: v_mov_b32_e32 v62, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:380
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:196
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:364
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:372
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v59
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v56
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_or_b32_e32 v3, v40, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v47
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v43
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v52
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v50
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v62
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v56
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v46
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v44
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v52
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v33
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v51
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v57
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v50
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v45
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
@@ -81724,50 +82354,54 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -81776,78 +82410,84 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -81855,769 +82495,848 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v30, v31, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v31, v31, v43
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: .LBB58_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v47
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v43
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v63
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v46, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v49
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v44, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v54
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v52
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v50
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_or_b32_e32 v23, v24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v27, v28, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: v_or_b32_e32 v28, v29, v28
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v30
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v31, v43, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
; SI-NEXT: .LBB58_4: ; %end
@@ -92542,8 +93261,6 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v16i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -92560,230 +93277,349 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v0
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v63
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v53
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v37
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v8
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v14
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v10
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v9
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v6
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v4
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v3
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v2
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v1
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v4
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB62_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v59
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v56
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v57
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v47
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v43
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v41
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v55
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v53
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v49
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v32
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
@@ -92849,393 +93685,329 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v34
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_alignbit_b32 v19, v19, v59, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v57, 16
-; SI-NEXT: v_alignbit_b32 v21, v21, v46, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v44, 16
-; SI-NEXT: v_alignbit_b32 v23, v23, v42, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v40, 16
-; SI-NEXT: v_alignbit_b32 v25, v25, v54, 16
-; SI-NEXT: v_alignbit_b32 v26, v26, v52, 16
-; SI-NEXT: v_alignbit_b32 v27, v27, v50, 16
-; SI-NEXT: v_alignbit_b32 v28, v28, v48, 16
-; SI-NEXT: v_alignbit_b32 v29, v29, v38, 16
-; SI-NEXT: v_alignbit_b32 v30, v30, v35, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v33, 16
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v62
-; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v60
-; SI-NEXT: v_alignbit_b32 v18, v18, v61, 16
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB62_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB62_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v60
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v56
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v46
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v44
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v42
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v40
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v54
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v52
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v48
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v38
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v36
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v34
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v61
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v59
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v57
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v46
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v42
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v40
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v54
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v48
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v38
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v35
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
; SI-NEXT: .LBB62_4: ; %end
@@ -103598,200 +104370,161 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v45, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
-; SI-NEXT: v_mov_b32_e32 v46, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_mov_b32_e32 v47, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v21
-; SI-NEXT: v_mov_b32_e32 v56, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_mov_b32_e32 v57, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v23
-; SI-NEXT: v_mov_b32_e32 v58, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v24
-; SI-NEXT: v_mov_b32_e32 v59, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; SI-NEXT: v_mov_b32_e32 v60, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
; SI-NEXT: v_mov_b32_e32 v61, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
-; SI-NEXT: v_mov_b32_e32 v43, v11
-; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_mov_b32_e32 v51, v19
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v17
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
+; SI-NEXT: v_mov_b32_e32 v52, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v61
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_mov_b32_e32 v53, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
+; SI-NEXT: v_mov_b32_e32 v54, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v53
+; SI-NEXT: v_mov_b32_e32 v55, v15
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
+; SI-NEXT: v_mov_b32_e32 v40, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v55
+; SI-NEXT: v_mov_b32_e32 v41, v13
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_mov_b32_e32 v42, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v41
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v62
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
-; SI-NEXT: v_or_b32_e32 v8, v8, v32
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v62
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v44
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_or_b32_e32 v1, v1, v42
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
-; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v55
-; SI-NEXT: v_or_b32_e32 v9, v9, v54
-; SI-NEXT: v_or_b32_e32 v10, v10, v39
-; SI-NEXT: v_or_b32_e32 v11, v11, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -103803,27 +104536,89 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v52
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v51
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
@@ -103840,183 +104635,268 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v37
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v51
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v36
-; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v18, v35
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: .LBB70_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v32, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
-; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v55, v7
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
-; SI-NEXT: v_or_b32_e32 v10, v39, v10
-; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v53
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v52
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -104034,70 +104914,42 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -113939,606 +114791,668 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v29
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v1
+; SI-NEXT: v_mov_b32_e32 v62, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v0
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:380
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:196
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:364
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:372
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v59
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v56
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_or_b32_e32 v3, v40, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v47
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v43
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v52
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v50
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v62
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v56
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v46
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v44
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v52
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v63
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v33
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v51
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v57
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v50
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v45
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
@@ -114547,50 +115461,54 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -114599,78 +115517,84 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -114678,769 +115602,848 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v30, v31, v30
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v31, v31, v43
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: .LBB74_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v47
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v45
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v43
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v63
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v55, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v46, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v49
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v44, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v32
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v54
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v38
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v52
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v50
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v35
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_or_b32_e32 v23, v24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_or_b32_e32 v22, v23, v22
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v27, v28, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: v_or_b32_e32 v26, v27, v26
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v28
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v29
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: v_or_b32_e32 v28, v29, v28
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_or_b32_e32 v29, v30, v29
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v30
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v31, v43, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v32
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
; SI-NEXT: .LBB74_4: ; %end
@@ -125457,8 +126460,6 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v16f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -125475,230 +126476,349 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v0
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v63
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v53
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v37
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v8
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v14
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v10
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v9
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v6
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v4
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v3
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v2
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v1
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v4
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB78_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v59
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v56
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v57
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v47
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v43
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v41
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v55
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v53
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v49
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v32
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
@@ -125764,393 +126884,329 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v34
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_alignbit_b32 v19, v19, v59, 16
-; SI-NEXT: v_alignbit_b32 v20, v20, v57, 16
-; SI-NEXT: v_alignbit_b32 v21, v21, v46, 16
-; SI-NEXT: v_alignbit_b32 v22, v22, v44, 16
-; SI-NEXT: v_alignbit_b32 v23, v23, v42, 16
-; SI-NEXT: v_alignbit_b32 v24, v24, v40, 16
-; SI-NEXT: v_alignbit_b32 v25, v25, v54, 16
-; SI-NEXT: v_alignbit_b32 v26, v26, v52, 16
-; SI-NEXT: v_alignbit_b32 v27, v27, v50, 16
-; SI-NEXT: v_alignbit_b32 v28, v28, v48, 16
-; SI-NEXT: v_alignbit_b32 v29, v29, v38, 16
-; SI-NEXT: v_alignbit_b32 v30, v30, v35, 16
-; SI-NEXT: v_alignbit_b32 v31, v31, v33, 16
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v62
-; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v60
-; SI-NEXT: v_alignbit_b32 v18, v18, v61, 16
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB78_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB78_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v58
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v41
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v51
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v39
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v34
-; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v60
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v56
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v46
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v44
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v42
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v40
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v54
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v52
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v48
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v38
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v36
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v34
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v61
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v59
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v57
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v46
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v44
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v42
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v40
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v54
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v48
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v38
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v35
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16
; SI-NEXT: .LBB78_4: ; %end
@@ -136573,200 +137629,161 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v45, v9
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
-; SI-NEXT: v_mov_b32_e32 v46, v8
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_mov_b32_e32 v47, v7
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v21
-; SI-NEXT: v_mov_b32_e32 v56, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_mov_b32_e32 v57, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v23
-; SI-NEXT: v_mov_b32_e32 v58, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v24
-; SI-NEXT: v_mov_b32_e32 v59, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; SI-NEXT: v_mov_b32_e32 v60, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
; SI-NEXT: v_mov_b32_e32 v61, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
-; SI-NEXT: v_mov_b32_e32 v43, v11
-; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v29
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_mov_b32_e32 v51, v19
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v17
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
+; SI-NEXT: v_mov_b32_e32 v52, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v61
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_mov_b32_e32 v53, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
+; SI-NEXT: v_mov_b32_e32 v54, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v53
+; SI-NEXT: v_mov_b32_e32 v55, v15
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
+; SI-NEXT: v_mov_b32_e32 v40, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v55
+; SI-NEXT: v_mov_b32_e32 v41, v13
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_mov_b32_e32 v42, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v41
+; SI-NEXT: v_mov_b32_e32 v43, v11
+; SI-NEXT: v_mov_b32_e32 v44, v10
+; SI-NEXT: v_mov_b32_e32 v45, v9
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: v_mov_b32_e32 v47, v7
+; SI-NEXT: v_mov_b32_e32 v56, v6
+; SI-NEXT: v_mov_b32_e32 v57, v5
+; SI-NEXT: v_mov_b32_e32 v58, v4
+; SI-NEXT: v_mov_b32_e32 v59, v3
+; SI-NEXT: v_mov_b32_e32 v60, v2
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v62
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
-; SI-NEXT: v_or_b32_e32 v8, v8, v32
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v62
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v44
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_or_b32_e32 v1, v1, v42
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
-; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v55
-; SI-NEXT: v_or_b32_e32 v9, v9, v54
-; SI-NEXT: v_or_b32_e32 v10, v10, v39
-; SI-NEXT: v_or_b32_e32 v11, v11, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v43
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -136778,27 +137795,89 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v52
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v51
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
@@ -136815,183 +137894,268 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v37
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v51
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v36
-; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v18, v35
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; kill: killed $vgpr63
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: .LBB86_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v32, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v62
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
-; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v55, v7
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
-; SI-NEXT: v_or_b32_e32 v10, v39, v10
-; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v53
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v52
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -137009,70 +138173,42 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -138339,505 +139475,451 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:388
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:108
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v21
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v29
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:380
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:372
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:368
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:364
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:360
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:356
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:352
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:348
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:340
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:292
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:268
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:260
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:220
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:208
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v18
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:196
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:192
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:188
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:184
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:180
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:176
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:172
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:144
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v25
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:128
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:112
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v1
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v0
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:300
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:292
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:308
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v0
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v5
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v14
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:376
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:364
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:356
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:372
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:380
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v61, 24, v13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; kill: killed $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v14
-; SI-NEXT: ; kill: killed $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; kill: killed $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:8
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:92
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v31, v7, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v6
-; SI-NEXT: v_or_b32_e32 v32, v4, v2
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v29, v45, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: v_or_b32_e32 v33, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: v_or_b32_e32 v5, v10, v5
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v19
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v34, v47, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v11
+; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v17
+; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v14
+; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
@@ -138888,17 +139970,12 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v27, v54, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v9
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
@@ -138935,6 +140012,18 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
@@ -138951,1095 +140040,1162 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v27
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v12
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v42
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v55
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v13
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v18
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v24
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v20
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v45
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v43
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v16
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v8
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v32, v4, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v47
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v44
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v42
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v35, v60, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v56
+; SI-NEXT: v_or_b32_e32 v34, v5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v61
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v58
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v36, v5, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v44
+; SI-NEXT: v_or_b32_e32 v35, v5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v56
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v46
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v36, v5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v63
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v62
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v37, v61, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v58
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v57
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v60
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v59
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v38, v62, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v4
+; SI-NEXT: v_or_b32_e32 v37, v7, v5
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v4
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v22, v25, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v22, v25, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_or_b32_e32 v22, v25, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_or_b32_e32 v25, v22, v25
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v29, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v30, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v38, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v48, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v39, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v48, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v49, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v50, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v51, v22, v26
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v22, v19, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v26, v19, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v25, v3, v15
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v24, v17, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v3, v3, v18
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v33
+; SI-NEXT: v_or_b32_e32 v6, v22, v6
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
-; SI-NEXT: v_or_b32_e32 v30, v17, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v28, v10, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: .LBB88_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v27
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
+; SI-NEXT: v_or_b32_e32 v4, v4, v12
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v7, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_or_b32_e32 v5, v47, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v11
-; SI-NEXT: v_or_b32_e32 v5, v43, v5
+; SI-NEXT: v_or_b32_e32 v12, v4, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v17
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v14
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_or_b32_e32 v9, v45, v9
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v9, v5
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_or_b32_e32 v8, v54, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v8, v6
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_or_b32_e32 v12, v63, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, 0x300, v12
-; SI-NEXT: v_or_b32_e32 v13, v62, v13
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v56
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v46
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_or_b32_e32 v14, v61, v14
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v41
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v42
-; SI-NEXT: v_or_b32_e32 v14, v59, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v9, v4, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v19
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v15, v60, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v4
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v0
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v11, v0, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v10, v2
-; SI-NEXT: v_or_b32_e32 v8, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v10, v1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v63
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v62
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x300, v21
+; SI-NEXT: v_or_b32_e32 v22, v22, v25
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v61
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v58
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v22, v25, v22
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v22, v25, v22
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v57
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v47
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_or_b32_e32 v26, v26, v29
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
+; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v43
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v26, v29, v26
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v8, v8, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v8, v8, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v16, v16, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v16, v3
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v1, v18, v1
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_or_b32_e32 v2, v17, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v9, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v9
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v14, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_or_b32_e32 v13, v16, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v13, v13, v15
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v14
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v13
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v3
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v10, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v10
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v15, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v15
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v11, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v16, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v16
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v12
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v15, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v17, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v17
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v16, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v16
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v18, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v18
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v14
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v17, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v19, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v19
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v18, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v18
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v20, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v20
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v16
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v19, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v19
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v23, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v23
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v21, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v24, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v24
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v18
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v23, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v26, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v25, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v25
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v26, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v26
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v27, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v27
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v27, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v28, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v28
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v2
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v28, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v28
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v29, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v29, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_or_b32_e32 v30, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v27
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v30, v12
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v2
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_or_b32_e32 v30, v0, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v29
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: v_or_b32_e32 v21, v30, v21
+; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v1
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v0
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v25
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v25
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v23, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v26
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v23, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v26
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v29, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v29
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v30, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v30
+; SI-NEXT: v_or_b32_e32 v22, v26, v22
+; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
-; SI-NEXT: v_or_b32_e32 v15, v30, v15
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v22, v30, v22
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: v_or_b32_e32 v15, v30, v15
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
+; SI-NEXT: v_or_b32_e32 v22, v30, v22
+; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v31, v15
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v31
+; SI-NEXT: v_or_b32_e32 v22, v31, v22
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
-; SI-NEXT: v_or_b32_e32 v15, v31, v15
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v31
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_or_b32_e32 v22, v31, v22
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
@@ -140050,285 +141206,325 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v31
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v32
-; SI-NEXT: v_and_b32_e32 v32, 0xff, v32
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_or_b32_e32 v32, v33, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v32
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v22
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v19
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v26
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v23
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v21
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v14
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v25
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v13
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v7
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v5
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: .LBB88_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v12
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v38
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v39
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v48
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v35
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v22
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v50
; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v25
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v24
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v28
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v30
; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v31
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v40
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v32
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v41
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
@@ -140345,25 +141541,15 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v29
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v53
-; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v33
; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v55
; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v36
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v36
; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v38
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v37
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -141676,693 +142862,703 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:272
-; GFX9-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:288
-; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:296
-; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:304
-; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:320
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:156
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:152
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:140
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:132
-; GFX9-NEXT: s_waitcnt vmcnt(27)
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:4
+; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: s_waitcnt vmcnt(31)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(26)
-; GFX9-NEXT: v_lshlrev_b16_e32 v53, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(25)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(24)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(23)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v6
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:100
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
+; GFX9-NEXT: s_waitcnt vmcnt(31)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:384
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v7
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v9
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v10
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v11
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v13
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v14
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v15
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v16
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v17
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v18
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:328
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:352
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:324
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:332
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:348
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:344
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:360
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:384
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:356
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:364
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:116
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:260
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:380
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:340
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:372
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:248
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:380
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:376
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:372
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:200
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:200
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:196
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:344
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:376
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:168
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:332
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:328
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:324
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:156
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:320
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:152
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:316
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:148
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:312
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:144
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:308
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:140
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:304
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:300
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:132
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:284
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:124
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB88_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
-; GFX9-NEXT: v_or_b32_sdwa v9, v59, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v47, v45, s6
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v55, v54, s6
-; GFX9-NEXT: v_perm_b32 v17, v43, v42, s6
-; GFX9-NEXT: v_perm_b32 v18, v58, v57, s6
-; GFX9-NEXT: v_perm_b32 v19, v63, v46, s6
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v10, v62, v35, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v60
+; GFX9-NEXT: v_or_b32_sdwa v11, v63, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v59, v58, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v13, v44, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v43, v42, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v53
+; GFX9-NEXT: v_or_b32_sdwa v15, v52, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr35
+; GFX9-NEXT: ; implicit-def: $vgpr63
+; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr55
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr58
-; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr46
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: ; implicit-def: $vgpr52
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v33, s6
+; GFX9-NEXT: v_perm_b32 v8, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v60, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
+; GFX9-NEXT: v_or_b32_sdwa v8, v38, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v36, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v44, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v9, v61, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v41, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v32, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v52, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v57
+; GFX9-NEXT: v_or_b32_sdwa v11, v56, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr44
-; GFX9-NEXT: ; implicit-def: $vgpr41
-; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v12, v50, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v12, v46, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr50
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v37, v36, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v13, v40, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v55
+; GFX9-NEXT: v_or_b32_sdwa v14, v54, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v51, v50, s6
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr57
+; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr55
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_sdwa v15, v62, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v17, v16, s6
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v35, s6
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
-; GFX9-NEXT: v_perm_b32 v16, v32, v56, s6
+; GFX9-NEXT: v_perm_b32 v17, v18, v17, s6
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s7
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v17, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr62
-; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s7
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v20, v20, v61, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s7
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v21, v21, v22, s6
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s7
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s7
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s6
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v23, v23, v48, s6
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s7
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s7
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s6
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s7
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s7
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s6
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s7
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s7
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s6
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s7
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v30, 8, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s7
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v32, v33, v32, s6
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s7
@@ -142431,80 +143627,94 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; kill: killed $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB88_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB88_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v33
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v45
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v11, v38, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
-; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v46
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v56
-; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v42
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v34
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v60
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v45
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v41
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v49
+; GFX9-NEXT: v_mov_b32_e32 v29, v48
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(20)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(19)
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: s_waitcnt vmcnt(18)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
+; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(12)
+; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(9)
+; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: s_waitcnt vmcnt(11)
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v9
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
+; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
+; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -142512,16 +143722,16 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v2
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v3
; GFX9-NEXT: v_perm_b32 v0, v2, v0, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
@@ -142530,312 +143740,330 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: v_add_u16_e32 v8, 3, v60
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v8, v53, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v9, v51, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v8, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v36
+; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s6
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v10, v49, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v61
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v41
-; GFX9-NEXT: v_or_b32_sdwa v10, v39, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v63
+; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s6
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v55
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v52
-; GFX9-NEXT: v_or_b32_sdwa v12, v34, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v56
+; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s6
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v50
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v47
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v48
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v44
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s6
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v37
-; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v36
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v43
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v40
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s6
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v52
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v35
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v50
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v62
-; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v57
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v17, 3, v63
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v18, 3, v32
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 3, v43
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v16
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v18
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v19
; GFX9-NEXT: v_perm_b32 v16, v18, v16, s6
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v17, v17, v20, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v19
; GFX9-NEXT: v_perm_b32 v31, v32, v31, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v21
; GFX9-NEXT: v_perm_b32 v30, v33, v30, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v23
-; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v36, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v36
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v37, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v38, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v39, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v39
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v48, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v49, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v50, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v50
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
+; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v51, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v51
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v52, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v53, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v53
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v54, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v55, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v55
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v40, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v61
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v50, 0x300, v40
; GFX9-NEXT: v_perm_b32 v21, v50, v21, s6
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v41, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v41
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v42, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v51, 0x300, v42
; GFX9-NEXT: v_perm_b32 v20, v51, v20, s6
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -142843,23 +144071,23 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v43, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v43
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v44, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v45, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v45
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
@@ -142909,742 +144137,754 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:488
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:484
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:384
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:368
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:360
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:352
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:328
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB88_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v96, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v118, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v132, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v151, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v164, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v85, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v166, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v113, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v112, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v129, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v117, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v145, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v178, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v161, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v87, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v37.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v115, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v49.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v144, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v15.h, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v167, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v182, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v42, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v160, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v46, v183, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v57, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v176, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v61, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v45, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v26.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.h, 8, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v44, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v56, v41, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v63, v59, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.h, 8, v52.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v58, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.l, v26.h
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v25.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v73, v62, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.h, v28.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v65.l
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v76, v74, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
-; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
-; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v69.h
+; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v31.l, v31.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v77, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v32.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: .LBB88_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB88_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v79.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v78.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v71.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v69.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v68.h, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v76.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v73.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v62.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v53.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v72.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v60.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v59.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v61.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v47.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v41.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v44.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v40.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v181.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v46.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v42.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v180.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v176.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v182.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v150.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v149.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v167.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v148.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v128.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v38.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v144.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v37.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v102.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v35.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v161.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v135.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v166.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v164.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v133.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v130.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v117.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v100.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v129.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v112.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v101.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v103.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -143657,32 +144897,31 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v32.h
; GFX11-TRUE16-NEXT: .LBB88_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:392
-; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:488
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:392
+; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:484
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -143739,165 +144978,128 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v24 :: v_dual_mov_b32 v51, v19
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v71, v20
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v67, v17
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v65, v18
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v16 :: v_dual_mov_b32 v50, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v14 :: v_dual_mov_b32 v53, v9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:364
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:360
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:356
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:352
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v6, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:312
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:308
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:304
-; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:284
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:280
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:276
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:384
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:380
+; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:360
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:356
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:352
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:348
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:308
+; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:304
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:300
+; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:280
+; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:276
+; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:272
+; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:252
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:232
-; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:228
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:224
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:192
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:188
-; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:184
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:180
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:152
-; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:148
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:136
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:248
+; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:228
+; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:224
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:220
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:188
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:184
+; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:180
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:176
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:148
+; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:144
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_b32 v13, off, s32 offset:388
-; GFX11-FAKE16-NEXT: scratch_load_u16 v14, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v15, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v16, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v17, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v18, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v19, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v20, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v21, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v22, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v23, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v24, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v126, 8, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v125, 8, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v123, 8, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v122, 8, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v124, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v121, 8, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v120, 8, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v111, 8, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v110, 8, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v108, 8, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v109, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v107, 8, v12
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(28)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v182, 8, v14
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v166, 8, v15
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(26)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v180, 8, v16
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v46, 8, v17
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v47, 8, v18
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(23)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v56, 8, v19
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v75, 8, v20
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v59, 8, v21
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v74, 8, v22
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v95, 8, v23
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v90, 8, v24
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v30 :: v_dual_mov_b32 v85, v29
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, v28 :: v_dual_mov_b32 v81, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v27 :: v_dual_mov_b32 v83, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v71, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v65, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v69, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v17 :: v_dual_mov_b32 v52, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v15 :: v_dual_mov_b32 v64, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v13 :: v_dual_mov_b32 v32, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v33, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -143907,124 +145109,147 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v37, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v48, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v39, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v55, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v65, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v49, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v84, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v82, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v70, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v118
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v113
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v86, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v71, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v70, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v82, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v86, v85, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v84, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v102
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v99
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v7, v182
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v134
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v129
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v112, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v166
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v7, v46
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v47
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v132
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v151
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v145
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v150
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v75
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v162
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v130, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v14, v59
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v74
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v148, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v11, v95
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v90
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v116
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v107
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v103, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v131, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v102, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v147, v146, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v133, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v149, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v18, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v20, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v24, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v177, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v165, v161, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v183, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v179, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v43, v42, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v40, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v60, v57, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v44, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v72
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v21, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v27, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v58
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v109
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v73
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v63
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v24, v108
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v61, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v27, v111
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v120
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v110
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v91
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v103
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v113
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v147
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v129
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v117, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v14, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v119
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v162
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v150
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v145
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v165
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v151
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v131, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v163, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v161, v146, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v149, v144, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v177, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v17, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v180, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v176, v164, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v181, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v44, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v42, v183, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v57, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v47, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v72, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v59, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v78
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v75
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v73
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v88
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v94
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v105
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v27, v122
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v106
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v121
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v76, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v29, v124
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v123
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v89, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v27, v125
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v126
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v34, v127
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v104, v93, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v28, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v35, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v33, v36, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v34, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v76
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v60, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v58, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v23, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v79, v74, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v104
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v77
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v26, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v32, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v95
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v92
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v111
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v109
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v107
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v93
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v110
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v32, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v127
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v123
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v121
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v120
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xff, v126
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v124
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v94, v90, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v108, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v35, v36
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v38
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v125, v122, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v32, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v35, v36, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
@@ -144034,13 +145259,13 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
@@ -144049,346 +145274,364 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: .LBB88_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB88_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v104, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v105, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v93
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v94, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v125, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v126, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v122
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v124
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v127, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v92, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v121, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v123
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v120
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v127, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v89, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v125, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v126, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v108, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v89, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v77
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v91, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v88, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v76, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v62
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v123, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v124, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v78, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v122, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v108, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v105
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v110, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v105, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v107, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v94, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v93
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v90
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v95, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v90, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v104, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v92, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v91, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v88, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v74
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v76
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v78, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v74, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v75
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v73, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v73, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v121, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v62, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v61, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v72, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v61, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v63, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v120, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v111, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v45
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v45, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v110, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v58, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v60, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v42
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v58, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v109, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v60
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v58, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v72, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v61
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v59, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v46, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v56
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v57, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v56, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v47, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v57
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v43, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v108, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v43, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v42, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v41
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v183
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v40, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v183, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v181
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v183, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v181, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v179, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v182
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v181, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v180, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v178
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v176
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v176, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v165, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v176, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v177, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v164, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v161, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v164
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v167
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v166, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v164, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v160
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v149, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v147, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v160, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v149, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v144
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v146
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v144, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v165, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v148
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v146
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v133, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v151
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v162, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v146, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v131, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v131, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v118
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v134, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v119
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v128
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v117, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v118, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v102
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v102, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v98, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v129
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v128, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v115, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v96, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v167, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v107, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v162, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v148, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v95, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v150, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v135
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v151, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v90, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v116
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v113, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v101
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v100, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v74, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v75, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v130, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v103, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v132, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v59, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v129, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v114, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v56, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v99, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v86, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v46, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v47, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v101
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v113, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v101, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v180, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v182, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v85
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v166, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v85
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v84, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v84, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
@@ -144416,28 +145659,28 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v64, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v54
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v53
; GFX11-FAKE16-NEXT: v_add_nc_u16 v52, v52, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v66, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v51, 8, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v50, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v49
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v52
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v55, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v51, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v49, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v50, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v51, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v50, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v49, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v39, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v38, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v37, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xff, v39
@@ -144469,30 +145712,30 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v68, v67, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v84, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v100, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v98, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v97, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v102, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v117, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v147, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v161, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v176, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v181, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v40, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v58, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v45, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v61, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v73, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v77, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v89, v31, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v84, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v98, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v112, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v117, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v131, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v144, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v160, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v164, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v180, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v183, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v43, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v56, v23, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v46, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v62, v25, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v74, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v77, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v92, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v90, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v105, v30, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v108, v31, 0x5040100
; GFX11-FAKE16-NEXT: .LBB88_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -149054,16 +150297,6 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v128i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8
-; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
@@ -149080,72 +150313,32 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v56
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
@@ -149159,6 +150352,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
@@ -149175,98 +150371,6 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v33
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v36
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v39
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v39
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v36
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v36
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v33
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v53
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v51
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
@@ -149317,1766 +150421,1972 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v63
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v58
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v28
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v20
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; kill: killed $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v43
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v55
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v42
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v41
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v38
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v60
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v59
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; kill: killed $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v13
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v32
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(10) expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v33
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v33
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; kill: killed $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB90_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_alignbit_b32 v38, v0, v1, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v50
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v35, v0, v1, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v36, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v32, v0, v1, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v33, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v29, v0, v1, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v29, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v25, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v28
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v26, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v34, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v20, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v34
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v43
+; SI-NEXT: v_mul_f32_e32 v43, 1.0, v44
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v40, v54, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v17, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v55, v52, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v14, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v28
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v40, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v53, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v47
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v11, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v51, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v31
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v23, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v37, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v10, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v37
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v54, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v49, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v7, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v38, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v18, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v6, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v52, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v35, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v5, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_alignbit_b32 v15, v0, v27, 16
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v32, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v50, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v4, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v31
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v30, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v39, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v3, v1, v2, 16
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v13, v0, v53, 16
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v39
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v48, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v27, v2, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
-; SI-NEXT: v_alignbit_b32 v11, v0, v19, 16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v6
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v48, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v23, v8, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v41, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v51
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v41
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_alignbit_b32 v24, v8, v9, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v12
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v19, v8, v9, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v50, 1.0, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v50
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v16, v8, v9, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v42, 1.0, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v42
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v13, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v45
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v43
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v34
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v22
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v28
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v15
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v37
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v18
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v26
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v21
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v31
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v39
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_alignbit_b32 v37, v0, v1, 16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
-; SI-NEXT: v_alignbit_b32 v8, v0, v21, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v48
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 24
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v41
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v12
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v21, 24, v59
-; SI-NEXT: v_mov_b32_e32 v59, v19
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_alignbit_b32 v34, v0, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
-; SI-NEXT: v_alignbit_b32 v5, v0, v41, 16
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v50
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v42
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4) expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v57
-; SI-NEXT: v_alignbit_b32 v4, v1, v36, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
-; SI-NEXT: v_alignbit_b32 v28, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v43
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v45
-; SI-NEXT: v_alignbit_b32 v3, v1, v61, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v40, v36, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v40, v36, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v40, v36, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v55, v33, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v55, v33, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v9
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v55, v33, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v56
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v53, v29, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v33
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v53, v29, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v53, v29, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_alignbit_b32 v25, v1, v2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v44
-; SI-NEXT: v_alignbit_b32 v2, v1, v47, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
-; SI-NEXT: v_alignbit_b32 v22, v1, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v33
-; SI-NEXT: v_alignbit_b32 v20, v7, v10, 16
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v51, v25, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v51, v25, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v51, v25, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v49, v20, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v49, v20, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v49, v20, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v38, v17, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v38, v17, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v38, v17, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v35, v14, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v46
-; SI-NEXT: v_alignbit_b32 v1, v1, v60, 16
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_alignbit_b32 v17, v7, v10, 16
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 24
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v35, v14, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 16
-; SI-NEXT: v_alignbit_b32 v14, v7, v24, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v35, v14, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v32, v11, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v14, v3, 16
-; SI-NEXT: v_alignbit_b32 v10, v19, v30, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v32, v11, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v14, v3, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v32, v11, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v30, v10, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v51
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v30, v10, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v30, v10, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v7, v7, v63, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v27, v7, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v27, v7, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v7, v1, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v27, v7, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v7, v1, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v23, v6, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v40
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v23, v6, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v54
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v23, v6, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v52
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v24, v5, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v50
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v24, v5, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v48
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v24, v5, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v37
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v19, v4, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v34
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v19, v4, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v0
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v19, v4, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v28
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v16, v3, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v25
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v16, v3, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v22
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v16, v3, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v20
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v13, v2, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v17
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v13, v2, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v14
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v13, v2, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v10
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v9, v1, 24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v7
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v58
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v9, v1, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v39
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v8, v9, v1, 8
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v27
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v40
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v49
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v55
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v53
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v53
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v55
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v51
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v41
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v49
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v43
-; SI-NEXT: ; kill: killed $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v39, v14, v3, 24
-; SI-NEXT: v_alignbit_b32 v58, v7, v1, 8
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v38
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v35
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v32
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v30
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v27
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v23
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v24
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v19
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v13
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v8, 8, v9
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; kill: killed $vgpr6
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: .LBB90_2: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB90_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v46
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v60
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v44
-; SI-NEXT: v_alignbit_b32 v1, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v47
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v45
-; SI-NEXT: v_alignbit_b32 v2, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v61
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
+; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v57
-; SI-NEXT: v_alignbit_b32 v3, v3, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v60
+; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v51
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v42
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_add_f32_e32 v36, 0x40c00000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v41
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v62
+; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v44
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v39
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_alignbit_b32 v4, v4, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_alignbit_b32 v5, v7, v5, 16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v36
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v62
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v7, v7, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v21
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v55
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
+; SI-NEXT: v_alignbit_b32 v9, v7, v6, 16
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v6
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v8, v10, v8, 16
-; SI-NEXT: v_alignbit_b32 v10, v59, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v11, v13, v11, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
-; SI-NEXT: v_alignbit_b32 v14, v13, v0, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v53
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_alignbit_b32 v13, v15, v13, 16
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v6
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v36
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v58, v7, v1, 8
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v17, v15, v0, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v27
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_alignbit_b32 v15, v18, v15, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v21
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v34
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v34
-; SI-NEXT: v_alignbit_b32 v32, v34, v32, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v42
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_alignbit_b32 v17, v20, v17, 16
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; SI-NEXT: v_lshrrev_b32_e32 v12, 24, v12
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
-; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; SI-NEXT: v_alignbit_b32 v35, v38, v35, 16
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v52
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_alignbit_b32 v29, v33, v29, 16
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v54
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v40
+; SI-NEXT: v_mul_f32_e32 v49, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
; SI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; SI-NEXT: v_add_f32_e32 v51, 0x40c00000, v50
-; SI-NEXT: v_add_f32_e32 v53, 0x40c00000, v52
-; SI-NEXT: v_add_f32_e32 v55, 0x40c00000, v54
-; SI-NEXT: v_add_f32_e32 v41, 0x40c00000, v40
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v41
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v20, v18, v0, 16
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v56
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_mul_f32_e32 v50, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v50
+; SI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v50, 24, v50
+; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v39, 0x40c00000, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_alignbit_b32 v6, v8, v6, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v39
+; SI-NEXT: v_alignbit_b32 v13, v8, v7, 16
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v27
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v22, v19, v0, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_alignbit_b32 v7, v10, v7, 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v21
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v16, v10, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v23, v23, v19, 16
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v25, v19, v0, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v9
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v27
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v21
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v10
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v26
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v19, v11, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v11
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v11, v14, v11, 16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v24, v14, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v26, v26, v19, 16
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; SI-NEXT: v_alignbit_b32 v28, v19, v0, 16
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v14
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v46
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v23, v15, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v0, v30, v0, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v15
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v27, v20, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v19
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v15
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 24, v24
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v31
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v18
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v26
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v21
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v39
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_add_f32_e32 v37, 0x40c00000, v20
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v20, v22, v20, 16
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v37
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v30, v22, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v63
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_alignbit_b32 v25, v28, v25, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v30
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v22
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v32, v28, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v37
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v28
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v35, v33, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v34, v34, v33, 16
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v30, 24, v30
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v28, 24, v28
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v33
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
-; SI-NEXT: v_add_f32_e32 v37, 0x40c00000, v33
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v33
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v33
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v33
-; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v37, v38, v37, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v33, 24, v33
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v33, v36, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v34
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v38, v36, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v34
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v38
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v39, 0x40c00000, v38
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v36
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
-; SI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
-; SI-NEXT: v_alignbit_b32 v38, v49, v38, 16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v39
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v48, v49, v48, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v39
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v36
+; SI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
+; SI-NEXT: v_alignbit_b32 v36, v49, v36, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v48
+; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v39, v14, v3, 24
+; SI-NEXT: v_alignbit_b32 v49, v49, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v48
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; SI-NEXT: v_alignbit_b32 v50, v50, v49, 16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v51, v51, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; SI-NEXT: v_alignbit_b32 v52, v52, v49, 16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v52, 0x40c00000, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; SI-NEXT: v_alignbit_b32 v54, v54, v49, 16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v41, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v41
+; SI-NEXT: v_alignbit_b32 v53, v8, v52, 16
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v41
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v54, 0x40c00000, v52
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
-; SI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
-; SI-NEXT: v_alignbit_b32 v40, v40, v49, 16
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v52
+; SI-NEXT: v_add_f32_e32 v42, 0x40c00000, v52
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v42
+; SI-NEXT: v_alignbit_b32 v55, v52, v54, 16
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v42
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v40, 0x40c00000, v54
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v54, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v54
+; SI-NEXT: v_add_f32_e32 v43, 0x40c00000, v54
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v43
+; SI-NEXT: v_alignbit_b32 v40, v54, v40, 16
+; SI-NEXT: v_alignbit_b32 v12, v40, v36, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v40, v38, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v40, v36, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v40, v36, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v55, v33, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v54, v35, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v55, v33, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v55, v33, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v53, v29, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v52, v32, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v53, v29, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v53, v29, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v51, v25, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v50, v29, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v51, v25, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v51, v25, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v49, v20, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v48, v26, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v49, v20, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v49, v20, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v38, v17, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v37, v23, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v38, v17, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v38, v17, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v35, v14, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v34, v18, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v35, v14, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v35, v14, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v32, v11, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v0, v15, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v32, v11, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v32, v11, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v30, v10, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v28, v13, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v30, v10, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v30, v10, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v27, v7, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v25, v11, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v27, v7, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v27, v7, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v23, v6, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v22, v8, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v23, v6, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v23, v6, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v24, v5, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v20, v5, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v24, v5, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v24, v5, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v19, v4, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v17, v4, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v19, v4, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v14, v3, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v19, v4, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v14, v3, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v16, v3, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v16, v3, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v16, v3, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v10, v2, 8
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v13, v2, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v7, v1, 24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v13, v2, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v7, v1, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v13, v2, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v40
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v9, v1, 24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v54
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v9, v1, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v52
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v12, v9, v1, 8
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v50
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v40
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v48
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v55
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v37
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v53
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v34
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v51
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v0
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v49
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v28
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v38
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v25
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v35
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v22
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v32
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v20
-; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v41
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v30
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v17
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v27
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v55
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v23
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v14
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v24
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v53
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v19
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v10
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v51
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v13
+; SI-NEXT: v_lshrrev_b32_e32 v43, 24, v43
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v7
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v9
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: .LBB90_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v38
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v36
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_store_dword v6, v31, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: buffer_store_dword v12, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v40
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v40
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 4, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 4, v0
+; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v35
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v33
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 8, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 8, v0
+; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v54
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v55
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 12, v0
+; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v29
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 12, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 16, v0
+; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v53
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v8, v15, v8
+; SI-NEXT: v_or_b32_e32 v8, v12, v8
+; SI-NEXT: v_add_i32_e32 v12, vcc, 20, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v25
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 16, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 24, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v52
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v51
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 20, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 28, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v29
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v20
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 24, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 32, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v50
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v49
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 28, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 36, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v26
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v17
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 32, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 40, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v48
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v38
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 36, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v15, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 44, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v23
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 40, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 48, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v37
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v35
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 44, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 52, v0
+; SI-NEXT: buffer_store_dword v8, v12, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v8, v8, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 48, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_or_b32_e32 v8, v8, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 56, v0
+; SI-NEXT: buffer_store_dword v8, v11, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v34
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v32
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v8, v8, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 52, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_or_b32_e32 v8, v8, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 60, v0
+; SI-NEXT: buffer_store_dword v8, v11, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v15
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v12, v9
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 56, v31
-; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 64, v0
+; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v9, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 60, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x44, v0
+; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v13
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v9, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 64, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x48, v0
+; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v27
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v9, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 0x44, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x4c, v0
+; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v11
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v9, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 0x48, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x50, v0
+; SI-NEXT: buffer_store_dword v6, v7, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v25
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v23
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v9, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 0x4c, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x54, v0
+; SI-NEXT: buffer_store_dword v6, v7, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 0x50, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x58, v0
+; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v22
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v24
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v8, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 0x54, v31
-; SI-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x5c, v0
+; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x58, v31
-; SI-NEXT: buffer_store_dword v0, v5, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x60, v0
+; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v19
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x5c, v31
-; SI-NEXT: buffer_store_dword v0, v5, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x64, v0
+; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v31
-; SI-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x68, v0
+; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v16
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 0x64, v31
-; SI-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x6c, v0
+; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v39
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v31
-; SI-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0
+; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v13
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v31
-; SI-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0
+; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v31
-; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
+; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v9
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v59
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v31
-; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v58
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x78, v31
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v7
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x7c, v31
-; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
@@ -164827,1999 +166137,2103 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v59, v24
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v47, v16
-; SI-NEXT: v_mov_b32_e32 v61, v14
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v60, v6
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v28, v1
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; kill: killed $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; kill: killed $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:380
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:372
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:368
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v21
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:244
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v29
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v43, v8
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:216
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:192
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:76
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:108
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:148
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:144
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v32
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v2
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:300
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:292
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v14
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:376
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v0
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:364
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v20
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:352
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:340
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:328
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:300
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v51, 0xff, v47
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v48, 0xff, v43
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v58
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
+; SI-NEXT: v_or_b32_e32 v21, v6, v21
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v20
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v27
+; SI-NEXT: v_or_b32_e32 v10, v3, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v12
+; SI-NEXT: v_or_b32_e32 v3, v11, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v26
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v59
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v22
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: v_or_b32_e32 v1, v12, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v0, v12
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v60
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mov_b32_e32 v60, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v5
+; SI-NEXT: v_or_b32_e32 v5, v9, v13
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v9, v28
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v17, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v1, v9
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v13, v18, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v10, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v61
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v10, v1, v10
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v18, v18, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v1, v12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v31, v25, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v28, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v15, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v32, v29, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v25, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v33, v28, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v16, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v29, v29, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v19, v19, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v37, v30, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v38, v28, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v20, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v30, v30, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v21, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v39, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v49, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v22, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v35, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v23, v23, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v51, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v53, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v24, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v27, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v55, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v41, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v28, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v50, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v29, v29, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v43, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v54, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v44, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v30, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v52, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v33, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v45, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v55, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v47, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v34, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v54, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v35, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v57, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v41, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v58, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v40, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v37, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v60, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v42, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v61, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v38, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v42, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v62
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v63, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v44, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v45, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v63, v31, v63
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v26, v26, v31
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v16, v16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v7, v7, v31
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v32, v31, v4
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v46, v56, v31
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v20, v20, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v31, v31, v40
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v59
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v31, v31, v9
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v48, v48, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v51, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v22, v22, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v56, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v57, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v58, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v46, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v62, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v56, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v59, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v6, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v62, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v40, v1
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v40, v40, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v60, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v34, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v47, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v61, v43, v59
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v36, v28, v36
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v43, v43, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v59, 0xff, v59
-; SI-NEXT: v_or_b32_e32 v59, v59, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v28, v28, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v5
-; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v11, v9, v10
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v48, v9, v12
-; SI-NEXT: v_alignbit_b32 v9, v11, v12, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v12, v9, v17
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v51
-; SI-NEXT: v_or_b32_e32 v9, v9, v14
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v9, v12, v14, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v17
+; SI-NEXT: v_alignbit_b32 v13, v9, v13, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v51, v9, v25
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v56
-; SI-NEXT: v_or_b32_e32 v15, v9, v16
-; SI-NEXT: v_alignbit_b32 v9, v51, v16, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v9, v9, v49
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v57
-; SI-NEXT: v_or_b32_e32 v16, v13, v20
-; SI-NEXT: v_alignbit_b32 v13, v9, v20, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v31, v13, v50
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v58
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v13, v31, v22, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v62
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: v_or_b32_e32 v14, v14, v24
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v14, v13, v24, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v24, v14, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v14, v28
-; SI-NEXT: v_alignbit_b32 v14, v24, v28, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v21, v14, v54
-; SI-NEXT: v_or_b32_e32 v22, v6, v30
-; SI-NEXT: v_alignbit_b32 v6, v21, v30, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v19, v6, v55
-; SI-NEXT: v_or_b32_e32 v29, v1, v34
-; SI-NEXT: v_alignbit_b32 v1, v19, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v18, v13, v23
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v14, v13, v24
+; SI-NEXT: v_alignbit_b32 v13, v18, v24, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v13, v13, v25
+; SI-NEXT: v_or_b32_e32 v31, v15, v32
+; SI-NEXT: v_alignbit_b32 v15, v13, v32, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v33, v15, v29
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v24, v15, v37
+; SI-NEXT: v_alignbit_b32 v15, v33, v37, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v32, v15, v30
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v19
+; SI-NEXT: v_or_b32_e32 v37, v15, v39
+; SI-NEXT: v_alignbit_b32 v15, v32, v39, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v23, v1, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v20, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v23, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v30, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
-; SI-NEXT: v_or_b32_e32 v27, v1, v38
-; SI-NEXT: v_alignbit_b32 v1, v30, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v28, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v47
-; SI-NEXT: v_or_b32_e32 v34, v1, v45
-; SI-NEXT: v_alignbit_b32 v1, v28, v45, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v49
+; SI-NEXT: v_or_b32_e32 v38, v15, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v15, v15, v51
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v63
-; SI-NEXT: v_or_b32_e32 v33, v1, v26
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v36, v1, v7
-; SI-NEXT: v_alignbit_b32 v1, v33, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v15, v38, v51, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v35, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v38, v1, v46
-; SI-NEXT: v_alignbit_b32 v1, v35, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v53
+; SI-NEXT: v_or_b32_e32 v39, v15, v48
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v15, v15, v55
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v37, v1, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v59
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v0
+; SI-NEXT: v_alignbit_b32 v15, v39, v55, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v49, v15, v50
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v15, v15, v43
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v49, v43, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v44
+; SI-NEXT: v_or_b32_e32 v51, v15, v52
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v27
+; SI-NEXT: v_or_b32_e32 v15, v15, v45
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v51, v45, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v47
+; SI-NEXT: v_or_b32_e32 v53, v15, v54
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v46
+; SI-NEXT: v_or_b32_e32 v15, v15, v57
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v53, v57, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v55, v15, v40
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v56
+; SI-NEXT: v_or_b32_e32 v15, v15, v60
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v55, v60, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v61
+; SI-NEXT: v_or_b32_e32 v41, v15, v42
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v59
+; SI-NEXT: v_or_b32_e32 v15, v15, v63
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v41, v63, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v21
+; SI-NEXT: v_or_b32_e32 v43, v15, v6
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v62
+; SI-NEXT: v_or_b32_e32 v15, v15, v7
+; SI-NEXT: v_alignbit_b32 v7, v43, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v45, v7, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v7, v7, v11
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v7, v45, v11, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v47, v7, v1
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v58, v7, v2
+; SI-NEXT: v_alignbit_b32 v2, v47, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v57, v2, v0
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v39, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v37, v3, 16
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v28
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v60, v2, v4
+; SI-NEXT: v_alignbit_b32 v2, v57, v4, 16
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr4
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; kill: killed $vgpr4
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: .LBB92_2: ; %Flow
-; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
-; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: s_movk_i32 s6, 0x300
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_or_b32_e32 v2, v58, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v37
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v5
+; SI-NEXT: v_or_b32_e32 v9, v13, v9
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v62
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x300, v9
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v13, v9
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v56
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v36
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v15
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v57, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v60, vcc, s7, v9
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v57
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v5, v13, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v59
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v22
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v1, v5, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v56, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v47, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v58, vcc, s7, v0
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v47
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v26
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v35
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v27
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v45, vcc, s7, v3
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v45
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v63, v5
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v5, v8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v20
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v5
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v33
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v5, v7, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v11
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v10
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v6
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v43
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v28
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v7
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v41, vcc, s7, v8
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v32
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v9
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v11
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v55, vcc, s7, v11
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v55
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v12
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v53, vcc, s7, v13
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v15
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v51
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v17
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v24
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v17
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v49
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v18
-; SI-NEXT: v_mov_b32_e32 v18, v5
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v19
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v39
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v25, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v26, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v26
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v31, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v15
-; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v32, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v32
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v48, v20, v19
-; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v25
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v10
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
+; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v51
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v28
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v40, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v0, v11, v48, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v12, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v0, v9, v5, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v18, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v51, v15, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v13, v31, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v33, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v9, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v32, v37, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v38, v3, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v31, v3, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v39, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v49, v6, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v24, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v21, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v19, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v23, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v30, v27, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v28, v34, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v33, v36, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v35, v38, 16
-; SI-NEXT: v_alignbit_b32 v1, v8, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v51, v7, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v53, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v55, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v41, v25, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v43, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v45, v27, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v37, v39, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v47, v58, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v57, v60, 16
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v33
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v45
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v61
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v40
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v48
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v31
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v13
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v24
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v51
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v37
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v49
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v54
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v42
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v44
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v31
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v50
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v24
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v22
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v29
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v18, v18, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v53
-; SI-NEXT: v_or_b32_e32 v19, v19, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v53
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v30
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v34
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v43
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v47
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff, v60
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v57
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
@@ -166836,20 +168250,6 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v36
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v38
-; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -168161,693 +169561,703 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:272
-; GFX9-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:288
-; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:296
-; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:304
-; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:320
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:156
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:152
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:140
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:132
-; GFX9-NEXT: s_waitcnt vmcnt(27)
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:4
+; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: s_waitcnt vmcnt(31)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(26)
-; GFX9-NEXT: v_lshlrev_b16_e32 v53, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(25)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(24)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(23)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v6
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:100
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
+; GFX9-NEXT: s_waitcnt vmcnt(31)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:384
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v7
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v9
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v10
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v11
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v13
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v14
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v15
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v16
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v17
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v18
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:328
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:352
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:324
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:332
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:348
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:344
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:360
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:384
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:356
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:364
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:116
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:260
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:380
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:340
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:372
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:248
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:380
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:376
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:372
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:200
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:200
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:196
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:344
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:376
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:168
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:332
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:328
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:324
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:156
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:320
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:152
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:316
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:148
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:312
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:144
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:308
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:140
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:304
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:300
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:132
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:284
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:124
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB92_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
-; GFX9-NEXT: v_or_b32_sdwa v9, v59, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v47, v45, s6
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v55, v54, s6
-; GFX9-NEXT: v_perm_b32 v17, v43, v42, s6
-; GFX9-NEXT: v_perm_b32 v18, v58, v57, s6
-; GFX9-NEXT: v_perm_b32 v19, v63, v46, s6
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v10, v62, v35, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v60
+; GFX9-NEXT: v_or_b32_sdwa v11, v63, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v59, v58, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v13, v44, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v43, v42, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v53
+; GFX9-NEXT: v_or_b32_sdwa v15, v52, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr35
+; GFX9-NEXT: ; implicit-def: $vgpr63
+; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr55
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr58
-; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr46
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: ; implicit-def: $vgpr52
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v33, s6
+; GFX9-NEXT: v_perm_b32 v8, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v60, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
+; GFX9-NEXT: v_or_b32_sdwa v8, v38, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v36, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v44, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v9, v61, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v41, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v32, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v52, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v57
+; GFX9-NEXT: v_or_b32_sdwa v11, v56, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr44
-; GFX9-NEXT: ; implicit-def: $vgpr41
-; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v12, v50, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v12, v46, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr50
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v37, v36, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v13, v40, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v55
+; GFX9-NEXT: v_or_b32_sdwa v14, v54, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v51, v50, s6
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr57
+; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr55
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_sdwa v15, v62, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v17, v16, s6
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v35, s6
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
-; GFX9-NEXT: v_perm_b32 v16, v32, v56, s6
+; GFX9-NEXT: v_perm_b32 v17, v18, v17, s6
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s7
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v17, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr62
-; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s7
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v20, v20, v61, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s7
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v21, v21, v22, s6
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s7
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s7
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s6
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v23, v23, v48, s6
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s7
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s7
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s6
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s7
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s7
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s6
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s7
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s7
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s6
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s7
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v30, 8, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s7
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v32, v33, v32, s6
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s7
@@ -168916,80 +170326,94 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; kill: killed $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB92_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB92_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v33
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v45
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v11, v38, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
-; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v46
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v56
-; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v42
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v34
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v60
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v45
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v41
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v49
+; GFX9-NEXT: v_mov_b32_e32 v29, v48
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(20)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(19)
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: s_waitcnt vmcnt(18)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
+; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(12)
+; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(9)
+; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: s_waitcnt vmcnt(11)
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v9
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
+; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
+; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -168997,16 +170421,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v2
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v3
; GFX9-NEXT: v_perm_b32 v0, v2, v0, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
@@ -169015,312 +170439,330 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: v_add_u16_e32 v8, 3, v60
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v8, v53, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v9, v51, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v8, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v36
+; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s6
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v10, v49, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v61
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v41
-; GFX9-NEXT: v_or_b32_sdwa v10, v39, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v63
+; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s6
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v55
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v52
-; GFX9-NEXT: v_or_b32_sdwa v12, v34, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v56
+; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s6
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v50
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v47
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v48
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v44
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s6
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v37
-; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v36
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v43
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v40
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s6
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v52
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v35
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v50
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v62
-; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v57
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v17, 3, v63
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v18, 3, v32
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 3, v43
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v16
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v18
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v19
; GFX9-NEXT: v_perm_b32 v16, v18, v16, s6
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v17, v17, v20, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v19
; GFX9-NEXT: v_perm_b32 v31, v32, v31, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v21
; GFX9-NEXT: v_perm_b32 v30, v33, v30, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v23
-; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v36, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v36
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v37, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v38, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v39, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v39
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v48, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v49, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v50, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v50
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
+; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v51, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v51
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v52, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v53, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v53
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v54, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v55, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v55
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v40, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v61
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v50, 0x300, v40
; GFX9-NEXT: v_perm_b32 v21, v50, v21, s6
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v41, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v41
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v42, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v51, 0x300, v42
; GFX9-NEXT: v_perm_b32 v20, v51, v20, s6
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -169328,23 +170770,23 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v43, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v43
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v44, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v45, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v45
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
@@ -169394,742 +170836,754 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:488
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:484
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:384
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:368
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:360
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:352
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:328
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB92_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v96, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v118, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v132, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v151, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v164, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v85, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v166, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v113, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v112, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v129, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v117, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v145, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v178, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v161, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v87, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v37.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v115, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v49.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v144, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v15.h, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v167, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v182, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v42, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v160, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v46, v183, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v57, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v176, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v61, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v45, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v26.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.h, 8, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v44, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v56, v41, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v63, v59, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.h, 8, v52.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v58, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.l, v26.h
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v25.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v73, v62, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.h, v28.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v65.l
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v76, v74, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
-; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
-; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v69.h
+; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v31.l, v31.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v77, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v32.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: .LBB92_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB92_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v79.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v78.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v71.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v69.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v68.h, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v76.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v73.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v62.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v53.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v72.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v60.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v59.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v61.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v47.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v41.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v44.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v40.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v181.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v46.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v42.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v180.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v176.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v182.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v150.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v149.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v167.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v148.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v128.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v38.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v144.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v37.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v102.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v35.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v161.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v135.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v166.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v164.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v133.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v130.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v117.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v100.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v129.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v112.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v101.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v103.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -170142,32 +171596,31 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v32.h
; GFX11-TRUE16-NEXT: .LBB92_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:392
-; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:488
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:392
+; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:484
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -170224,165 +171677,128 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v24 :: v_dual_mov_b32 v51, v19
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v71, v20
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v67, v17
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v65, v18
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v16 :: v_dual_mov_b32 v50, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v14 :: v_dual_mov_b32 v53, v9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:364
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:360
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:356
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:352
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v6, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:312
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:308
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:304
-; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:284
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:280
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:276
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:384
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:380
+; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:360
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:356
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:352
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:348
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:308
+; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:304
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:300
+; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:280
+; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:276
+; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:272
+; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:252
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:232
-; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:228
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:224
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:192
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:188
-; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:184
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:180
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:152
-; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:148
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:136
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:248
+; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:228
+; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:224
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:220
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:188
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:184
+; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:180
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:176
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:148
+; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:144
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_b32 v13, off, s32 offset:388
-; GFX11-FAKE16-NEXT: scratch_load_u16 v14, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v15, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v16, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v17, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v18, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v19, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v20, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v21, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v22, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v23, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v24, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v126, 8, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v125, 8, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v123, 8, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v122, 8, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v124, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v121, 8, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v120, 8, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v111, 8, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v110, 8, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v108, 8, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v109, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v107, 8, v12
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(28)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v182, 8, v14
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v166, 8, v15
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(26)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v180, 8, v16
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v46, 8, v17
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v47, 8, v18
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(23)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v56, 8, v19
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v75, 8, v20
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v59, 8, v21
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v74, 8, v22
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v95, 8, v23
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v90, 8, v24
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v30 :: v_dual_mov_b32 v85, v29
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, v28 :: v_dual_mov_b32 v81, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v27 :: v_dual_mov_b32 v83, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v71, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v65, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v69, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v17 :: v_dual_mov_b32 v52, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v15 :: v_dual_mov_b32 v64, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v13 :: v_dual_mov_b32 v32, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v33, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -170392,124 +171808,147 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v37, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v48, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v39, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v55, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v65, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v49, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v84, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v82, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v70, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v118
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v113
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v86, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v71, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v70, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v82, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v86, v85, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v84, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v102
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v99
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v7, v182
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v134
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v129
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v112, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v166
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v7, v46
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v47
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v132
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v151
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v145
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v150
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v75
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v162
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v130, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v14, v59
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v74
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v148, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v11, v95
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v90
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v116
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v107
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v103, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v131, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v102, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v147, v146, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v133, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v149, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v18, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v20, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v24, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v177, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v165, v161, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v183, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v179, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v43, v42, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v40, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v60, v57, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v44, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v72
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v21, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v27, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v58
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v109
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v73
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v63
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v24, v108
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v61, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v27, v111
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v120
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v110
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v91
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v103
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v113
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v147
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v129
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v117, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v14, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v119
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v162
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v150
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v145
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v165
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v151
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v131, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v163, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v161, v146, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v149, v144, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v177, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v17, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v180, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v176, v164, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v181, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v44, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v42, v183, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v57, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v47, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v72, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v59, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v78
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v75
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v73
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v88
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v94
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v105
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v27, v122
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v106
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v121
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v76, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v29, v124
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v123
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v89, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v27, v125
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v126
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v34, v127
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v104, v93, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v28, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v35, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v33, v36, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v34, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v76
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v60, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v58, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v23, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v79, v74, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v104
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v77
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v26, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v32, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v95
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v92
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v111
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v109
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v107
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v93
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v110
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v32, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v127
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v123
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v121
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v120
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xff, v126
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v124
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v94, v90, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v108, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v35, v36
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v38
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v125, v122, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v32, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v35, v36, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
@@ -170519,13 +171958,13 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
@@ -170534,346 +171973,364 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: .LBB92_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB92_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v104, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v105, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v93
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v94, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v125, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v126, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v122
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v124
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v127, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v92, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v121, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v123
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v120
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v127, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v89, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v125, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v126, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v108, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v89, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v77
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v91, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v88, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v76, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v62
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v123, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v124, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v78, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v122, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v108, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v105
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v110, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v105, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v107, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v94, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v93
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v90
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v95, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v90, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v104, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v92, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v91, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v88, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v74
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v76
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v78, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v74, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v75
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v73, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v73, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v121, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v62, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v61, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v72, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v61, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v63, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v120, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v111, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v45
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v45, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v110, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v58, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v60, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v42
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v58, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v109, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v60
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v58, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v72, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v61
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v59, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v46, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v56
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v57, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v56, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v47, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v57
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v43, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v108, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v43, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v42, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v41
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v183
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v40, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v183, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v181
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v183, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v181, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v179, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v182
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v181, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v180, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v178
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v176
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v176, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v165, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v176, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v177, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v164, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v161, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v164
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v167
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v166, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v164, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v160
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v149, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v147, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v160, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v149, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v144
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v146
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v144, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v165, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v148
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v146
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v133, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v151
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v162, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v146, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v131, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v131, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v118
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v134, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v119
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v128
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v117, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v118, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v102
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v102, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v98, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v129
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v128, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v115, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v96, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v167, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v107, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v162, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v148, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v95, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v150, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v135
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v151, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v90, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v116
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v113, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v101
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v100, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v74, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v75, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v130, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v103, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v132, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v59, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v129, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v114, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v56, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v99, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v86, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v46, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v47, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v101
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v113, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v101, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v180, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v182, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v85
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v166, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v85
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v84, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v84, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
@@ -170901,28 +172358,28 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v64, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v54
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v53
; GFX11-FAKE16-NEXT: v_add_nc_u16 v52, v52, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v66, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v51, 8, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v50, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v49
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v52
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v55, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v51, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v49, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v50, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v51, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v50, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v49, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v39, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v38, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v37, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xff, v39
@@ -170954,30 +172411,30 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v68, v67, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v84, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v100, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v98, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v97, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v102, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v117, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v147, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v161, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v176, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v181, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v40, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v58, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v45, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v61, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v73, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v77, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v89, v31, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v84, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v98, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v112, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v117, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v131, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v144, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v160, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v164, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v180, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v183, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v43, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v56, v23, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v46, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v62, v25, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v74, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v77, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v92, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v90, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v105, v30, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v108, v31, 0x5040100
; GFX11-FAKE16-NEXT: .LBB92_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -177554,989 +179011,1068 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v24
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v31, v30
-; VI-NEXT: v_mov_b32_e32 v30, v29
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:8
-; VI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4
-; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v12
-; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v31
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v25
-; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v22
-; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v20
-; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v18
-; VI-NEXT: v_lshrrev_b32_e32 v63, 16, v17
-; VI-NEXT: ; kill: killed $vgpr24
-; VI-NEXT: ; implicit-def: $vgpr24
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: ; kill: killed $vgpr7
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: v_mov_b32_e32 v31, v26
+; VI-NEXT: v_mov_b32_e32 v30, v25
+; VI-NEXT: v_mov_b32_e32 v51, v24
+; VI-NEXT: v_mov_b32_e32 v50, v23
+; VI-NEXT: v_mov_b32_e32 v53, v20
+; VI-NEXT: v_mov_b32_e32 v52, v19
+; VI-NEXT: v_mov_b32_e32 v24, v18
+; VI-NEXT: v_mov_b32_e32 v23, v17
+; VI-NEXT: ; kill: killed $vgpr7
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: ; implicit-def: $vgpr8
+; VI-NEXT: ; implicit-def: $vgpr59
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr57
-; VI-NEXT: ; implicit-def: $vgpr33
-; VI-NEXT: ; kill: killed $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr61
+; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; implicit-def: $vgpr19
+; VI-NEXT: ; implicit-def: $vgpr47
+; VI-NEXT: ; implicit-def: $vgpr13
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr46
+; VI-NEXT: ; implicit-def: $vgpr34
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr63
+; VI-NEXT: ; implicit-def: $vgpr60
+; VI-NEXT: ; implicit-def: $vgpr36
+; VI-NEXT: ; implicit-def: $vgpr62
+; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; kill: killed $vgpr7
+; VI-NEXT: ; implicit-def: $vgpr58
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr42
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr45
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: s_waitcnt vmcnt(14)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
-; VI-NEXT: s_waitcnt vmcnt(13)
-; VI-NEXT: v_lshrrev_b32_e32 v44, 16, v51
-; VI-NEXT: s_waitcnt vmcnt(12)
-; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v50
-; VI-NEXT: ; kill: killed $vgpr23
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: ; implicit-def: $vgpr60
-; VI-NEXT: ; implicit-def: $vgpr62
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: ; implicit-def: $vgpr35
+; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; kill: killed $vgpr29
+; VI-NEXT: ; kill: killed $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; kill: killed $vgpr6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB94_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v16
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v16
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v15
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v14
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v14
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v13
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v12
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v12
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v11
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v10
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v10
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v9
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v7
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v6
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v6
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v5
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v4
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v4
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v3
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v2
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v2
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v1
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v51
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v51
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v50
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v31
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v31
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v30
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v28
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v28
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v27
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v26
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v26
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v25
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v24, 8, v20
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v24, 8, v19
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v29, v49
-; VI-NEXT: v_lshrrev_b64 v[48:49], 24, v[5:6]
-; VI-NEXT: v_mov_b32_e32 v49, v29
+; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v16
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v15
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v15
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[15:16]
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v31
+; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v24
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v52
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v16
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v23
+; VI-NEXT: v_lshrrev_b32_e32 v32, 24, v16
+; VI-NEXT: v_lshrrev_b32_e32 v44, 24, v28
+; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21
+; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v53
+; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v24
+; VI-NEXT: v_lshrrev_b32_e32 v11, 24, v22
+; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v22
+; VI-NEXT: v_lshrrev_b32_e32 v62, 24, v53
+; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v52
; VI-NEXT: s_waitcnt vmcnt(14)
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v55
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v55
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v54
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v22
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v21
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v18
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v23, 8, v17
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[15:16]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[9:10]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[50:51]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[30:31]
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v29, v44
-; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[3:4]
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[27:28]
-; VI-NEXT: v_mov_b32_e32 v44, v29
-; VI-NEXT: v_mov_b32_e32 v29, v47
-; VI-NEXT: v_lshrrev_b64 v[46:47], 24, v[1:2]
-; VI-NEXT: v_mov_b32_e32 v47, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v29, v63
-; VI-NEXT: v_lshrrev_b64 v[62:63], 24, v[54:55]
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[25:26]
-; VI-NEXT: v_mov_b32_e32 v63, v29
-; VI-NEXT: v_mov_b32_e32 v29, v61
-; VI-NEXT: v_lshrrev_b64 v[60:61], 24, v[21:22]
-; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; VI-NEXT: v_mov_b32_e32 v61, v29
-; VI-NEXT: v_mov_b32_e32 v29, v56
-; VI-NEXT: v_lshrrev_b64 v[55:56], 24, v[17:18]
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v22
-; VI-NEXT: v_lshrrev_b32_e32 v57, 24, v20
-; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v18
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v56, v29
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v20
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v19
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v19
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v8
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v8
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v7
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v7
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v39
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v39
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v38
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v38
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[19:20]
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[7:8]
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[38:39]
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v61, 24, v39
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v46
+; VI-NEXT: v_lshrrev_b32_e32 v57, 24, v18
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; VI-NEXT: v_lshrrev_b64 v[38:39], 24, v[30:31]
+; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v37
+; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v37
+; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v46
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v55
+; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v55
+; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[36:37]
+; VI-NEXT: v_mov_b32_e32 v39, v54
+; VI-NEXT: v_lshrrev_b32_e32 v42, 24, v56
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v30
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v50
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v20
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v21
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v53
+; VI-NEXT: v_mov_b32_e32 v19, v35
+; VI-NEXT: v_mov_b32_e32 v8, v25
+; VI-NEXT: v_lshrrev_b32_e32 v47, 24, v20
+; VI-NEXT: v_mov_b32_e32 v20, v32
+; VI-NEXT: v_lshrrev_b32_e32 v32, 24, v51
+; VI-NEXT: s_waitcnt vmcnt(13)
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v6
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v5
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[5:6]
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v6
+; VI-NEXT: v_mov_b32_e32 v5, v13
+; VI-NEXT: v_mov_b32_e32 v13, v34
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v10
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v9
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v9
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v37
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v36
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v36
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v46
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v45
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v45
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v18
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v18
+; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[9:10]
+; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v10
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v17
+; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v10
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v56
+; VI-NEXT: v_mov_b32_e32 v37, v40
+; VI-NEXT: v_mov_b32_e32 v40, v48
+; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[45:46]
+; VI-NEXT: v_lshrrev_b64 v[45:46], 24, v[17:18]
+; VI-NEXT: v_mov_b32_e32 v18, v57
+; VI-NEXT: v_mov_b32_e32 v57, v1
+; VI-NEXT: v_mov_b32_e32 v48, v2
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[55:56]
+; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[52:53]
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v56
+; VI-NEXT: v_lshrrev_b64 v[55:56], 24, v[23:24]
+; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v28
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v27
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v31
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v31
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v30
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v51
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v51
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v50
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v46, v33
+; VI-NEXT: v_mov_b32_e32 v17, v26
+; VI-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
+; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[50:51]
+; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[21:22]
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v12, 24, v24
+; VI-NEXT: v_mov_b32_e32 v10, v60
+; VI-NEXT: v_mov_b32_e32 v60, v49
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v36, v29
+; VI-NEXT: v_mov_b32_e32 v34, v4
+; VI-NEXT: v_mov_b32_e32 v26, v58
+; VI-NEXT: v_mov_b32_e32 v58, v44
+; VI-NEXT: v_mov_b32_e32 v44, v41
; VI-NEXT: .LBB94_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB94_4
; VI-NEXT: ; %bb.3: ; %cmp.true
-; VI-NEXT: v_mov_b32_e32 v42, 0x200
-; VI-NEXT: v_add_f16_sdwa v23, v18, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
-; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
-; VI-NEXT: v_add_f16_sdwa v23, v17, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v57, v18, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
-; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
-; VI-NEXT: v_add_f16_sdwa v23, v20, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v56, v17, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
-; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
-; VI-NEXT: v_add_f16_sdwa v23, v19, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
-; VI-NEXT: v_or_b32_e32 v59, v20, v29
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
-; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: v_add_f16_sdwa v20, v51, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v51, 0x200, v51
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_sdwa v37, v10, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_add_f16_sdwa v45, v14, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_or_b32_e32 v58, v19, v29
-; VI-NEXT: v_add_f16_sdwa v19, v22, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_mov_b32_e32 v45, 0x200
+; VI-NEXT: v_add_f16_sdwa v1, v24, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
+; VI-NEXT: v_or_b32_e32 v57, v24, v29
+; VI-NEXT: v_add_f16_sdwa v29, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_add_f16_e32 v23, 0x200, v23
+; VI-NEXT: v_add_f16_sdwa v1, v53, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: v_or_b32_e32 v56, v23, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; VI-NEXT: v_add_f16_e32 v53, 0x200, v53
+; VI-NEXT: v_or_b32_e32 v59, v53, v29
+; VI-NEXT: v_add_f16_sdwa v29, v52, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v52, 0x200, v52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_add_f16_sdwa v9, v22, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v22
-; VI-NEXT: v_add_f16_sdwa v19, v21, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v19, v21, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v21
+; VI-NEXT: v_add_f16_sdwa v10, v51, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v51, 0x200, v51
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_sdwa v1, v31, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v31, 0x200, v31
+; VI-NEXT: v_add_f16_sdwa v7, v30, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: v_add_f16_sdwa v37, v28, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_sdwa v13, v16, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
+; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v58, v52, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v9
; VI-NEXT: v_or_b32_e32 v55, v22, v29
-; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: s_waitcnt vmcnt(5)
-; VI-NEXT: v_add_f16_sdwa v19, v24, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
-; VI-NEXT: v_add_f16_sdwa v22, v8, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_or_b32_e32 v54, v21, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v10
+; VI-NEXT: v_add_f16_sdwa v19, v50, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v61, v51, v29
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v23, 0x200, v23
-; VI-NEXT: v_or_b32_e32 v61, v24, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v26, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
-; VI-NEXT: v_add_f16_sdwa v24, v4, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT: v_add_f16_sdwa v21, v6, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_or_b32_e32 v60, v23, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v25, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v25, 0x200, v25
-; VI-NEXT: v_or_b32_e32 v63, v26, v29
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v28, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
-; VI-NEXT: v_add_f16_sdwa v26, v31, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v31, 0x200, v31
-; VI-NEXT: v_add_f16_sdwa v23, v12, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
-; VI-NEXT: v_or_b32_e32 v62, v25, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v27, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v50, 0x200, v50
+; VI-NEXT: v_or_b32_e32 v60, v50, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; VI-NEXT: v_or_b32_e32 v63, v31, v29
+; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_sdwa v19, v27, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, 0x200, v27
+; VI-NEXT: s_waitcnt vmcnt(8)
+; VI-NEXT: v_add_f16_sdwa v1, v6, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
+; VI-NEXT: v_add_f16_sdwa v20, v5, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; VI-NEXT: s_waitcnt vmcnt(8)
+; VI-NEXT: v_add_f16_sdwa v26, v3, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v62, v30, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v37
; VI-NEXT: v_or_b32_e32 v39, v28, v29
-; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v50, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v50, 0x200, v50
-; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_sdwa v25, v30, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v38, v27, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
-; VI-NEXT: v_or_b32_e32 v34, v31, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
-; VI-NEXT: v_or_b32_e32 v33, v30, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; VI-NEXT: v_or_b32_e32 v34, v6, v29
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: v_or_b32_e32 v36, v51, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v2, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v35, v50, v29
+; VI-NEXT: v_or_b32_e32 v33, v5, v29
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: v_add_f16_sdwa v1, v2, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(6)
+; VI-NEXT: v_add_f16_sdwa v27, v5, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(5)
+; VI-NEXT: v_add_f16_sdwa v42, v6, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
+; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v42
+; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v36, v6, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v27
+; VI-NEXT: v_or_b32_e32 v35, v5, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; VI-NEXT: v_or_b32_e32 v47, v3, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; VI-NEXT: v_or_b32_e32 v46, v2, v29
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: v_mov_b32_e32 v27, v50
+; VI-NEXT: v_mov_b32_e32 v28, v51
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_add_f16_sdwa v3, v1, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_f16_sdwa v25, v2, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT: v_add_f16_sdwa v20, v1, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_or_b32_e32 v47, v2, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v46, v1, v29
-; VI-NEXT: v_add_f16_sdwa v20, v3, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v24
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v44, v2, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v3
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; VI-NEXT: v_or_b32_e32 v43, v1, v29
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_add_f16_sdwa v5, v3, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_f16_sdwa v18, v4, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT: v_or_b32_e32 v44, v4, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v43, v3, v29
-; VI-NEXT: v_add_f16_sdwa v20, v5, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v21
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v18
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v49, v4, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v5
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; VI-NEXT: v_or_b32_e32 v48, v3, v29
+; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[35:36]
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_add_f16_sdwa v7, v5, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_f16_sdwa v17, v6, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_or_b32_e32 v49, v6, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v48, v5, v29
-; VI-NEXT: v_add_f16_sdwa v20, v7, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v22
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v17
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v51, v6, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
+; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: v_or_b32_e32 v50, v5, v29
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v44
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v43
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v47
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v46
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v36
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v35
+; VI-NEXT: v_lshrrev_b64 v[35:36], 24, v[38:39]
+; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v34
+; VI-NEXT: v_mov_b32_e32 v5, v17
+; VI-NEXT: v_mov_b32_e32 v17, v26
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v39
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v38
+; VI-NEXT: v_lshrrev_b64 v[38:39], 24, v[62:63]
+; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v63
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v62
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v61
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v60
+; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v58
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: v_add_f16_sdwa v12, v7, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v11, v8, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_or_b32_e32 v51, v8, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v50, v7, v29
-; VI-NEXT: v_add_f16_sdwa v20, v9, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v37
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_or_b32_e32 v53, v10, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v52, v9, v29
-; VI-NEXT: v_add_f16_sdwa v20, v11, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
-; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
-; VI-NEXT: v_or_b32_e32 v41, v12, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v40, v11, v29
-; VI-NEXT: v_add_f16_sdwa v20, v13, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v45
-; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_or_b32_e32 v32, v14, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: v_mov_b32_e32 v27, v30
-; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mov_b32_e32 v28, v31
-; VI-NEXT: v_or_b32_e32 v31, v13, v29
-; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_add_f16_sdwa v42, v15, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v11
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v53, v8, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
+; VI-NEXT: v_or_b32_e32 v52, v7, v29
+; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_add_f16_sdwa v12, v7, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_f16_sdwa v14, v8, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v14
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v41, v8, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
+; VI-NEXT: v_or_b32_e32 v40, v7, v29
+; VI-NEXT: v_add_f16_sdwa v12, v20, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
+; VI-NEXT: v_add_f16_sdwa v7, v19, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v32, v20, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
+; VI-NEXT: v_or_b32_e32 v31, v19, v29
+; VI-NEXT: v_add_f16_sdwa v7, v15, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v13
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
; VI-NEXT: v_or_b32_e32 v30, v16, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v42
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
; VI-NEXT: v_or_b32_e32 v29, v15, v29
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v30
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v29
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v32
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v31
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v41
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v40
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v53
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v52
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v51
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v50
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v49
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v48
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v44
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v43
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v47
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v46
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v36
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v35
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v34
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v33
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v39
-; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[29:30]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v38
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v63
-; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v62
-; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[31:32]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v61
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v60
-; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v55
-; VI-NEXT: v_mov_b32_e32 v31, v28
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v54
-; VI-NEXT: v_mov_b32_e32 v30, v27
-; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[40:41]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v59
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[33:34]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v58
-; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v57
-; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[52:53]
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v56
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[38:39]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v20, v25, 8, 8
-; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[43:44]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v40, v45
-; VI-NEXT: v_bfe_u32 v20, v45, 8, 8
-; VI-NEXT: v_mov_b32_e32 v45, v23
-; VI-NEXT: v_mov_b32_e32 v52, v26
-; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[50:51]
-; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v20, v45, 8, 8
-; VI-NEXT: v_lshrrev_b64 v[35:36], 24, v[35:36]
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[62:63]
-; VI-NEXT: v_lshrrev_b64 v[62:63], 24, v[60:61]
-; VI-NEXT: v_lshrrev_b64 v[60:61], 24, v[54:55]
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[29:30]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[31:32]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[40:41]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[52:53]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[50:51]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[46:47]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[33:34]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v30
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v29
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v32
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v31
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v41
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v40
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v53
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v52
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v51
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v50
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v49
+; VI-NEXT: v_mov_b32_e32 v51, v28
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v48
+; VI-NEXT: v_mov_b32_e32 v50, v27
+; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[43:44]
+; VI-NEXT: v_mov_b32_e32 v8, v25
+; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v55
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v54
+; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[54:55]
; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[58:59]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v59, v37
-; VI-NEXT: v_bfe_u32 v20, v37, 8, 8
-; VI-NEXT: v_mov_b32_e32 v37, v22
-; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v20, v37, 8, 8
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; VI-NEXT: v_lshrrev_b64 v[48:49], 24, v[48:49]
-; VI-NEXT: v_lshrrev_b64 v[46:47], 24, v[46:47]
-; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v20, v21, 8, 8
-; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: v_mov_b32_e32 v32, v10
+; VI-NEXT: v_mov_b32_e32 v10, v14
+; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v33
+; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[60:61]
+; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v56
; VI-NEXT: v_lshrrev_b64 v[55:56], 24, v[56:57]
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v20, v24, 8, 8
-; VI-NEXT: v_mov_b32_e32 v35, v19
-; VI-NEXT: v_bfe_u32 v19, v19, 8, 8
-; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; VI-NEXT: v_mov_b32_e32 v58, v21
-; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v34, v24
+; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v57
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v56, v10, 8, 8
+; VI-NEXT: v_mov_b32_e32 v10, v18
+; VI-NEXT: v_bfe_u32 v57, v18, 8, 8
+; VI-NEXT: v_bfe_u32 v18, v42, 8, 8
+; VI-NEXT: v_mov_b32_e32 v45, v9
+; VI-NEXT: v_lshrrev_b64 v[48:49], 24, v[48:49]
+; VI-NEXT: v_mov_b32_e32 v19, v12
+; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v59
+; VI-NEXT: v_bfe_u32 v20, v13, 8, 8
+; VI-NEXT: v_bfe_u32 v47, v19, 8, 8
+; VI-NEXT: v_bfe_u32 v61, v11, 8, 8
+; VI-NEXT: v_bfe_u32 v26, v5, 8, 8
+; VI-NEXT: v_bfe_u32 v59, v8, 8, 8
+; VI-NEXT: v_bfe_u32 v40, v17, 8, 8
+; VI-NEXT: v_bfe_u32 v58, v37, 8, 8
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v32, v32, 8, 8
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v11, v45, 8, 8
+; VI-NEXT: v_mov_b32_e32 v45, v3
+; VI-NEXT: v_bfe_u32 v62, v36, 8, 8
; VI-NEXT: s_waitcnt vmcnt(14)
-; VI-NEXT: v_bfe_u32 v23, v44, 8, 8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v23, v52, 8, 8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v23, v32, 8, 8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v23, v42, 8, 8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v33, v53, 8, 8
-; VI-NEXT: v_bfe_u32 v23, v41, 8, 8
-; VI-NEXT: v_bfe_u32 v57, v49, 8, 8
-; VI-NEXT: v_bfe_u32 v38, v47, 8, 8
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v42, v1, 8, 8
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; VI-NEXT: v_bfe_u32 v12, v39, 8, 8
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bfe_u32 v37, v1, 8, 8
; VI-NEXT: .LBB94_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v29, v24, v46, s4
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v29, v6, v1, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v24, s4
+; VI-NEXT: v_perm_b32 v1, v1, v6, s4
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; VI-NEXT: v_or_b32_e32 v1, v1, v29
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v2, v2, v24, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v35, v1, s4
+; VI-NEXT: v_perm_b32 v1, v17, v40, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v2, v2, v6, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v1, v43, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v1, v7, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v4, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v34, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v8, v59, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v4, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v1, v48, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v5, v2, s4
+; VI-NEXT: v_perm_b32 v1, v1, v48, s4
+; VI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v48, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v6, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v58, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v10, v57, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v49, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v7, v2, s4
+; VI-NEXT: v_perm_b32 v2, v40, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v8, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v37, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v5, v26, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v41, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v10, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v59, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v61, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v11, v2, s4
+; VI-NEXT: v_perm_b32 v2, v40, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_perm_b32 v1, v41, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v45, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v56, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v13, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v4, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v40, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v19, v47, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v3, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v13, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v1, v63, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v23, v46, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v17, v2, s4
+; VI-NEXT: v_perm_b32 v1, v1, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v47, v38, s4
+; VI-NEXT: v_perm_b32 v2, v39, v12, s4
+; VI-NEXT: v_perm_b32 v1, v24, v34, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v1, v56, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v52, v63, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v19, v2, s4
+; VI-NEXT: v_perm_b32 v1, v1, v54, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v49, v57, s4
+; VI-NEXT: v_perm_b32 v2, v36, v62, s4
+; VI-NEXT: v_perm_b32 v1, v53, v60, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v39, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v21, v44, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v21, v1, s4
+; VI-NEXT: v_perm_b32 v2, v2, v25, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v53, v33, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v22, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_perm_b32 v2, v2, v11, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v50, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: v_perm_b32 v2, v36, v62, s4
+; VI-NEXT: v_perm_b32 v2, v2, v33, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v3, v1, s4
+; VI-NEXT: v_perm_b32 v1, v51, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v41, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v32, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v25, v1, s4
+; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v38, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v42, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v37, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v27, v1, s4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v35, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v32, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v58, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v30, v14, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v52, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v42, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_perm_b32 v1, v50, v1, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v2, v1, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v45, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v51, v1, s4
+; VI-NEXT: v_perm_b32 v1, v3, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v44, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v18, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -185454,1999 +186990,2103 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v59, v24
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v47, v16
-; SI-NEXT: v_mov_b32_e32 v61, v14
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v60, v6
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:388
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v28, v1
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; kill: killed $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; kill: killed $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; kill: killed $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:292
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:380
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:372
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:368
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:364
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:264
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v21
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:244
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v29
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v43, v8
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:216
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:192
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:76
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:172
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:108
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:148
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:144
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v32
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v2
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:300
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:292
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v14
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:376
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v0
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:364
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v15
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v20
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:352
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:340
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:328
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:312
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:300
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v51, 0xff, v47
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v48, 0xff, v43
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v58
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
+; SI-NEXT: v_or_b32_e32 v21, v6, v21
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v20
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v27
+; SI-NEXT: v_or_b32_e32 v10, v3, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v12
+; SI-NEXT: v_or_b32_e32 v3, v11, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v26
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v59
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v8, v8, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v22
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: v_or_b32_e32 v1, v12, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v15
+; SI-NEXT: v_or_b32_e32 v12, v0, v12
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v60
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mov_b32_e32 v60, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v5
+; SI-NEXT: v_or_b32_e32 v5, v9, v13
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v9, v28
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v17, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v1, v9
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v13, v18, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v10, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v61
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v10, v1, v10
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v18, v18, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v1, v12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v31, v25, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v25, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v28, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v15, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v32, v29, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v25, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v33, v28, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v16, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v29, v29, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v19, v19, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v37, v30, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v38, v28, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v20, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v30, v30, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v21, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v39, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v49, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v22, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v35, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v23, v23, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v51, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v53, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v24, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v27, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v55, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v41, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v28, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v50, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v29, v29, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v43, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v54, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v44, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v30, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v52, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v33, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v45, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v55, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v47, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v34, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v54, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v35, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v57, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v41, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v58, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v40, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v37, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v60, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v42, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v61, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v38, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v42, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v62
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v63, v34, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v44, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v45, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v63, v31, v63
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v26, v26, v31
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v16, v16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v7, v7, v31
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v32, v31, v4
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v46, v56, v31
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v20, v20, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v31, v31, v40
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v59
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v31, v31, v9
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v48, v48, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v51, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v22, v22, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v56, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v57, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v27, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v58, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v46, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v62, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v56, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v59, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v6, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v62, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v40, v1
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v40, v40, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v60, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v34, v28, v34
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v47, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v61, v43, v59
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v36, v28, v36
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v43, v43, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v59, 0xff, v59
-; SI-NEXT: v_or_b32_e32 v59, v59, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v28, v28, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v5
-; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v11, v9, v10
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v48, v9, v12
-; SI-NEXT: v_alignbit_b32 v9, v11, v12, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v12, v9, v17
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v51
-; SI-NEXT: v_or_b32_e32 v9, v9, v14
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v9, v12, v14, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v17
+; SI-NEXT: v_alignbit_b32 v13, v9, v13, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v51, v9, v25
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v56
-; SI-NEXT: v_or_b32_e32 v15, v9, v16
-; SI-NEXT: v_alignbit_b32 v9, v51, v16, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v9, v9, v49
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v57
-; SI-NEXT: v_or_b32_e32 v16, v13, v20
-; SI-NEXT: v_alignbit_b32 v13, v9, v20, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v31, v13, v50
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v58
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v13, v31, v22, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v62
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: v_or_b32_e32 v14, v14, v24
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v14, v13, v24, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v24, v14, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v14, v28
-; SI-NEXT: v_alignbit_b32 v14, v24, v28, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v21, v14, v54
-; SI-NEXT: v_or_b32_e32 v22, v6, v30
-; SI-NEXT: v_alignbit_b32 v6, v21, v30, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v19, v6, v55
-; SI-NEXT: v_or_b32_e32 v29, v1, v34
-; SI-NEXT: v_alignbit_b32 v1, v19, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v18, v13, v23
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v14, v13, v24
+; SI-NEXT: v_alignbit_b32 v13, v18, v24, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v13, v13, v25
+; SI-NEXT: v_or_b32_e32 v31, v15, v32
+; SI-NEXT: v_alignbit_b32 v15, v13, v32, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v33, v15, v29
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v24, v15, v37
+; SI-NEXT: v_alignbit_b32 v15, v33, v37, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v32, v15, v30
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v19
+; SI-NEXT: v_or_b32_e32 v37, v15, v39
+; SI-NEXT: v_alignbit_b32 v15, v32, v39, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v23, v1, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v20, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v23, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v30, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
-; SI-NEXT: v_or_b32_e32 v27, v1, v38
-; SI-NEXT: v_alignbit_b32 v1, v30, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v28, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v47
-; SI-NEXT: v_or_b32_e32 v34, v1, v45
-; SI-NEXT: v_alignbit_b32 v1, v28, v45, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v49
+; SI-NEXT: v_or_b32_e32 v38, v15, v35
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v15, v15, v51
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v63
-; SI-NEXT: v_or_b32_e32 v33, v1, v26
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v36, v1, v7
-; SI-NEXT: v_alignbit_b32 v1, v33, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v15, v38, v51, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v35, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v38, v1, v46
-; SI-NEXT: v_alignbit_b32 v1, v35, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v53
+; SI-NEXT: v_or_b32_e32 v39, v15, v48
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v15, v15, v55
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v37, v1, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v59
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v0
+; SI-NEXT: v_alignbit_b32 v15, v39, v55, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v49, v15, v50
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v15, v15, v43
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v49, v43, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v44
+; SI-NEXT: v_or_b32_e32 v51, v15, v52
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v27
+; SI-NEXT: v_or_b32_e32 v15, v15, v45
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v51, v45, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v47
+; SI-NEXT: v_or_b32_e32 v53, v15, v54
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v46
+; SI-NEXT: v_or_b32_e32 v15, v15, v57
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v53, v57, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v55, v15, v40
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v56
+; SI-NEXT: v_or_b32_e32 v15, v15, v60
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v55, v60, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v61
+; SI-NEXT: v_or_b32_e32 v41, v15, v42
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v59
+; SI-NEXT: v_or_b32_e32 v15, v15, v63
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v15, v41, v63, 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v21
+; SI-NEXT: v_or_b32_e32 v43, v15, v6
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v62
+; SI-NEXT: v_or_b32_e32 v15, v15, v7
+; SI-NEXT: v_alignbit_b32 v7, v43, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v45, v7, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v7, v7, v11
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v7, v45, v11, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v47, v7, v1
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v58, v7, v2
+; SI-NEXT: v_alignbit_b32 v2, v47, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v57, v2, v0
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v39, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v37, v3, 16
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v28
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v60, v2, v4
+; SI-NEXT: v_alignbit_b32 v2, v57, v4, 16
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr4
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; kill: killed $vgpr4
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: .LBB96_2: ; %Flow
-; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
-; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v46
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: s_movk_i32 s6, 0x300
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_or_b32_e32 v2, v58, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v37
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v5
+; SI-NEXT: v_or_b32_e32 v9, v13, v9
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v62
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x300, v9
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v13, v9
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v56
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v36
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v15
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v57, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v60, vcc, s7, v9
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v57
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v5, v13, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v59
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v22
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v1, v5, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v56, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_add_i32_e32 v47, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v58, vcc, s7, v0
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v47
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v26
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v35
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v27
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v45, vcc, s7, v3
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v45
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v63, v5
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
+; SI-NEXT: v_or_b32_e32 v5, v8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v20
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v5
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v33
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v5, v7, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v11
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v10
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v6
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v43
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v28
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v7
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v41, vcc, s7, v8
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v32
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v9
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v11
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v55, vcc, s7, v11
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v55
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v12
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v53, vcc, s7, v13
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v15
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v51
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v17
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v24
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v17
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v49
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v18
-; SI-NEXT: v_mov_b32_e32 v18, v5
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v19
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v39
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v25, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v26, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v26
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v20
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: v_or_b32_e32 v31, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v15
-; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v21
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v32, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v32
+; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v48, v20, v19
-; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v25
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v10
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
+; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v38
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v51
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v28
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v40, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v0, v11, v48, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v12, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v0, v9, v5, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v18, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v51, v15, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v13, v31, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v33, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v9, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v32, v37, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v38, v3, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v31, v3, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v39, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v49, v6, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v24, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v21, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v19, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v23, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v30, v27, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v28, v34, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v33, v36, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v35, v38, 16
-; SI-NEXT: v_alignbit_b32 v1, v8, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v51, v7, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v53, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v55, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v41, v25, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v43, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v45, v27, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v37, v39, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v47, v58, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v57, v60, 16
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v33
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
; SI-NEXT: .LBB96_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v45
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v61
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v40
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v48
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v31
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v13
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v24
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v51
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v37
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v49
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v54
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v42
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v44
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v31
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v50
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v24
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v22
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v29
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_or_b32_e32 v18, v18, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v53
-; SI-NEXT: v_or_b32_e32 v19, v19, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v53
+; SI-NEXT: v_or_b32_e32 v19, v19, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v30
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v34
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v43
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
+; SI-NEXT: v_and_b32_e32 v28, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v47
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff, v60
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v57
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
@@ -187463,20 +189103,6 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v36
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v38
-; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -188788,693 +190414,703 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:272
-; GFX9-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:288
-; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:296
-; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:304
-; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:320
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:156
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:152
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:140
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:132
-; GFX9-NEXT: s_waitcnt vmcnt(27)
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:4
+; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: s_waitcnt vmcnt(31)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(26)
-; GFX9-NEXT: v_lshlrev_b16_e32 v53, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(25)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(24)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(23)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v6
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:100
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
+; GFX9-NEXT: s_waitcnt vmcnt(31)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:384
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v7
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v9
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v10
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v11
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v13
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v14
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v15
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v16
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v17
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v18
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:328
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:352
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:324
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:332
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:348
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:344
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:360
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:384
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:356
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v1
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:364
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:116
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:260
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:380
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:340
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:372
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:248
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:380
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:376
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:372
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:200
-; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:368
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:200
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:196
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:344
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:376
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:168
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:332
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:328
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:324
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:156
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:320
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:152
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:316
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:148
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:312
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:144
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:308
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:140
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:304
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:300
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:132
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:284
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:124
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB96_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
-; GFX9-NEXT: v_or_b32_sdwa v9, v59, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v47, v45, s6
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v55, v54, s6
-; GFX9-NEXT: v_perm_b32 v17, v43, v42, s6
-; GFX9-NEXT: v_perm_b32 v18, v58, v57, s6
-; GFX9-NEXT: v_perm_b32 v19, v63, v46, s6
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v10, v62, v35, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v60
+; GFX9-NEXT: v_or_b32_sdwa v11, v63, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v59, v58, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v13, v44, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v43, v42, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v53
+; GFX9-NEXT: v_or_b32_sdwa v15, v52, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr35
+; GFX9-NEXT: ; implicit-def: $vgpr63
+; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr55
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr58
-; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr46
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: ; implicit-def: $vgpr52
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v33, s6
+; GFX9-NEXT: v_perm_b32 v8, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v60, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
+; GFX9-NEXT: v_or_b32_sdwa v8, v38, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v36, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v44, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v9, v61, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v41, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v32, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v52, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v57
+; GFX9-NEXT: v_or_b32_sdwa v11, v56, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr44
-; GFX9-NEXT: ; implicit-def: $vgpr41
-; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; kill: killed $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v12, v50, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v12, v46, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr50
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v37, v36, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v13, v40, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v55
+; GFX9-NEXT: v_or_b32_sdwa v14, v54, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v51, v50, s6
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr57
+; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr55
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_sdwa v15, v62, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v16, v17, v16, s6
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v35, s6
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
-; GFX9-NEXT: v_perm_b32 v16, v32, v56, s6
+; GFX9-NEXT: v_perm_b32 v17, v18, v17, s6
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s7
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v17, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr62
-; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s7
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s7
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v20, v20, v61, s6
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s7
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
-; GFX9-NEXT: ; kill: killed $vgpr61
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v21, v22, v21, s6
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v21, v21, v22, s6
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
; GFX9-NEXT: v_perm_b32 v21, v22, v21, s7
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s6
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_perm_b32 v22, v23, v22, s7
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s6
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v23, v23, v48, s6
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s7
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
+; GFX9-NEXT: ; kill: killed $vgpr48
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s7
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s6
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s7
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s7
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s6
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s7
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s7
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v29, 8, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s6
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s7
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v30, 8, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s7
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v32, v33, v32, s6
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s7
@@ -189543,80 +191179,94 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; kill: killed $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr33
-; GFX9-NEXT: ; kill: killed $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB96_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB96_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v33
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v45
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v11, v38, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
-; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v46
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v56
-; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v42
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v34
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v60
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v45
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v41
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v49
+; GFX9-NEXT: v_mov_b32_e32 v29, v48
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(20)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
+; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(19)
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: s_waitcnt vmcnt(18)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
+; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(12)
+; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(9)
+; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: s_waitcnt vmcnt(11)
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v9
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
+; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v26, 8, v26
+; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v27
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -189624,16 +191274,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v2
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v3
; GFX9-NEXT: v_perm_b32 v0, v2, v0, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
@@ -189642,312 +191292,330 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s6
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
-; GFX9-NEXT: v_add_u16_e32 v8, 3, v60
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v8, v53, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v9, v51, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v8, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v36
+; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s6
-; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
+; GFX9-NEXT: v_add_u16_e32 v9, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v10, v49, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v61
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v41
-; GFX9-NEXT: v_or_b32_sdwa v10, v39, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v63
+; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s6
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v55
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v52
-; GFX9-NEXT: v_or_b32_sdwa v12, v34, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v56
+; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s6
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v50
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v47
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v48
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v44
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s6
-; GFX9-NEXT: v_add_u16_e32 v13, 3, v37
-; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v36
+; GFX9-NEXT: v_add_u16_e32 v13, 3, v43
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v40
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s6
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v14, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v52
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v35
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v50
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v62
-; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
-; GFX9-NEXT: v_add_u16_e32 v16, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v57
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u16_e32 v16, 3, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v17, 3, v63
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v18, 3, v32
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 3, v43
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v16
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v18
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v19
; GFX9-NEXT: v_perm_b32 v16, v18, v16, s6
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v17, v17, v20, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v19
; GFX9-NEXT: v_perm_b32 v31, v32, v31, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v21
; GFX9-NEXT: v_perm_b32 v30, v33, v30, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v23
-; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v36, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v36
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v37, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v38, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v39, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v39
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v48, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v49, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v50, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v22
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v50
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: v_perm_b32 v29, v34, v29, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
+; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v51, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v51
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v52, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v53, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v53
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v54, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v55, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v55
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v40, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v61
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v50, 0x300, v40
; GFX9-NEXT: v_perm_b32 v21, v50, v21, s6
-; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v41, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v41
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v42, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v51, 0x300, v42
; GFX9-NEXT: v_perm_b32 v20, v51, v20, s6
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -189955,23 +191623,23 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v43, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v43
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v44, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28
; GFX9-NEXT: v_or_b32_sdwa v45, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v45
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
@@ -190021,742 +191689,754 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:488
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:484
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:384
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:368
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:360
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:352
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:328
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v96, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v118, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v132, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v151, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v164, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v85, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v166, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v113, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v112, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v129, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v117, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v145, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v178, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v161, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v87, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v37.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v115, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v49.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v144, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v15.h, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v167, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v182, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v42, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v160, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v46, v183, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v57, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v176, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v61, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v45, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v26.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.h, 8, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v44, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v56, v41, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v63, v59, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.h, 8, v52.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v58, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.l, v26.h
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v25.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v73, v62, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.h, v28.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v65.l
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v76, v74, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
-; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
-; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
-; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v29.l
+; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v31.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_and_b16 v30.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v69.h
+; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v31.l, v31.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v77, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v30.h, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v32.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: .LBB96_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v79.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v78.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v70.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v71.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v69.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v68.h, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v66.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v76.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v73.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v62.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v53.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v52.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v72.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v60.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v59.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v61.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v47.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v41.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v44.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v40.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v181.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v46.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v42.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v180.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v176.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v182.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v150.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v149.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v167.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v148.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v128.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v38.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v35.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v144.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v37.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v33.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v102.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v35.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v161.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v135.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v166.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v164.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v133.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v130.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v117.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v100.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v129.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v112.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v101.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v103.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -190769,32 +192449,31 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v32.h
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:392
-; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:396
-; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:400
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:404
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:408
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:412
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:416
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:420
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:424
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:428
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:432
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:436
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:440
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:444
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:448
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:452
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:456
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:460
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:464
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:468
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:472
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:476
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:480
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:484
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:488
+; GFX11-TRUE16-NEXT: s_clause 0x17 ; 96-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:392
+; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:396
+; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:400
+; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:404
+; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:408
+; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:412
+; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:416
+; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:420
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:424
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:428
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:432
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:436
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:440
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:444
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:448
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:452
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:456
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:460
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:464
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:468
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:472
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:476
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:480
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:484
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -190851,165 +192530,128 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v24 :: v_dual_mov_b32 v51, v19
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v71, v20
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v67, v17
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v65, v18
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v16 :: v_dual_mov_b32 v50, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v14 :: v_dual_mov_b32 v53, v9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:364
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:360
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:356
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:352
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v6, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:312
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:308
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:304
-; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:284
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:280
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:276
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:384
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:380
+; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:360
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:356
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:352
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:348
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:308
+; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:304
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:300
+; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:280
+; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:276
+; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:272
+; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:252
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:232
-; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:228
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:224
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:192
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:188
-; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:184
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:180
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:152
-; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:148
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:136
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:248
+; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:228
+; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:224
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:220
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:188
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:184
+; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:180
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:176
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:148
+; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:144
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_b32 v13, off, s32 offset:388
-; GFX11-FAKE16-NEXT: scratch_load_u16 v14, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v15, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v16, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v17, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v18, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v19, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v20, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v21, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v22, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v23, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v24, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v126, 8, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v125, 8, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v123, 8, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v122, 8, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v124, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v121, 8, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v120, 8, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v111, 8, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v110, 8, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v108, 8, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v109, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v107, 8, v12
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(28)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v182, 8, v14
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v166, 8, v15
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(26)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v180, 8, v16
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v46, 8, v17
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v47, 8, v18
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(23)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v56, 8, v19
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v75, 8, v20
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v59, 8, v21
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v74, 8, v22
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v95, 8, v23
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v90, 8, v24
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v30 :: v_dual_mov_b32 v85, v29
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, v28 :: v_dual_mov_b32 v81, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v27 :: v_dual_mov_b32 v83, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v71, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v23 :: v_dual_mov_b32 v65, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v21 :: v_dual_mov_b32 v69, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v17 :: v_dual_mov_b32 v52, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v15 :: v_dual_mov_b32 v64, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v13 :: v_dual_mov_b32 v32, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v33, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -191019,124 +192661,147 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v37, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v48, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v39, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v55, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v65, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v49, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v84, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v82, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v70, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v118
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v113
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v86, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v69, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v71, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v70, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v82, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v86, v85, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v84, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v102
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v99
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v7, v182
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v134
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v129
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v112, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v166
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v7, v46
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v47
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v132
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v151
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v145
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v150
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v75
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v162
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v130, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v14, v59
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v74
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v148, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v11, v95
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v90
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v116
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v107
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v103, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v131, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v102, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v147, v146, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v133, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v149, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v18, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v20, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v24, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v177, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v165, v161, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v183, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v179, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v43, v42, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v40, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v60, v57, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v44, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v72
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v21, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v27, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v58
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v109
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v73
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v63
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v24, v108
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v61, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v27, v111
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v120
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v110
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v91
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v103
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v113
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v147
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v129
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v117, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v14, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v119
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v162
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v150
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v145
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v165
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v151
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v131, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v163, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v161, v146, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v149, v144, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v177, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v17, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v180, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v176, v164, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v181, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v44, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v42, v183, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v57, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v47, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v72, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v59, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v78
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v75
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v73
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v88
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v94
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v105
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v27, v122
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v106
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v121
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v76, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v29, v124
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v123
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v89, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v27, v125
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v126
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v34, v127
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v104, v93, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v28, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v35, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v33, v36, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v34, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v76
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v60, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v58, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v23, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v79, v74, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v104
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v77
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v26, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v32, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v95
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v92
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v111
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v109
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v107
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v93
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v110
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v32, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v127
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v123
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v121
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v120
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xff, v126
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v124
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v94, v90, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v108, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v33, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v35, v36
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v38
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v125, v122, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v32, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v35, v36, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
@@ -191146,13 +192811,13 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
@@ -191161,346 +192826,364 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: .LBB96_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v104, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v105, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v93
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v94, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v125, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v126, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v122
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v124
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v127, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v92, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v121, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v123
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v120
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v127, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v89, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v125, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v126, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v108, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v89, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v77
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v91, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v88, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v76, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v62
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v123, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v124, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v78, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v122, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v108, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v105
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v110, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v105, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v107, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v94, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v93
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v90
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v95, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v90, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v104, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v92, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v91, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v89
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v79, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v77, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v88, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v74
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v76
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v78, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v74, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v75
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v73, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v73, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v121, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v62, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v62, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v61, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v72, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v61, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v63, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v120, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v111, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v45
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v63
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v45, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v110, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v58, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v60, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v42
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v58, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v109, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v60
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v58, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v72, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v61
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v59, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v46, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v56
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v57, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v56, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v47, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v57
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v43, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v108, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v43, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v42, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v41
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v183
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v40, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v183, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v181
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v183, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v181, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v179, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v182
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v181, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v180, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v178
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v176
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v176, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v165, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v176, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v177, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v164, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v161, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v164
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v167
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v166, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v164, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v160
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v149, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v147, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v160, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v149, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v144
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v146
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v144, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v165, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v148
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v146
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v133, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v151
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v162, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v146, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v131, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v131, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v118
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v134, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v147, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v119
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v128
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v117, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v118, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v102
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v102, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v98, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v129
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v117, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v128, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v115, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v96, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v167, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v107, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v162, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v148, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v95, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v150, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v135
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v151, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v90, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v116
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v113, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v145, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v101
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v100, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v74, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v75, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v130, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v103, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v132, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v59, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v129, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v114, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v98, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v56, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v99, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v86, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v112, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v46, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v47, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v101
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v113, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v101, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v180, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v182, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v85
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v166, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v96
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v85
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v84, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v84, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v84, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v83, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
@@ -191528,28 +193211,28 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v64, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v54
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v53
; GFX11-FAKE16-NEXT: v_add_nc_u16 v52, v52, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v66, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v51, 8, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v50, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v49
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v52
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v55, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v51, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v49, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v50, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v51, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v50, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v49, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v39, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v38, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v37, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v53, 8, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xff, v39
@@ -191581,30 +193264,30 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v68, v67, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v84, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v83, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v100, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v98, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v97, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v102, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v117, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v147, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v161, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v176, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v181, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v40, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v58, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v45, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v61, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v73, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v62, v29, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v77, v30, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v89, v31, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v84, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v98, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v112, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v117, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v131, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v144, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v160, v18, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v164, v19, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v180, v20, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v183, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v43, v22, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v56, v23, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v46, v24, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v62, v25, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v74, v26, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v77, v27, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v92, v28, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v90, v29, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v105, v30, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v108, v31, 0x5040100
; GFX11-FAKE16-NEXT: .LBB96_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -196226,185 +197909,248 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
-; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v29
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v4
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v28
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v26
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v25
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v24
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v10
-; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v22
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v21
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v20
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v19
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v17
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v16
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v14
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v13
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v12
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v10
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v9
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v12
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v58
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v14
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v57
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v16
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v56
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v18
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v47
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v20
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v46
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v22
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v45
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v24
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v44
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v43
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v28
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v42
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v30
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v41
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v40
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr38
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v7
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v6
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v5
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; kill: killed $vgpr53
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v4
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v60
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v2
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v58
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v51
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
@@ -196420,656 +198166,515 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr31
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; kill: killed $vgpr49
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v41, v1, v31
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_or_b32_e32 v44, v1, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v60
; SI-NEXT: v_or_b32_e32 v47, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v44, v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v54, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v56
+; SI-NEXT: v_or_b32_e32 v41, v1, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v48, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v37, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v45
+; SI-NEXT: v_or_b32_e32 v49, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v35, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v38, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v34, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v42
+; SI-NEXT: v_or_b32_e32 v39, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v33, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v36, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v32, v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v37, v1, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v31, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v34, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v63, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v53
+; SI-NEXT: v_or_b32_e32 v35, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v62, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v32, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v61, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; SI-NEXT: v_or_b32_e32 v33, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v59, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v63, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v58, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v31, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v57, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v61, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v56, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; SI-NEXT: v_or_b32_e32 v62, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v46, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v19, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v45, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_or_b32_e32 v59, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v42, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v43, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v18, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v57, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v55, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v17, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v40, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; SI-NEXT: v_or_b32_e32 v46, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v53, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v16, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v54, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; SI-NEXT: v_or_b32_e32 v43, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v50, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v15, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v51, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
+; SI-NEXT: v_or_b32_e32 v40, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v29
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v3, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v14, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v48, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v52, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v2, v1, v2
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
-; SI-NEXT: v_or_b32_e32 v38, v1, v4
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 8
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v13, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; SI-NEXT: v_or_b32_e32 v50, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 16
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 8
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 16
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 16
+; SI-NEXT: v_alignbit_b32 v1, v59, v19, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v59, v19, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v59, v19, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 24
+; SI-NEXT: v_alignbit_b32 v1, v57, v18, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
+; SI-NEXT: v_alignbit_b32 v1, v57, v18, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v57, v18, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v43, v42, 24
+; SI-NEXT: v_alignbit_b32 v1, v46, v17, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v46, v17, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v43, v42, 16
+; SI-NEXT: v_alignbit_b32 v1, v46, v17, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v43, v42, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v40, v55, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v40, v55, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v40, v55, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 16
+; SI-NEXT: v_alignbit_b32 v1, v43, v16, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 8
+; SI-NEXT: v_alignbit_b32 v1, v43, v16, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v43, v16, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v40, v15, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 8
+; SI-NEXT: v_alignbit_b32 v1, v40, v15, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v48, v3, 24
+; SI-NEXT: v_alignbit_b32 v1, v40, v15, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v52, v14, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v48, v3, 16
+; SI-NEXT: v_alignbit_b32 v1, v52, v14, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v48, v3, 8
+; SI-NEXT: v_alignbit_b32 v1, v52, v14, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v38, v2, 24
+; SI-NEXT: v_alignbit_b32 v1, v50, v13, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v38, v2, 16
+; SI-NEXT: v_alignbit_b32 v1, v50, v13, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v38, v2, 8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v50, v13, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v36
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v47
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v44
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v41
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v49
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v34
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v39
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v32
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v35
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v58
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v56
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v62
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v45
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v59
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v43
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v40
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v54
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v51
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v40
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v48
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v52
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v50
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v60, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v56, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v45, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v42, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v55, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v53, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v12, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v11, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v10, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v8, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v6, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
+; SI-NEXT: v_bfe_u32 v1, v7, 8, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: v_bfe_u32 v1, v5, 8, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_bfe_u32 v1, v4, 8, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_bfe_u32 v1, v3, 8, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v1, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_bfe_u32 v1, v9, 8, 8
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v60, v19
+; SI-NEXT: v_mov_b32_e32 v56, v18
+; SI-NEXT: v_mov_b32_e32 v45, v17
+; SI-NEXT: v_mov_b32_e32 v42, v16
+; SI-NEXT: v_mov_b32_e32 v55, v15
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; kill: killed $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: .LBB98_2: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v39
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -197087,6 +198692,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
@@ -197097,464 +198704,493 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_or_b32_e32 v31, v32, v31
-; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v32, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v32, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_or_b32_e32 v32, v33, v32
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v31
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v32
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v31
+; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_or_b32_e32 v29, v33, v29
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v30, v33, v30
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v30, v27
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_or_b32_e32 v30, v33, v30
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v27
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_or_b32_e32 v23, v25, v23
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v23
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v21, v23, v21
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v19
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v19
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v15, v17, v15
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v13
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v9, v11, v9
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v1
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v1
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v47, v44, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v44, v47, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v41, v54, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v37, v52, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v49, v48, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v34, v35, 8
+; SI-NEXT: v_alignbit_b32 v1, v39, v38, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 16
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v32, v33, 8
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v37, v36, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v63, v31, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v35, v34, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v33, v32, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 16
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v62, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v31, v63, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v58, v59, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v62, v61, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 16
+; SI-NEXT: v_alignbit_b32 v1, v59, v60, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v56, v57, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v59, v60, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v59, v60, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 24
+; SI-NEXT: v_alignbit_b32 v1, v57, v56, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
+; SI-NEXT: v_alignbit_b32 v1, v57, v56, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v57, v56, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v43, v42, 24
+; SI-NEXT: v_alignbit_b32 v1, v46, v45, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v46, v45, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v43, v42, 16
+; SI-NEXT: v_alignbit_b32 v1, v46, v45, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v43, v42, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v43, v42, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v43, v42, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v40, v55, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v40, v55, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v40, v55, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v54, v53, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v50, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v48, v29, 24
+; SI-NEXT: v_alignbit_b32 v1, v52, v51, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v48, v29, 16
+; SI-NEXT: v_alignbit_b32 v1, v52, v51, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v48, v29, 8
+; SI-NEXT: v_alignbit_b32 v1, v52, v51, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v38, v39, 24
+; SI-NEXT: v_alignbit_b32 v1, v50, v53, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v38, v39, 16
+; SI-NEXT: v_alignbit_b32 v1, v50, v53, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v38, v39, 8
+; SI-NEXT: v_alignbit_b32 v1, v50, v53, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v36
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v47
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v47
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v36
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v47
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v44
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v41
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v41
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v44
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v41
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v37
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v49
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v49
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v49
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v34
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v39
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v39
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v34
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v39
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v32
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v37
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v37
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v32
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v35
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v35
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v63
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v35
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v61
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v33
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v61
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v58
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v31
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v31
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v58
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v56
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v62
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v62
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v56
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v62
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v45
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v59
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v45
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v59
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v45
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v59
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v43
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v57
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v57
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v43
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v40
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v46
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v46
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v40
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v54
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v43
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v54
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v43
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v51
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v40
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v51
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v40
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v48
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v52
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v48
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v50
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v52
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v50
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v41
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v44
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197566,7 +199202,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v47
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197582,14 +199218,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v47
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v54
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197602,7 +199238,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v44
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v41
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197618,14 +199254,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v48
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197638,7 +199274,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v37
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v49
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197656,12 +199292,12 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v35
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197674,7 +199310,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v39
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197692,12 +199328,12 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197710,7 +199346,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v37
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197726,14 +199362,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197746,7 +199382,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v63
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v35
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197762,14 +199398,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v62
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197782,7 +199418,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v61
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197798,14 +199434,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v59
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v63
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197818,7 +199454,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197834,14 +199470,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v61
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197854,7 +199490,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v56
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v62
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197870,14 +199506,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v46
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v60
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197890,12 +199526,12 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v45
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v59
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197906,14 +199542,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v42
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v56
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197926,12 +199562,12 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197942,14 +199578,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v55
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v45
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197960,9 +199596,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v46
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
@@ -197978,14 +199614,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v53
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v42
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -197996,10 +199632,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v54
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v43
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -198014,14 +199650,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v55
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -198032,10 +199668,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v51
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v40
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -198051,7 +199687,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
@@ -198070,26 +199706,24 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v48
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v53
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
@@ -198108,15 +199742,15 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v50
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -198148,30 +199782,64 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-LABEL: bitcast_v64i16_to_v128i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8
-; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:4
-; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v30
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v29
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v26
+; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr53
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
@@ -198188,66 +199856,73 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v63, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
-; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v62, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v28
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v27
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v25
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v23
-; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v22
-; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v21
-; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v20
-; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v18
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; kill: killed $vgpr39
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr44
+; VI-NEXT: ; implicit-def: $vgpr43
+; VI-NEXT: ; implicit-def: $vgpr42
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: ; implicit-def: $vgpr57
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr59
+; VI-NEXT: ; implicit-def: $vgpr45
+; VI-NEXT: ; implicit-def: $vgpr49
+; VI-NEXT: ; implicit-def: $vgpr47
+; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr55
+; VI-NEXT: ; implicit-def: $vgpr62
+; VI-NEXT: ; implicit-def: $vgpr58
+; VI-NEXT: ; implicit-def: $vgpr51
+; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: ; implicit-def: $vgpr46
+; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; kill: killed $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr50
+; VI-NEXT: ; implicit-def: $vgpr60
+; VI-NEXT: ; implicit-def: $vgpr34
+; VI-NEXT: ; implicit-def: $vgpr61
+; VI-NEXT: ; kill: killed $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr63
+; VI-NEXT: ; implicit-def: $vgpr41
+; VI-NEXT: ; implicit-def: $vgpr54
+; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v19
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v36
-; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v37
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
@@ -198298,19 +199973,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
@@ -198319,7 +199989,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
@@ -198328,7 +199997,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
@@ -198369,82 +200037,51 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: ; kill: killed $vgpr31
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; kill: killed $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr39
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr39
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr39
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr39
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr44
-; VI-NEXT: ; implicit-def: $vgpr43
-; VI-NEXT: ; implicit-def: $vgpr42
-; VI-NEXT: ; implicit-def: $vgpr39
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB98_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v16
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v16
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v16
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v15
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v14
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v13
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v13
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v12
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v12
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v12
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v11
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v11
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v10
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v10
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v10
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v9
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v9
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v8
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v8
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v7
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v6
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v6
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[15:16]
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
@@ -198452,153 +200089,195 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[11:12]
+; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[1:2]
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[9:10]
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v31, v7
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v10
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v11
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v12
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v13
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v14
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v15
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v9, v16
+; VI-NEXT: v_lshrrev_b64 v[42:43], 24, v[21:22]
+; VI-NEXT: v_mov_b32_e32 v31, v9
+; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[19:20]
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v12
+; VI-NEXT: v_lshrrev_b64 v[44:45], 24, v[17:18]
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v13
+; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v14
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v15
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v16
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v11, v10
+; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[9:10]
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 24, v8
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v9, v7
+; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v8
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v9, v8
; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[7:8]
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v6
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v6
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v5
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v7, v6
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 24, v4
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v5, v3
-; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
+; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[3:4]
; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v2
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v3, v1
-; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v37
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v36
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v36
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v35
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v35
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v1, v35
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v36
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v1, v37
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v2
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v3, v2
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[36:37]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[35:36]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v30
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v30
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v29
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v29
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v29
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v30
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[29:30]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v28
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v27
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v27
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v27
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v28
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[27:28]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 24, v26
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v26
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v25
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v26
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[25:26]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v24
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v23
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v23
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v24
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v21
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v21
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v21
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v22
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v20
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v19
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v19
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v20
-; VI-NEXT: v_lshrrev_b64 v[42:43], 24, v[21:22]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, v17
-; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[19:20]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v1, v18
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v5, v4
; VI-NEXT: v_lshrrev_b64 v[39:40], 24, v[23:24]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v1, v45
-; VI-NEXT: v_lshrrev_b64 v[44:45], 24, v[17:18]
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v24
-; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v22
-; VI-NEXT: v_lshrrev_b32_e32 v49, 24, v20
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v19
-; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v18
-; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v18
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v17
-; VI-NEXT: v_mov_b32_e32 v45, v1
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v1, v18
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v4
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v63, 16, v36
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v30
+; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v28
+; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v28
+; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v26
+; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v26
+; VI-NEXT: v_lshrrev_b32_e32 v50, 24, v24
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v24
+; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v22
+; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v22
+; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v22
+; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v21
+; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v20
+; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v20
+; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v20
+; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v19
+; VI-NEXT: v_lshrrev_b32_e32 v55, 24, v18
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v18
+; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v18
+; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v17
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
@@ -198614,322 +200293,318 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr29
-; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: .LBB98_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB98_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v31, 3
-; VI-NEXT: v_add_u16_sdwa v55, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v37, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v32, 3, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v55
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v18, v32, v18
; VI-NEXT: v_add_u16_e32 v32, 3, v17
; VI-NEXT: v_add_u16_sdwa v17, v17, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_add_u16_sdwa v54, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v58, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v17, v32, v17
; VI-NEXT: v_add_u16_e32 v32, 3, v20
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v54
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v58
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v20, v32, v20
; VI-NEXT: v_add_u16_e32 v32, 3, v19
; VI-NEXT: v_add_u16_sdwa v19, v19, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_add_u16_sdwa v57, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v46, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v19, v32, v19
; VI-NEXT: v_add_u16_e32 v32, 3, v22
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v57
-; VI-NEXT: v_add_u16_sdwa v52, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v46
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v22, v32, v22
; VI-NEXT: v_add_u16_e32 v32, 3, v21
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v52
-; VI-NEXT: v_add_u16_sdwa v56, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v21, v32, v21
-; VI-NEXT: v_add_u16_e32 v32, 3, v24
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
-; VI-NEXT: v_add_u16_sdwa v50, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v24, v32, v24
-; VI-NEXT: v_add_u16_e32 v32, 3, v23
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v50
-; VI-NEXT: v_add_u16_sdwa v49, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v23, v32, v23
-; VI-NEXT: v_add_u16_e32 v32, 3, v26
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v49
-; VI-NEXT: v_add_u16_sdwa v59, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v26, v32, v26
-; VI-NEXT: v_add_u16_e32 v32, 3, v25
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v59
-; VI-NEXT: v_add_u16_sdwa v38, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v21, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v25, v32, v25
-; VI-NEXT: v_add_u16_e32 v32, 3, v28
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v38
-; VI-NEXT: v_add_u16_sdwa v35, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v28, v32, v28
-; VI-NEXT: v_add_u16_e32 v32, 3, v27
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v35
-; VI-NEXT: v_add_u16_sdwa v48, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v27, v32, v27
-; VI-NEXT: v_add_u16_e32 v32, 3, v30
-; VI-NEXT: v_add_u16_e32 v33, 3, v29
-; VI-NEXT: v_add_u16_sdwa v34, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
-; VI-NEXT: v_or_b32_e32 v30, v32, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v34
-; VI-NEXT: v_add_u16_sdwa v53, v37, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v29, v33, v29
-; VI-NEXT: v_add_u16_e32 v34, 3, v37
-; VI-NEXT: v_add_u16_sdwa v33, v36, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
-; VI-NEXT: v_add_u16_e32 v39, 3, v36
-; VI-NEXT: v_or_b32_e32 v37, v34, v32
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v33
-; VI-NEXT: v_add_u16_sdwa v47, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v21, v32, v21
+; VI-NEXT: v_add_u16_sdwa v32, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v33, 3, v24
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v24, v33, v24
+; VI-NEXT: v_add_u16_e32 v33, 3, v23
+; VI-NEXT: v_add_u16_sdwa v23, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_add_u16_sdwa v60, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v23, v33, v23
+; VI-NEXT: v_add_u16_e32 v33, 3, v26
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v60
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v26, v33, v26
+; VI-NEXT: v_add_u16_e32 v33, 3, v25
+; VI-NEXT: v_add_u16_sdwa v25, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_add_u16_sdwa v61, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v25, v33, v25
+; VI-NEXT: v_add_u16_e32 v33, 3, v28
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v61
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v28, v33, v28
+; VI-NEXT: v_add_u16_e32 v33, 3, v27
+; VI-NEXT: v_add_u16_sdwa v27, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v27, v33, v27
+; VI-NEXT: v_add_u16_sdwa v33, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v34, 3, v30
+; VI-NEXT: v_add_u16_e32 v38, 3, v29
+; VI-NEXT: v_add_u16_sdwa v39, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v33
+; VI-NEXT: v_or_b32_e32 v30, v34, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v39
+; VI-NEXT: v_add_u16_sdwa v63, v36, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v29, v38, v29
+; VI-NEXT: v_add_u16_e32 v38, 3, v36
+; VI-NEXT: v_add_u16_e32 v39, 3, v35
+; VI-NEXT: v_add_u16_sdwa v35, v35, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v63
+; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v36, v38, v34
+; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v35
+; VI-NEXT: v_add_u16_sdwa v38, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v35, v39, v34
+; VI-NEXT: v_add_u16_e32 v34, 3, v2
+; VI-NEXT: v_add_u16_e32 v39, 3, v1
+; VI-NEXT: v_add_u16_sdwa v48, v1, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v38
+; VI-NEXT: v_or_b32_e32 v2, v34, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v48
+; VI-NEXT: v_add_u16_sdwa v57, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v1, v39, v1
+; VI-NEXT: v_add_u16_e32 v34, 3, v4
+; VI-NEXT: v_add_u16_e32 v39, 3, v3
+; VI-NEXT: v_add_u16_sdwa v48, v3, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; VI-NEXT: v_or_b32_e32 v4, v34, v3
+; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; VI-NEXT: v_add_u16_sdwa v48, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v36, v39, v32
-; VI-NEXT: v_add_u16_e32 v33, 3, v2
-; VI-NEXT: v_add_u16_e32 v34, 3, v1
-; VI-NEXT: v_add_u16_sdwa v32, v1, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v47
-; VI-NEXT: v_or_b32_e32 v2, v33, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
-; VI-NEXT: v_add_u16_sdwa v46, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v1, v34, v1
-; VI-NEXT: v_add_u16_e32 v33, 3, v4
-; VI-NEXT: v_add_u16_e32 v34, 3, v3
-; VI-NEXT: v_add_u16_sdwa v32, v3, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
-; VI-NEXT: v_or_b32_e32 v4, v33, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v3, v34, v3
-; VI-NEXT: v_add_u16_sdwa v34, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: v_add_u16_e32 v33, 3, v6
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v3, v39, v3
+; VI-NEXT: v_add_u16_e32 v34, 3, v6
; VI-NEXT: v_add_u16_e32 v39, 3, v5
-; VI-NEXT: v_add_u16_sdwa v32, v5, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v34
-; VI-NEXT: v_or_b32_e32 v6, v33, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
-; VI-NEXT: v_add_u16_sdwa v62, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v49, v5, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; VI-NEXT: v_or_b32_e32 v6, v34, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v49
+; VI-NEXT: v_add_u16_sdwa v59, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v5, v39, v5
-; VI-NEXT: v_add_u16_e32 v39, 3, v8
-; VI-NEXT: v_add_u16_e32 v33, 3, v7
-; VI-NEXT: v_add_u16_sdwa v32, v7, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v62
-; VI-NEXT: v_or_b32_e32 v8, v39, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
-; VI-NEXT: v_add_u16_sdwa v61, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v7, v33, v7
-; VI-NEXT: v_add_u16_e32 v33, 3, v10
+; VI-NEXT: v_add_u16_e32 v34, 3, v8
+; VI-NEXT: v_add_u16_e32 v39, 3, v7
+; VI-NEXT: v_add_u16_sdwa v49, v7, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; VI-NEXT: v_or_b32_e32 v8, v34, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v49
+; VI-NEXT: v_add_u16_sdwa v56, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v7, v39, v7
+; VI-NEXT: v_add_u16_e32 v49, 3, v10
; VI-NEXT: v_add_u16_e32 v39, 3, v9
-; VI-NEXT: v_add_u16_sdwa v32, v9, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v61
-; VI-NEXT: v_or_b32_e32 v10, v33, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v32
-; VI-NEXT: v_add_u16_sdwa v60, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v34, v9, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v56
+; VI-NEXT: v_or_b32_e32 v10, v49, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; VI-NEXT: v_add_u16_sdwa v51, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v9, v39, v9
-; VI-NEXT: v_add_u16_e32 v33, 3, v12
-; VI-NEXT: v_add_u16_e32 v39, 3, v11
-; VI-NEXT: v_add_u16_sdwa v32, v11, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v60
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v12, v33, v11
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
-; VI-NEXT: v_add_u16_sdwa v33, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v11, v39, v11
+; VI-NEXT: v_add_u16_e32 v39, 3, v12
+; VI-NEXT: v_add_u16_e32 v49, 3, v11
+; VI-NEXT: v_add_u16_sdwa v34, v11, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v51
+; VI-NEXT: v_or_b32_e32 v12, v39, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v34
+; VI-NEXT: v_add_u16_sdwa v50, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v11, v49, v11
; VI-NEXT: v_add_u16_e32 v39, 3, v14
-; VI-NEXT: v_add_u16_e32 v40, 3, v13
-; VI-NEXT: v_add_u16_sdwa v32, v13, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v33
-; VI-NEXT: v_add_u16_sdwa v63, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v49, 3, v13
+; VI-NEXT: v_add_u16_sdwa v34, v13, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v50
; VI-NEXT: v_or_b32_e32 v14, v39, v13
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v32
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v34
+; VI-NEXT: v_add_u16_sdwa v34, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; VI-NEXT: v_add_u16_sdwa v31, v15, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v16, 3, v16
-; VI-NEXT: v_add_u16_e32 v32, 3, v15
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v63
-; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_e32 v39, 3, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v16, v16, v15
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v31
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v15, v32, v15
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v15, v39, v15
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v16
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v15
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[15:16]
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v13, v40, v13
+; VI-NEXT: v_or_b32_e32 v13, v49, v13
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v14
-; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v13
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[13:14]
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v11
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v10
-; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v9
; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[9:10]
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v7
; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[7:8]
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v6
-; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v5
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
-; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
+; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[3:4]
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v37
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v36
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[36:37]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v35
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[35:36]
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v30
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v29
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[29:30]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v27
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[27:28]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v26
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[25:26]
+; VI-NEXT: v_lshrrev_b64 v[42:43], 24, v[21:22]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[19:20]
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v24
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v23
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: v_lshrrev_b64 v[44:45], 24, v[17:18]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v21
+; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v23
+; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v20
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v63, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v33, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v60, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v61, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v62, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v34, 8, 8
-; VI-NEXT: v_lshrrev_b64 v[42:43], 24, v[21:22]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v46, 8, 8
-; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[19:20]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v47, 8, 8
-; VI-NEXT: v_lshrrev_b64 v[44:45], 24, v[17:18]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v53, 8, 8
-; VI-NEXT: v_mov_b32_e32 v45, v38
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v48, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; VI-NEXT: v_bfe_u32 v1, v45, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v49, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v50, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v51, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v56, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v59, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v48, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v57, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v38, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v63, 8, 8
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[39:40], 24, v[23:24]
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v1, v57
-; VI-NEXT: v_mov_b32_e32 v57, v55
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v19
-; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v18
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v17
-; VI-NEXT: v_bfe_u32 v56, v56, 8, 8
-; VI-NEXT: v_mov_b32_e32 v51, v1
-; VI-NEXT: v_bfe_u32 v38, v1, 8, 8
-; VI-NEXT: v_mov_b32_e32 v55, v54
-; VI-NEXT: v_bfe_u32 v49, v54, 8, 8
-; VI-NEXT: v_bfe_u32 v48, v57, 8, 8
-; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v33, 8, 8
+; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v28
+; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v22
+; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v21
+; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v20
+; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v19
+; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v18
+; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v17
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v61, 8, 8
+; VI-NEXT: v_bfe_u32 v34, v60, 8, 8
+; VI-NEXT: v_bfe_u32 v50, v32, 8, 8
+; VI-NEXT: v_bfe_u32 v56, v46, 8, 8
+; VI-NEXT: v_bfe_u32 v51, v58, 8, 8
+; VI-NEXT: v_bfe_u32 v55, v37, 8, 8
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
; VI-NEXT: .LBB98_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v1, v41, s4
@@ -198938,310 +200613,310 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v47, v2, s4
+; VI-NEXT: v_perm_b32 v2, v38, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v1, v31, s4
+; VI-NEXT: v_perm_b32 v1, v1, v54, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v46, v2, s4
+; VI-NEXT: v_perm_b32 v2, v57, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v1, v2, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v34, v2, s4
+; VI-NEXT: v_perm_b32 v2, v48, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v1, v2, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v62, v2, s4
+; VI-NEXT: v_perm_b32 v2, v59, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v61, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v60, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v33, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v63, v2, s4
+; VI-NEXT: v_perm_b32 v2, v45, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v44, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v2, v58, s4
+; VI-NEXT: v_perm_b32 v2, v2, v49, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v57, v48, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v37, v55, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v40, s4
+; VI-NEXT: v_perm_b32 v1, v1, v47, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v2, v32, s4
+; VI-NEXT: v_perm_b32 v2, v2, v62, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: v_perm_b32 v2, v55, v49, s4
+; VI-NEXT: v_perm_b32 v2, v58, v51, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v1, v31, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v1, v53, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: v_perm_b32 v2, v52, v42, s4
+; VI-NEXT: v_perm_b32 v2, v2, v42, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: v_perm_b32 v2, v51, v38, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v46, v56, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v1, v40, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: v_perm_b32 v2, v50, v39, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v39, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v2, v56, s4
+; VI-NEXT: v_perm_b32 v2, v32, v50, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v59, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
+; VI-NEXT: v_perm_b32 v2, v60, v34, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v35, v2, s4
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v1, v52, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v45, v2, s4
+; VI-NEXT: v_perm_b32 v2, v61, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
@@ -199250,39 +200925,38 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
+; VI-NEXT: v_perm_b32 v2, v33, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v53, v2, s4
+; VI-NEXT: v_perm_b32 v2, v63, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -205805,586 +207479,576 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v64bf16_to_v64f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:4
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v30
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v29
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v3
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v23
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v8
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v16
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v19
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v9
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v36
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v43
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v31
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v62
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v59
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v46
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v32
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v63
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v61
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v60
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v58
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v47
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v44
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v41
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr4
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; kill: killed $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; kill: killed $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; kill: killed $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; kill: killed $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; kill: killed $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; kill: killed $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; kill: killed $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; kill: killed $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; kill: killed $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; kill: killed $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; kill: killed $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; kill: killed $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB100_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v30
-; SI-NEXT: v_alignbit_b32 v2, v2, v45, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v28
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
-; SI-NEXT: v_alignbit_b32 v2, v2, v43, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
-; SI-NEXT: v_alignbit_b32 v1, v1, v40, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_alignbit_b32 v1, v1, v54, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v18
-; SI-NEXT: v_alignbit_b32 v1, v1, v11, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; SI-NEXT: v_alignbit_b32 v1, v1, v50, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v23
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; SI-NEXT: v_alignbit_b32 v1, v1, v48, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
-; SI-NEXT: v_alignbit_b32 v1, v1, v19, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v11
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v25
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13
-; SI-NEXT: v_alignbit_b32 v1, v1, v17, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v31
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v62
-; SI-NEXT: v_alignbit_b32 v1, v1, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v17
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v51
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v59
-; SI-NEXT: v_alignbit_b32 v1, v1, v15, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v38
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v57
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v6, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v0, v6, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v23
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v4, v63, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v0, v4, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v61, v60, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v0, v61, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v58, v56, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v0, v58, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v29
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v47, v46, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v0, v47, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v44, v42, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v20
-; SI-NEXT: v_alignbit_b32 v0, v44, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v13, v2, v4, 16
+; SI-NEXT: v_alignbit_b32 v38, v13, v0, 16
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v41, v55, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v0, v41, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
+; SI-NEXT: v_alignbit_b32 v9, v4, v5, 16
+; SI-NEXT: v_alignbit_b32 v0, v9, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v53, v52, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v16
-; SI-NEXT: v_alignbit_b32 v0, v53, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v5, v6, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: v_alignbit_b32 v0, v5, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v8, v7, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v8, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v51, v49, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v0, v51, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v28, v10, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v28, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v24, v12, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v24, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v22, v14, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_alignbit_b32 v19, v22, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v39, v38, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v0, v39, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v18, v16, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; SI-NEXT: v_alignbit_b32 v37, v18, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v37, v21, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v0, v37, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v63, v62, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
+; SI-NEXT: v_alignbit_b32 v39, v63, v1, 16
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v36, v23, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
-; SI-NEXT: v_alignbit_b32 v0, v36, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_alignbit_b32 v61, v60, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_alignbit_b32 v49, v61, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v35, v25, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v13
-; SI-NEXT: v_alignbit_b32 v0, v35, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v59, v58, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; SI-NEXT: v_alignbit_b32 v50, v59, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v34, v27, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v62
-; SI-NEXT: v_alignbit_b32 v0, v34, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v57, v56, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; SI-NEXT: v_alignbit_b32 v53, v57, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v33, v29, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v59
-; SI-NEXT: v_alignbit_b32 v0, v33, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v47, v46, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26
+; SI-NEXT: v_alignbit_b32 v54, v47, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; kill: killed $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; kill: killed $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v32, v31, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
-; SI-NEXT: v_alignbit_b32 v0, v32, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v45, v44, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; SI-NEXT: v_alignbit_b32 v55, v45, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v43, v42, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; SI-NEXT: v_alignbit_b32 v29, v43, v1, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
@@ -206430,539 +208094,595 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_alignbit_b32 v41, v40, v1, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_alignbit_b32 v32, v41, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_mov_b32_e32 v0, v38
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: .LBB100_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB100_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v30
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v30
-; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; SI-NEXT: v_alignbit_b32 v4, v6, v4, 16
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v43
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v40
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v6
-; SI-NEXT: v_alignbit_b32 v7, v21, v7, 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v7
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v18
-; SI-NEXT: v_alignbit_b32 v11, v20, v11, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; SI-NEXT: v_alignbit_b32 v11, v20, v11, 16
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v14
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
-; SI-NEXT: v_alignbit_b32 v3, v14, v3, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v48
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; SI-NEXT: v_alignbit_b32 v3, v14, v3, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v19
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v10
-; SI-NEXT: v_alignbit_b32 v3, v14, v3, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v51
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
-; SI-NEXT: v_alignbit_b32 v3, v9, v3, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v38
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v9
-; SI-NEXT: v_alignbit_b32 v3, v13, v3, 16
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v62
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; SI-NEXT: v_alignbit_b32 v3, v13, v3, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v59
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_alignbit_b32 v3, v14, v3, 16
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v57
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v14, v0, 16
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v12
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v10
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_alignbit_b32 v32, v31, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v0, v32, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; SI-NEXT: v_alignbit_b32 v33, v29, v3, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v34, v27, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v35, v25, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v36, v23, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v37, v21, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v39, v38, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v13
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v14
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v51, v49, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v16
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v14
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_alignbit_b32 v53, v52, v13, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_alignbit_b32 v9, v11, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; SI-NEXT: v_alignbit_b32 v9, v17, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v44, v42, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v17
+; SI-NEXT: v_alignbit_b32 v41, v40, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v32, v41, v11, 16
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v17
+; SI-NEXT: v_alignbit_b32 v43, v42, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v47, v46, v15, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v17
+; SI-NEXT: v_alignbit_b32 v45, v44, v9, 16
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v55, v45, v17, 16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v16
+; SI-NEXT: v_alignbit_b32 v47, v46, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v54, v47, v20, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_alignbit_b32 v57, v56, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v53, v57, v21, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_alignbit_b32 v59, v58, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v50, v59, v23, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_alignbit_b32 v61, v60, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v49, v61, v25, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_alignbit_b32 v63, v62, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_alignbit_b32 v39, v63, v26, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v9
+; SI-NEXT: v_alignbit_b32 v18, v16, v8, 16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_alignbit_b32 v37, v18, v27, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
+; SI-NEXT: v_alignbit_b32 v22, v14, v7, 16
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v58, v56, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v58, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v47, v15, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v44, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_alignbit_b32 v19, v22, v19, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
+; SI-NEXT: v_alignbit_b32 v24, v12, v6, 16
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_alignbit_b32 v61, v60, v6, 16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_alignbit_b32 v41, v55, v14, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v18
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v41, v14, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v53, v13, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v51, v11, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v39, v12, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v37, v10, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v36, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; SI-NEXT: v_alignbit_b32 v28, v10, v5, 16
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_alignbit_b32 v8, v7, v4, 16
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; SI-NEXT: v_alignbit_b32 v5, v6, v4, 16
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_alignbit_b32 v9, v4, v2, 16
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v9, v1, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v35, v9, 16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v5, v31, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v34, v5, 16
-; SI-NEXT: v_alignbit_b32 v16, v61, v16, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v8, v3, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v3, 16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v28, v30, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v6
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_alignbit_b32 v4, v63, v4, 16
-; SI-NEXT: v_alignbit_b32 v17, v4, v17, 16
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v24, v29, 16
+; SI-NEXT: v_alignbit_b32 v29, v43, v15, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v6, v2, v6, 16
-; SI-NEXT: v_alignbit_b32 v18, v6, v18, 16
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v13, v2, v13, 16
+; SI-NEXT: v_alignbit_b32 v0, v13, v0, 16
; SI-NEXT: .LBB100_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v46
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v60
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v54
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v46
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v55
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_and_b32_e32 v32, 0xffff, v32
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v31, v32, v31
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v40
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v49
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v58
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v6, v6, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v47
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v44
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v58
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v53
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v62
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v51
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v63
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v39
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v61
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v59
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v22, v22, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v36
-; SI-NEXT: v_or_b32_e32 v23, v24, v23
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v57
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v24, v26
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v25, v26, v25
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v47
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v26, v26, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v34
-; SI-NEXT: v_or_b32_e32 v27, v28, v27
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_or_b32_e32 v28, v28, v30
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v43
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v31
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v41
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; SI-NEXT: v_or_b32_e32 v30, v30, v33
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v64bf16_to_v64f16:
@@ -216474,6 +218194,26 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -216490,1109 +218230,1141 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v29
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v25
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v30
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v30
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v28
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v27
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v23
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v20
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v11
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v13
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v18
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v41
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v36
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v29
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v9
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v17
-; SI-NEXT: ; kill: killed $vgpr15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v10
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v31
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v31
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v25
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v62
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; kill: killed $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; kill: killed $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; kill: killed $vgpr15
; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; kill: killed $vgpr19
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v40
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v33
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v61
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v60
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v43
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v42
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v59
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v58
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v45
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v44
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v47
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v46
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v57
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v56
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v55
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v54
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v53
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v49
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v23
-; SI-NEXT: ; kill: killed $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; kill: killed $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; kill: killed $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; kill: killed $vgpr15
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; kill: killed $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; kill: killed $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; kill: killed $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; kill: killed $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; kill: killed $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB104_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v26
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v62
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; kill: killed $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; kill: killed $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; kill: killed $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; kill: killed $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v58
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v57
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v56
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v47
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v22
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v43
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v30
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v56
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v58
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v61
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v60
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v62
; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: .LBB104_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB104_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v38
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v26
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v19
-; SI-NEXT: v_alignbit_b32 v0, v15, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_alignbit_b32 v1, v3, v1, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v32
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v62
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v4, v0, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v60
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v59
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v6, v0, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; SI-NEXT: v_alignbit_b32 v0, v11, v0, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v11
-; SI-NEXT: v_alignbit_b32 v0, v13, v0, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v56
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; SI-NEXT: v_alignbit_b32 v7, v9, v7, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v12
-; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
-; SI-NEXT: v_alignbit_b32 v0, v12, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v35
-; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v12, v0, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v9
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v46
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v45
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v30
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
-; SI-NEXT: v_alignbit_b32 v0, v13, v0, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v11
+; SI-NEXT: v_alignbit_b32 v10, v13, v10, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v44
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_alignbit_b32 v0, v14, v0, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v10, v14, v10, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v43
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
-; SI-NEXT: v_alignbit_b32 v0, v15, v0, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v10, v15, v10, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v42
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
-; SI-NEXT: v_alignbit_b32 v0, v16, v0, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v18, v16, v0, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v60
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v61
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v20, v16, v15, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v58
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v59
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v21, v16, v15, 16
+; SI-NEXT: v_alignbit_b32 v10, v16, v10, 16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v28
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v56
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v57
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v22, v16, v15, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v46
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v47
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v24, v16, v15, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v44
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v26, v16, v15, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v42
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v43
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: v_alignbit_b32 v27, v16, v15, 16
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_alignbit_b32 v10, v17, v10, 16
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; SI-NEXT: v_alignbit_b32 v0, v18, v0, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v17
+; SI-NEXT: v_alignbit_b32 v10, v18, v10, 16
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v55, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v55
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; SI-NEXT: v_alignbit_b32 v10, v19, v10, 16
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v31, v32, v8, 16
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_alignbit_b32 v41, v31, v8, 16
+; SI-NEXT: v_alignbit_b32 v1, v40, v1, 16
+; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
+; SI-NEXT: v_alignbit_b32 v29, v33, v10, 16
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v17
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v55, v29, v10, 16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_alignbit_b32 v27, v34, v12, 16
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v33, v50, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v34, v51, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_alignbit_b32 v25, v35, v16, 16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v25, v52, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v28, v39, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v17
+; SI-NEXT: v_alignbit_b32 v23, v36, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v23, v53, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
+; SI-NEXT: v_alignbit_b32 v21, v37, v15, 16
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: v_alignbit_b32 v31, v48, v15, 16
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
+; SI-NEXT: v_alignbit_b32 v19, v38, v13, 16
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v13
+; SI-NEXT: v_alignbit_b32 v17, v39, v11, 16
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v11
+; SI-NEXT: v_alignbit_b32 v15, v48, v9, 16
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v9
+; SI-NEXT: v_alignbit_b32 v13, v49, v7, 16
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v40, v54, v16, 16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v40, v1, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v9
+; SI-NEXT: v_alignbit_b32 v11, v50, v7, 16
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v7
+; SI-NEXT: v_alignbit_b32 v9, v51, v5, 16
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
+; SI-NEXT: v_alignbit_b32 v7, v52, v5, 16
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
+; SI-NEXT: v_alignbit_b32 v5, v53, v3, 16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_alignbit_b32 v3, v54, v3, 16
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v23, v3, 16
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v3, v30, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v5, 16
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v5, v2, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v34, v7, 16
-; SI-NEXT: v_alignbit_b32 v15, v49, v15, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v7, v28, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v9, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v9, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v15, v2, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v11, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v4, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; SI-NEXT: v_alignbit_b32 v17, v55, v16, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v19
-; SI-NEXT: v_mov_b32_e32 v19, v28
+; SI-NEXT: v_alignbit_b32 v0, v13, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v19, v6, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v27, v11, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v26, v10, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v24, v8, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v22, v12, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v21, v13, 16
-; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v20, v14, 16
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v15, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v17, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v19, v20, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v21, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v25, v16, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v27, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: .LBB104_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v52
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v51
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v50
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v55
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v40
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v23
+; SI-NEXT: v_or_b32_e32 v4, v4, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v52
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v51
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v10, v10, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v50
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v31
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v48
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v19
+; SI-NEXT: v_or_b32_e32 v16, v16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v38
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v37
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
+; SI-NEXT: v_or_b32_e32 v22, v22, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
+; SI-NEXT: v_or_b32_e32 v24, v24, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
+; SI-NEXT: v_or_b32_e32 v26, v26, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v34
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_or_b32_e32 v28, v28, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v41
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
-; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v31, v31, v32
+; SI-NEXT: v_or_b32_e32 v30, v30, v33
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v64bf16_to_v64i16:
@@ -223693,140 +225465,174 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v4
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v6
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v5
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v44
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v45
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v46
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v47
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v56
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v57
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v59
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v60
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v60
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v63
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v62
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; kill: killed $vgpr62
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
@@ -223834,103 +225640,206 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v31
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v32
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v34
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v36
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v63
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v33
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v35
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v37
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v38
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v39
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v48
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v49
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v50
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v51
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v52
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v53
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v54
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v55
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v40
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v41
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v42
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v45
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v46
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v47
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v56
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v57
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v58
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v60
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v61
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
@@ -223957,467 +225866,649 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr33
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB106_2: ; %Flow
-; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_or_b32_e32 v6, v33, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v33, v5
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_or_b32_e32 v0, v31, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v1, v32, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v4, v35, v4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_or_b32_e32 v7, v35, v7
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v8, v37, v8
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v9, v38, v9
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
+; SI-NEXT: v_or_b32_e32 v10, v39, v10
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_or_b32_e32 v11, v48, v11
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_or_b32_e32 v12, v49, v12
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_or_b32_e32 v4, v33, v4
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v33, v3
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v33, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v7, v38, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v9, v48, v9
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v10, v49, v10
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v11, v50, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v9
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v11
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v14, v53, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v13, v50, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v15, v54, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_or_b32_e32 v14, v51, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v16, v55, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_or_b32_e32 v15, v52, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v14
-; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v17, v40, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
+; SI-NEXT: v_or_b32_e32 v16, v53, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v15
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v18, v41, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v17, v54, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v19, v42, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
+; SI-NEXT: v_or_b32_e32 v18, v55, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v40
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v17
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v20, v43, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_or_b32_e32 v19, v40, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v18
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v41
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v18
-; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v21, v44, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
+; SI-NEXT: v_or_b32_e32 v20, v41, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v19
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v42
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v19
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
-; SI-NEXT: v_or_b32_e32 v22, v45, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v21, v42, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v43
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v20
-; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v23, v46, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
+; SI-NEXT: v_or_b32_e32 v22, v43, v22
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v44
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v21
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
-; SI-NEXT: v_or_b32_e32 v24, v47, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_or_b32_e32 v23, v44, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v22
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v45
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v25, v56, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
+; SI-NEXT: v_or_b32_e32 v24, v45, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v46
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v26, v57, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v25, v46, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v47
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v24
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_or_b32_e32 v27, v58, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
+; SI-NEXT: v_or_b32_e32 v26, v47, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v25
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v56
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v25
-; SI-NEXT: v_or_b32_e32 v30, v61, v30
-; SI-NEXT: v_or_b32_e32 v60, v60, v29
-; SI-NEXT: v_or_b32_e32 v59, v59, v28
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v58
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_or_b32_e32 v27, v56, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
+; SI-NEXT: v_or_b32_e32 v58, v58, v29
+; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v57
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v26
-; SI-NEXT: v_add_i32_e32 v63, vcc, 3, v63
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v30
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v60
-; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v57, v29, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v59
+; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v57
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v27
-; SI-NEXT: v_and_b32_e32 v63, 0xffff, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v30, v59, v30
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v60
-; SI-NEXT: v_or_b32_e32 v62, v62, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57
+; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v30
+; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v58
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v57
+; SI-NEXT: v_add_i32_e32 v60, vcc, 3, v60
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v30
+; SI-NEXT: v_and_b32_e32 v60, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v30
-; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v60, v61, v60
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v29
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v60
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v29
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v8
-; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v12
-; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v13
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v14
-; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v15
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v17
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v19
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v20
-; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v21
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v23
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v24
-; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v25
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v26
-; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v27
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v60
-; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v30
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v34
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v35
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v36
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v38
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v39
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v48
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v49
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v52
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v53
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v54
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v55
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_alignbit_b32 v16, v16, v17, 16
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v40
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
; SI-NEXT: v_alignbit_b32 v17, v17, v18, 16
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
; SI-NEXT: v_alignbit_b32 v18, v18, v19, 16
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v42
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
; SI-NEXT: v_alignbit_b32 v19, v19, v20, 16
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v43
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v44
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v45
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v46
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v47
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
; SI-NEXT: v_alignbit_b32 v24, v24, v25, 16
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v56
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
; SI-NEXT: v_alignbit_b32 v25, v25, v26, 16
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v57
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v58
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v59
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v60
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v61
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v62
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
; SI-NEXT: v_alignbit_b32 v31, v31, v32, 16
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v64i16_to_v64bf16:
@@ -227805,76 +229896,106 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v64i16_to_v64f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
+; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v26
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v24
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v4
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v22
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v49
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v48
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v8
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v39
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v38
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v7
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v5
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v10
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v4
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -227891,379 +230012,288 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v36
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v24
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v3
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v5
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v60
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v40
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v11
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v11
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v13
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v9
+; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v51
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v47
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v37
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v46
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v59
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v57
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v44
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v42
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v52
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; kill: killed $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; kill: killed $vgpr55
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
+; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v58
-; SI-NEXT: v_or_b32_e32 v61, v1, v50
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v34
+; SI-NEXT: v_or_b32_e32 v63, v1, v54
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
-; SI-NEXT: v_or_b32_e32 v47, v1, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36
+; SI-NEXT: v_or_b32_e32 v58, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
-; SI-NEXT: v_or_b32_e32 v62, v1, v3
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v56, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
-; SI-NEXT: v_or_b32_e32 v59, v1, v3
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v47, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
-; SI-NEXT: v_or_b32_e32 v57, v1, v3
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v61, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v62, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v56, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v1, v47, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v60, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v46, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v62, v9, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v59, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v44, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v59, v11, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v57, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v43, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v57, v13, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v46, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v42, v1, v48
-; SI-NEXT: v_alignbit_b32 v1, v56, v15, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: v_or_b32_e32 v45, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v41, v1, v49
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v46, v17, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v44, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: v_or_b32_e32 v55, v1, v39
-; SI-NEXT: v_alignbit_b32 v1, v44, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v42, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
-; SI-NEXT: v_or_b32_e32 v53, v1, v4
-; SI-NEXT: v_alignbit_b32 v1, v43, v35, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
+; SI-NEXT: v_or_b32_e32 v41, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v4, v1, v6
-; SI-NEXT: v_alignbit_b32 v1, v42, v32, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v52
+; SI-NEXT: v_or_b32_e32 v40, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v3, v1, v8
-; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v53
+; SI-NEXT: v_or_b32_e32 v54, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v55, v1, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v50, v1, v31
-; SI-NEXT: v_alignbit_b32 v1, v55, v45, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v63, v1, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v58, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v53, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v4, v33, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v56, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v3, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v47, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v50, v2, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v62, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v1, v1, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v60, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v1, v1, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v59, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v57, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v1, v1, v35
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v46, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v45, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v44, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v1, v1, v45
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v42, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v41, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v1, v1, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v40, v0, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v61
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v54, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v30
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v55, v0, 16
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
@@ -228271,360 +230301,359 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; kill: killed $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v0, v28
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v32
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v61
+; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
+; SI-NEXT: v_or_b32_e32 v28, v32, v28
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v29, v32, v29
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v30
+; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v28
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v30
-; SI-NEXT: v_or_b32_e32 v8, v8, v28
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v27
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v6, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v38, v0
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v25
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v36, v0
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v37
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v30
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v50
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v29
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v31
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v55
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v34, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_or_b32_e32 v26, v28, v26
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v52
+; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v40
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v15, v0
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_or_b32_e32 v24, v26, v24
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v51
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v41
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v12, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v50
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v42
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v13, v0
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v49
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v44
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v48
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v45
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v56
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v39
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v46
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v38
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v57
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v9, v0
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v57
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v37
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v59
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v9, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v35
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v60
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v59
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v62
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v62
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v47
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v61, v3, 16
+; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v63, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v47, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v58, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v62, v7, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v56, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v59, v9, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v47, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v57, v11, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v62, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v56, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v60, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v46, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v59, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v44, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v57, v16, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v43, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v46, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v42, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v45, v20, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v41, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v44, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v55, v4, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v42, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v53, v24, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v41, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v6, v8, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v40, v28, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v2, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v54, v30, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v50, v28, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v55, v32, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v63
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v47
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v51
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v53
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v63
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(8)
@@ -228646,63 +230675,81 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v47
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v62
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v59
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v57
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v62
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v56
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v60
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v46
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v59
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v44
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v57
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v43
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v46
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v42
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v45
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v41
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v44
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v42
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v40
+; SI-NEXT: v_or_b32_e32 v27, v27, v28
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -228720,37 +230767,15 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v53
-; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v54
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v50
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 8b971fe4c291d..9dbf88cd3115f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -1344,15 +1344,11 @@ define <4 x i32> @bitcast_v8i16_to_v4i32(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v5, v2
; SI-NEXT: v_mov_b32_e32 v6, v1
; SI-NEXT: v_mov_b32_e32 v7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1365,35 +1361,43 @@ define <4 x i32> @bitcast_v8i16_to_v4i32(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_or_b32_e32 v1, v10, v1
-; SI-NEXT: v_or_b32_e32 v2, v9, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -2461,22 +2465,14 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2488,14 +2484,23 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB22_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
@@ -2503,30 +2508,37 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: .LBB22_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -3969,17 +3981,11 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v16i8_to_v4i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v18, v2
-; SI-NEXT: v_mov_b32_e32 v17, v0
+; SI-NEXT: v_mov_b32_e32 v20, v3
+; SI-NEXT: v_mov_b32_e32 v17, v2
+; SI-NEXT: v_mov_b32_e32 v18, v1
+; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3991,93 +3997,109 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v22
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v20
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v16
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v7
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v20, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v7, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -5830,15 +5852,11 @@ define <4 x float> @bitcast_v8i16_to_v4f32(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v5, v2
; SI-NEXT: v_mov_b32_e32 v6, v1
; SI-NEXT: v_mov_b32_e32 v7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5851,35 +5869,43 @@ define <4 x float> @bitcast_v8i16_to_v4f32(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB38_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: .LBB38_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_or_b32_e32 v1, v10, v1
-; SI-NEXT: v_or_b32_e32 v2, v9, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -6963,22 +6989,14 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6990,14 +7008,23 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB46_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
@@ -7005,30 +7032,37 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_2
; SI-NEXT: .LBB46_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -8496,17 +8530,11 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v16i8_to_v4f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v18, v2
-; SI-NEXT: v_mov_b32_e32 v17, v0
+; SI-NEXT: v_mov_b32_e32 v20, v3
+; SI-NEXT: v_mov_b32_e32 v17, v2
+; SI-NEXT: v_mov_b32_e32 v18, v1
+; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -8518,93 +8546,109 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v22
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v20
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v16
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v7
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v20, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v7, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -9981,15 +10025,11 @@ define <2 x i64> @bitcast_v8i16_to_v2i64(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v5, v2
; SI-NEXT: v_mov_b32_e32 v6, v1
; SI-NEXT: v_mov_b32_e32 v7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -10002,35 +10042,43 @@ define <2 x i64> @bitcast_v8i16_to_v2i64(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB58_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: .LBB58_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_or_b32_e32 v1, v10, v1
-; SI-NEXT: v_or_b32_e32 v2, v9, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -11100,22 +11148,14 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -11127,14 +11167,23 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB66_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
@@ -11142,30 +11191,37 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB66_2
; SI-NEXT: .LBB66_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -12608,17 +12664,11 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v16i8_to_v2i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v18, v2
-; SI-NEXT: v_mov_b32_e32 v17, v0
+; SI-NEXT: v_mov_b32_e32 v20, v3
+; SI-NEXT: v_mov_b32_e32 v17, v2
+; SI-NEXT: v_mov_b32_e32 v18, v1
+; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -12630,93 +12680,109 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB70_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v22
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v20
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v16
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v7
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: .LBB70_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v20, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v7, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -13729,15 +13795,11 @@ define <2 x double> @bitcast_v8i16_to_v2f64(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v5, v2
; SI-NEXT: v_mov_b32_e32 v6, v1
; SI-NEXT: v_mov_b32_e32 v7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -13750,35 +13812,43 @@ define <2 x double> @bitcast_v8i16_to_v2f64(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB74_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_2
; SI-NEXT: .LBB74_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_or_b32_e32 v1, v10, v1
-; SI-NEXT: v_or_b32_e32 v2, v9, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -14838,22 +14908,14 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -14865,14 +14927,23 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB82_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v7, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v5, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
@@ -14880,30 +14951,37 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB82_2
; SI-NEXT: .LBB82_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v5
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -16358,17 +16436,11 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v16i8_to_v2f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v18, v2
-; SI-NEXT: v_mov_b32_e32 v17, v0
+; SI-NEXT: v_mov_b32_e32 v20, v3
+; SI-NEXT: v_mov_b32_e32 v17, v2
+; SI-NEXT: v_mov_b32_e32 v18, v1
+; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -16380,93 +16452,109 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB86_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v22
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v20
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v16
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v7
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_2
; SI-NEXT: .LBB86_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v18
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v20, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v7, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -17246,17 +17334,13 @@ define <8 x half> @bitcast_v8i16_to_v8f16(<8 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v8i16_to_v8f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v7
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr11
@@ -17266,61 +17350,67 @@ define <8 x half> @bitcast_v8i16_to_v8f16(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB88_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v8, v1, v13
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; SI-NEXT: v_or_b32_e32 v8, v1, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v13
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v1, v15
-; SI-NEXT: v_or_b32_e32 v9, v0, v12
+; SI-NEXT: v_or_b32_e32 v4, v3, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12
+; SI-NEXT: v_or_b32_e32 v10, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_alignbit_b32 v10, v8, v12, 16
-; SI-NEXT: v_alignbit_b32 v11, v4, v14, 16
-; SI-NEXT: v_or_b32_e32 v7, v0, v14
+; SI-NEXT: v_alignbit_b32 v9, v8, v1, 16
+; SI-NEXT: v_alignbit_b32 v11, v4, v3, 16
+; SI-NEXT: v_or_b32_e32 v7, v0, v3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: .LBB88_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v14, v2
-; SI-NEXT: v_or_b32_e32 v0, v12, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v15, v2
-; SI-NEXT: v_or_b32_e32 v0, v13, v0
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
-; SI-NEXT: v_alignbit_b32 v10, v8, v9, 16
+; SI-NEXT: v_alignbit_b32 v9, v8, v10, 16
; SI-NEXT: v_alignbit_b32 v11, v4, v7, 16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
; SI-NEXT: .LBB88_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -17892,76 +17982,88 @@ define <8 x bfloat> @bitcast_v8i16_to_v8bf16(<8 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v8i16_to_v8bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v15
; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v13
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v3, v7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v6, v2
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v10
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v11
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v9
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -18219,94 +18321,103 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v8bf16_to_v8i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v5
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB94_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: .LBB94_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v15
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v12
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v12
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v7
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v10
; SI-NEXT: v_alignbit_b32 v3, v4, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_alignbit_b32 v1, v5, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v6, v1, v6, 16
-; SI-NEXT: v_alignbit_b32 v7, v3, v7, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_alignbit_b32 v1, v6, v1, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_alignbit_b32 v5, v1, v5, 16
+; SI-NEXT: v_alignbit_b32 v8, v3, v7, 16
; SI-NEXT: .LBB94_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_or_b32_e32 v1, v1, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
; SI-NEXT: v_or_b32_e32 v2, v2, v5
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -19132,14 +19243,10 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v17, v1
; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v14
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -19164,14 +19271,18 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB96_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v8, v5, v22
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v8, v5, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v4, v1, v21
-; SI-NEXT: v_or_b32_e32 v12, v5, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v1, v2
+; SI-NEXT: v_or_b32_e32 v12, v5, v7
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -19183,31 +19294,33 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
; SI-NEXT: v_bfe_u32 v7, v6, 8, 8
; SI-NEXT: v_bfe_u32 v15, v14, 8, 8
; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: .LBB96_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v20, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
@@ -19231,20 +19344,20 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
; VI-NEXT: v_mov_b32_e32 v19, v3
; VI-NEXT: v_mov_b32_e32 v18, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr13
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -19252,10 +19365,14 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
; VI-NEXT: s_cbranch_execz .LBB96_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v18
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v0
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[18:19]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
@@ -19857,141 +19974,149 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v9
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v13
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v3
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v18, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v17
-; SI-NEXT: v_or_b32_e32 v3, v3, v21
-; SI-NEXT: v_or_b32_e32 v6, v20, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v9, v0, v2
+; SI-NEXT: v_or_b32_e32 v16, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v20, v0, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v7, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v11, v3, v5, 16
-; SI-NEXT: v_or_b32_e32 v5, v0, v5
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
+; SI-NEXT: v_alignbit_b32 v19, v18, v2, 16
+; SI-NEXT: v_alignbit_b32 v21, v16, v3, 16
+; SI-NEXT: v_or_b32_e32 v17, v0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: .LBB98_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v23, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v22, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v13, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x300, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v18, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v7, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v11, v3, v5, 16
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
+; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v19, v18, v20, 16
+; SI-NEXT: v_alignbit_b32 v21, v16, v17, 16
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v16
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v19
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v23
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -21152,23 +21277,15 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v8bf16_to_v8f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
@@ -21181,52 +21298,68 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_alignbit_b32 v5, v1, v9, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v14
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_alignbit_b32 v6, v5, v0, 16
-; SI-NEXT: v_alignbit_b32 v4, v3, v12, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v7, v4, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: v_alignbit_b32 v0, v0, v15, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v13, 16
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
+; SI-NEXT: v_alignbit_b32 v5, v1, v0, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v15
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; SI-NEXT: v_alignbit_b32 v6, v5, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v4, v3, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v14
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v7, v4, v7, 16
+; SI-NEXT: v_alignbit_b32 v0, v0, v9, 16
+; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: .LBB102_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v11
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v9
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v4, v3, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v5, v1, v5, 16
@@ -22216,27 +22349,31 @@ define <16 x i8> @bitcast_v8f16_to_v16i8(<8 x half> %a, i32 %b) {
; VI-NEXT: v_mov_b32_e32 v19, v1
; VI-NEXT: v_mov_b32_e32 v18, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v17
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v19
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr13
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB104_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v16
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v19
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v19
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[16:17]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[18:19]
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v18
@@ -22853,141 +22990,149 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v9
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v13
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v3
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v18, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v17
-; SI-NEXT: v_or_b32_e32 v3, v3, v21
-; SI-NEXT: v_or_b32_e32 v6, v20, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v9, v0, v2
+; SI-NEXT: v_or_b32_e32 v16, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v20, v0, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v7, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v11, v3, v5, 16
-; SI-NEXT: v_or_b32_e32 v5, v0, v5
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
+; SI-NEXT: v_alignbit_b32 v19, v18, v2, 16
+; SI-NEXT: v_alignbit_b32 v21, v16, v3, 16
+; SI-NEXT: v_or_b32_e32 v17, v0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: .LBB106_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v23, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v22, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v21, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v13, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x300, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v18, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v7, v1, v9, 16
-; SI-NEXT: v_alignbit_b32 v11, v3, v5, 16
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
+; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v19, v18, v20, 16
+; SI-NEXT: v_alignbit_b32 v21, v16, v17, 16
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v16
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v19
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v23
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -23788,23 +23933,15 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v8bf16_to_v16i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v2
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v1
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -23831,55 +23968,71 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB108_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v17
-; SI-NEXT: v_alignbit_b32 v0, v0, v20, 16
-; SI-NEXT: v_alignbit_b32 v4, v6, v18, 16
-; SI-NEXT: v_alignbit_b32 v8, v5, v23, 16
-; SI-NEXT: v_alignbit_b32 v12, v14, v21, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_alignbit_b32 v8, v7, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v17
+; SI-NEXT: v_alignbit_b32 v4, v6, v1, 16
+; SI-NEXT: v_alignbit_b32 v12, v14, v7, 16
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
; SI-NEXT: v_alignbit_b32 v11, v12, v8, 24
; SI-NEXT: v_alignbit_b32 v10, v12, v8, 16
; SI-NEXT: v_alignbit_b32 v9, v12, v8, 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v16
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v13
; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB108_2
; SI-NEXT: .LBB108_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v8, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
; SI-NEXT: v_alignbit_b32 v12, v14, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
@@ -25156,20 +25309,14 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v15
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
@@ -25177,122 +25324,134 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; SI-NEXT: v_or_b32_e32 v3, v1, v0
+; SI-NEXT: v_or_b32_e32 v16, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v5, v16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_or_b32_e32 v17, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v21
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v11, v18, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_or_b32_e32 v19, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
-; SI-NEXT: v_or_b32_e32 v13, v1, v0
+; SI-NEXT: v_or_b32_e32 v20, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v15, v20, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
+; SI-NEXT: v_or_b32_e32 v21, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v22, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v15
+; SI-NEXT: v_or_b32_e32 v23, v1, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v23, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v3, v21, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x300, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v18, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v8
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v12
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v8
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v23
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v22
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
index 430a93d9e9bf0..b15e4cab483bc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
@@ -668,17 +668,12 @@ define <5 x i32> @bitcast_v10i16_to_v5i32(<10 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v7, v2
; SI-NEXT: v_mov_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -691,43 +686,53 @@ define <5 x i32> @bitcast_v10i16_to_v5i32(<10 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: v_or_b32_e32 v1, v1, v13
-; SI-NEXT: v_or_b32_e32 v2, v2, v12
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v14, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v13, v1
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
-; SI-NEXT: v_or_b32_e32 v3, v11, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -1902,17 +1907,12 @@ define <5 x float> @bitcast_v10i16_to_v5f32(<10 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v7, v2
; SI-NEXT: v_mov_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1925,43 +1925,53 @@ define <5 x float> @bitcast_v10i16_to_v5f32(<10 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: v_or_b32_e32 v1, v1, v13
-; SI-NEXT: v_or_b32_e32 v2, v2, v12
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v14, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v13, v1
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
-; SI-NEXT: v_or_b32_e32 v3, v11, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -2873,16 +2883,11 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr10
@@ -2895,56 +2900,63 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB20_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; SI-NEXT: v_or_b32_e32 v10, v1, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v10, v1, v16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v11, v0, v17
+; SI-NEXT: v_or_b32_e32 v5, v3, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v11, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v5, v1, v18
-; SI-NEXT: v_or_b32_e32 v9, v0, v19
+; SI-NEXT: v_alignbit_b32 v12, v10, v1, 16
+; SI-NEXT: v_or_b32_e32 v9, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_alignbit_b32 v12, v10, v17, 16
-; SI-NEXT: v_alignbit_b32 v13, v5, v19, 16
-; SI-NEXT: v_or_b32_e32 v14, v0, v15
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_alignbit_b32 v13, v5, v3, 16
+; SI-NEXT: v_or_b32_e32 v14, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: .LBB20_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_4
; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v19, v2
-; SI-NEXT: v_or_b32_e32 v0, v16, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
-; SI-NEXT: v_or_b32_e32 v0, v15, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v12, v10, v11, 16
; SI-NEXT: v_alignbit_b32 v13, v5, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
; SI-NEXT: .LBB20_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -2952,13 +2964,13 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
index dd9fa1456e37a..4b728e1a38cc0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
@@ -398,15 +398,20 @@ define bfloat @bitcast_i16_to_bf16(i16 %a, i32 %b) {
; SI-LABEL: bitcast_i16_to_bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: ; %bb.2: ; %end
+; SI-NEXT: ; %bb.4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -580,9 +585,8 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {
; SI-LABEL: bitcast_bf16_to_i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -594,12 +598,14 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -1053,9 +1059,8 @@ define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) {
; SI-LABEL: bitcast_bf16_to_f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1067,12 +1072,14 @@ define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB10_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB10_2
; SI-NEXT: .LBB10_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
index d463b115d1088..d7bca3d2ab4e7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
@@ -1528,19 +1528,13 @@ define <6 x i32> @bitcast_v12i16_to_v6i32(<12 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v9, v2
; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v11, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1553,16 +1547,22 @@ define <6 x i32> @bitcast_v12i16_to_v6i32(<12 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v1, v16
-; SI-NEXT: v_or_b32_e32 v2, v2, v15
-; SI-NEXT: v_or_b32_e32 v3, v3, v14
-; SI-NEXT: v_or_b32_e32 v4, v4, v13
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -1570,33 +1570,39 @@ define <6 x i32> @bitcast_v12i16_to_v6i32(<12 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v2, v15, v2
-; SI-NEXT: v_or_b32_e32 v3, v14, v3
-; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -3704,19 +3710,13 @@ define <6 x float> @bitcast_v12i16_to_v6f32(<12 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v9, v2
; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v11, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3729,16 +3729,22 @@ define <6 x float> @bitcast_v12i16_to_v6f32(<12 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB30_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v1, v16
-; SI-NEXT: v_or_b32_e32 v2, v2, v15
-; SI-NEXT: v_or_b32_e32 v3, v3, v14
-; SI-NEXT: v_or_b32_e32 v4, v4, v13
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -3746,33 +3752,39 @@ define <6 x float> @bitcast_v12i16_to_v6f32(<12 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: .LBB30_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v2, v15, v2
-; SI-NEXT: v_or_b32_e32 v3, v14, v3
-; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -5463,19 +5475,13 @@ define <3 x i64> @bitcast_v12i16_to_v3i64(<12 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v9, v2
; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v11, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5488,16 +5494,22 @@ define <3 x i64> @bitcast_v12i16_to_v3i64(<12 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB42_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v1, v16
-; SI-NEXT: v_or_b32_e32 v2, v2, v15
-; SI-NEXT: v_or_b32_e32 v3, v3, v14
-; SI-NEXT: v_or_b32_e32 v4, v4, v13
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -5505,33 +5517,39 @@ define <3 x i64> @bitcast_v12i16_to_v3i64(<12 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: .LBB42_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v2, v15, v2
-; SI-NEXT: v_or_b32_e32 v3, v14, v3
-; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -6805,19 +6823,13 @@ define <3 x double> @bitcast_v12i16_to_v3f64(<12 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v9, v2
; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v11, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6830,16 +6842,22 @@ define <3 x double> @bitcast_v12i16_to_v3f64(<12 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v1, v16
-; SI-NEXT: v_or_b32_e32 v2, v2, v15
-; SI-NEXT: v_or_b32_e32 v3, v3, v14
-; SI-NEXT: v_or_b32_e32 v4, v4, v13
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -6847,33 +6865,39 @@ define <3 x double> @bitcast_v12i16_to_v3f64(<12 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v2, v15, v2
-; SI-NEXT: v_or_b32_e32 v3, v14, v3
-; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -7857,23 +7881,17 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v12i16_to_v12f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v10
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -7884,76 +7902,85 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v13, v1, v19
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_or_b32_e32 v12, v1, v6
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v11, v1, v21
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v16, v0, v18
+; SI-NEXT: v_or_b32_e32 v11, v3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v9
+; SI-NEXT: v_or_b32_e32 v16, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v6, v1, v22
-; SI-NEXT: v_or_b32_e32 v12, v0, v20
+; SI-NEXT: v_or_b32_e32 v6, v5, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v13, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_alignbit_b32 v14, v13, v18, 16
-; SI-NEXT: v_alignbit_b32 v15, v11, v20, 16
-; SI-NEXT: v_alignbit_b32 v17, v6, v23, 16
-; SI-NEXT: v_or_b32_e32 v10, v0, v23
+; SI-NEXT: v_alignbit_b32 v14, v12, v1, 16
+; SI-NEXT: v_alignbit_b32 v15, v11, v3, 16
+; SI-NEXT: v_alignbit_b32 v17, v6, v5, 16
+; SI-NEXT: v_or_b32_e32 v10, v0, v5
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v23, v4
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v2, v20, v2
-; SI-NEXT: v_or_b32_e32 v0, v18, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v9
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v19
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v22, v4
-; SI-NEXT: v_or_b32_e32 v2, v21, v2
-; SI-NEXT: v_or_b32_e32 v0, v19, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v0
-; SI-NEXT: v_alignbit_b32 v14, v13, v16, 16
-; SI-NEXT: v_alignbit_b32 v15, v11, v12, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v0
+; SI-NEXT: v_alignbit_b32 v14, v12, v16, 16
+; SI-NEXT: v_alignbit_b32 v15, v11, v13, 16
; SI-NEXT: v_alignbit_b32 v17, v6, v10, 16
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v6
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v12
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v11
@@ -7963,7 +7990,7 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
index e0fac42ac9d77..451e3d915952a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
@@ -766,21 +766,14 @@ define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v11, v2
; SI-NEXT: v_mov_b32_e32 v12, v1
; SI-NEXT: v_mov_b32_e32 v13, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -793,18 +786,25 @@ define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v20
-; SI-NEXT: v_or_b32_e32 v1, v1, v19
-; SI-NEXT: v_or_b32_e32 v2, v2, v18
-; SI-NEXT: v_or_b32_e32 v3, v3, v17
-; SI-NEXT: v_or_b32_e32 v4, v4, v16
-; SI-NEXT: v_or_b32_e32 v5, v5, v15
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
@@ -813,37 +813,44 @@ define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v0, v20, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v19, v1
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
-; SI-NEXT: v_or_b32_e32 v3, v17, v3
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: v_or_b32_e32 v5, v15, v5
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -2255,21 +2262,14 @@ define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v11, v2
; SI-NEXT: v_mov_b32_e32 v12, v1
; SI-NEXT: v_mov_b32_e32 v13, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2282,18 +2282,25 @@ define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v20
-; SI-NEXT: v_or_b32_e32 v1, v1, v19
-; SI-NEXT: v_or_b32_e32 v2, v2, v18
-; SI-NEXT: v_or_b32_e32 v3, v3, v17
-; SI-NEXT: v_or_b32_e32 v4, v4, v16
-; SI-NEXT: v_or_b32_e32 v5, v5, v15
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
@@ -2302,37 +2309,44 @@ define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v0, v20, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v19, v1
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
-; SI-NEXT: v_or_b32_e32 v3, v17, v3
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: v_or_b32_e32 v5, v15, v5
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -3431,27 +3445,20 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr20
@@ -3460,22 +3467,29 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB20_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v9
+; SI-NEXT: v_or_b32_e32 v14, v1, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v15, v1, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v16, v0, v22
+; SI-NEXT: v_or_b32_e32 v13, v3, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; SI-NEXT: v_or_b32_e32 v17, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v13, v1, v25
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v14, v0, v24
+; SI-NEXT: v_or_b32_e32 v7, v5, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v15, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v7, v1, v26
-; SI-NEXT: v_or_b32_e32 v11, v0, v27
+; SI-NEXT: v_alignbit_b32 v16, v14, v1, 16
+; SI-NEXT: v_or_b32_e32 v12, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_alignbit_b32 v17, v15, v22, 16
-; SI-NEXT: v_alignbit_b32 v18, v13, v24, 16
-; SI-NEXT: v_alignbit_b32 v19, v7, v27, 16
-; SI-NEXT: v_or_b32_e32 v20, v0, v21
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v8
+; SI-NEXT: v_alignbit_b32 v18, v13, v3, 16
+; SI-NEXT: v_alignbit_b32 v19, v7, v5, 16
+; SI-NEXT: v_or_b32_e32 v20, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -3483,72 +3497,75 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: .LBB20_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v22, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v27, v4
-; SI-NEXT: v_or_b32_e32 v2, v24, v2
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v7, v4
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v26, v4
-; SI-NEXT: v_or_b32_e32 v2, v25, v2
-; SI-NEXT: v_or_b32_e32 v0, v21, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v8
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v0
-; SI-NEXT: v_alignbit_b32 v17, v15, v16, 16
-; SI-NEXT: v_alignbit_b32 v18, v13, v14, 16
-; SI-NEXT: v_alignbit_b32 v19, v7, v11, 16
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v15
+; SI-NEXT: v_alignbit_b32 v16, v14, v17, 16
+; SI-NEXT: v_alignbit_b32 v18, v13, v15, 16
+; SI-NEXT: v_alignbit_b32 v19, v7, v12, 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
; SI-NEXT: .LBB20_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v18
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v19
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v8
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 2123bed663ebb..38730ee530ce4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -1715,23 +1715,15 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v13, v2
; SI-NEXT: v_mov_b32_e32 v14, v1
; SI-NEXT: v_mov_b32_e32 v15, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v15
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1744,20 +1736,28 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v22
-; SI-NEXT: v_or_b32_e32 v2, v2, v21
-; SI-NEXT: v_or_b32_e32 v3, v3, v20
-; SI-NEXT: v_or_b32_e32 v4, v4, v19
-; SI-NEXT: v_or_b32_e32 v5, v5, v18
-; SI-NEXT: v_or_b32_e32 v6, v6, v17
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
@@ -1767,6 +1767,7 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
@@ -1774,34 +1775,41 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v22, v1
-; SI-NEXT: v_or_b32_e32 v2, v21, v2
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v4, v19, v4
-; SI-NEXT: v_or_b32_e32 v5, v18, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -3375,38 +3383,22 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3418,46 +3410,66 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB22_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v13
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v14
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: .LBB22_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -3465,38 +3477,50 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v17
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v15
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v13
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v11
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
@@ -6019,31 +6043,18 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v8i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: v_mov_b32_e32 v38, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: v_mov_b32_e32 v31, v7
+; SI-NEXT: v_mov_b32_e32 v32, v6
+; SI-NEXT: v_mov_b32_e32 v33, v5
+; SI-NEXT: v_mov_b32_e32 v34, v4
+; SI-NEXT: v_mov_b32_e32 v35, v3
+; SI-NEXT: v_mov_b32_e32 v36, v2
+; SI-NEXT: v_mov_b32_e32 v37, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6053,179 +6064,214 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) {
; SI-NEXT: s_cbranch_execnz .LBB26_4
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v19
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v15
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v11
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v39
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v32
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v48, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v36, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v19, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v15, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v11, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x300, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -8910,23 +8956,15 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v13, v2
; SI-NEXT: v_mov_b32_e32 v14, v1
; SI-NEXT: v_mov_b32_e32 v15, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v15
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -8939,20 +8977,28 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB38_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v22
-; SI-NEXT: v_or_b32_e32 v2, v2, v21
-; SI-NEXT: v_or_b32_e32 v3, v3, v20
-; SI-NEXT: v_or_b32_e32 v4, v4, v19
-; SI-NEXT: v_or_b32_e32 v5, v5, v18
-; SI-NEXT: v_or_b32_e32 v6, v6, v17
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
@@ -8962,6 +9008,7 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
@@ -8969,34 +9016,41 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: .LBB38_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v22, v1
-; SI-NEXT: v_or_b32_e32 v2, v21, v2
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v4, v19, v4
-; SI-NEXT: v_or_b32_e32 v5, v18, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -10600,38 +10654,22 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -10643,46 +10681,66 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB46_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v13
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v14
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_2
; SI-NEXT: .LBB46_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -10690,38 +10748,50 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v17
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v15
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v13
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v11
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
@@ -13287,31 +13357,18 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v8f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: v_mov_b32_e32 v38, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: v_mov_b32_e32 v31, v7
+; SI-NEXT: v_mov_b32_e32 v32, v6
+; SI-NEXT: v_mov_b32_e32 v33, v5
+; SI-NEXT: v_mov_b32_e32 v34, v4
+; SI-NEXT: v_mov_b32_e32 v35, v3
+; SI-NEXT: v_mov_b32_e32 v36, v2
+; SI-NEXT: v_mov_b32_e32 v37, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -13321,179 +13378,214 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) {
; SI-NEXT: s_cbranch_execnz .LBB50_4
; SI-NEXT: .LBB50_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v19
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v15
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v11
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v39
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v32
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v48, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v36, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v19, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v15, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v11, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x300, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -15702,23 +15794,15 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v13, v2
; SI-NEXT: v_mov_b32_e32 v14, v1
; SI-NEXT: v_mov_b32_e32 v15, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v15
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -15731,20 +15815,28 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB58_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v22
-; SI-NEXT: v_or_b32_e32 v2, v2, v21
-; SI-NEXT: v_or_b32_e32 v3, v3, v20
-; SI-NEXT: v_or_b32_e32 v4, v4, v19
-; SI-NEXT: v_or_b32_e32 v5, v5, v18
-; SI-NEXT: v_or_b32_e32 v6, v6, v17
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
@@ -15754,6 +15846,7 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
@@ -15761,34 +15854,41 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: .LBB58_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v22, v1
-; SI-NEXT: v_or_b32_e32 v2, v21, v2
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v4, v19, v4
-; SI-NEXT: v_or_b32_e32 v5, v18, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -17366,38 +17466,22 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -17409,46 +17493,66 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB66_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v13
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v14
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB66_2
; SI-NEXT: .LBB66_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -17456,38 +17560,50 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v17
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v15
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v13
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v11
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
@@ -20016,31 +20132,18 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v4i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: v_mov_b32_e32 v38, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: v_mov_b32_e32 v31, v7
+; SI-NEXT: v_mov_b32_e32 v32, v6
+; SI-NEXT: v_mov_b32_e32 v33, v5
+; SI-NEXT: v_mov_b32_e32 v34, v4
+; SI-NEXT: v_mov_b32_e32 v35, v3
+; SI-NEXT: v_mov_b32_e32 v36, v2
+; SI-NEXT: v_mov_b32_e32 v37, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -20050,179 +20153,214 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) {
; SI-NEXT: s_cbranch_execnz .LBB70_4
; SI-NEXT: .LBB70_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB70_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v19
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v15
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v11
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v39
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: .LBB70_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v32
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v48, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v36, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v19, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v15, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v11, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x300, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -21975,23 +22113,15 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v13, v2
; SI-NEXT: v_mov_b32_e32 v14, v1
; SI-NEXT: v_mov_b32_e32 v15, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v15
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -22004,20 +22134,28 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB74_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v1, v1, v22
-; SI-NEXT: v_or_b32_e32 v2, v2, v21
-; SI-NEXT: v_or_b32_e32 v3, v3, v20
-; SI-NEXT: v_or_b32_e32 v4, v4, v19
-; SI-NEXT: v_or_b32_e32 v5, v5, v18
-; SI-NEXT: v_or_b32_e32 v6, v6, v17
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
@@ -22027,6 +22165,7 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
@@ -22034,34 +22173,41 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_2
; SI-NEXT: .LBB74_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v17
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v22, v1
-; SI-NEXT: v_or_b32_e32 v2, v21, v2
-; SI-NEXT: v_or_b32_e32 v3, v20, v3
-; SI-NEXT: v_or_b32_e32 v4, v19, v4
-; SI-NEXT: v_or_b32_e32 v5, v18, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -23611,38 +23757,22 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v5
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -23654,46 +23784,66 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB82_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v23, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v21, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v15, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v13, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v11, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v9, 16
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v16
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v13
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v14
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB82_2
; SI-NEXT: .LBB82_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -23701,38 +23851,50 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v17
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v14
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v15
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v13
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v14
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v10
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v11
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
@@ -26278,31 +26440,18 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v4f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: v_mov_b32_e32 v38, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: v_mov_b32_e32 v31, v7
+; SI-NEXT: v_mov_b32_e32 v32, v6
+; SI-NEXT: v_mov_b32_e32 v33, v5
+; SI-NEXT: v_mov_b32_e32 v34, v4
+; SI-NEXT: v_mov_b32_e32 v35, v3
+; SI-NEXT: v_mov_b32_e32 v36, v2
+; SI-NEXT: v_mov_b32_e32 v37, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -26312,179 +26461,214 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) {
; SI-NEXT: s_cbranch_execnz .LBB86_4
; SI-NEXT: .LBB86_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB86_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v19
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v15
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v11
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v39
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_2
; SI-NEXT: .LBB86_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v37
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v32
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v48, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v36, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v19, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v17, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v15, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v13, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v11, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x300, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -27913,33 +28097,25 @@ define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v16i16_to_v16f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v12
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -27947,25 +28123,33 @@ define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB88_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v17, v1, v25
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; SI-NEXT: v_or_b32_e32 v17, v1, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v15, v1, v27
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v22, v0, v24
+; SI-NEXT: v_or_b32_e32 v15, v3, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; SI-NEXT: v_or_b32_e32 v22, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v13, v1, v29
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v18, v0, v26
+; SI-NEXT: v_or_b32_e32 v14, v5, v8
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v12
+; SI-NEXT: v_or_b32_e32 v19, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v8, v1, v31
-; SI-NEXT: v_or_b32_e32 v16, v0, v28
+; SI-NEXT: v_or_b32_e32 v8, v7, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: v_or_b32_e32 v16, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_alignbit_b32 v19, v17, v24, 16
-; SI-NEXT: v_alignbit_b32 v20, v15, v26, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v28, 16
-; SI-NEXT: v_alignbit_b32 v23, v8, v30, 16
-; SI-NEXT: v_or_b32_e32 v12, v0, v30
+; SI-NEXT: v_alignbit_b32 v18, v17, v1, 16
+; SI-NEXT: v_alignbit_b32 v20, v15, v3, 16
+; SI-NEXT: v_alignbit_b32 v21, v14, v5, 16
+; SI-NEXT: v_alignbit_b32 v23, v8, v7, 16
+; SI-NEXT: v_or_b32_e32 v13, v0, v7
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -27974,84 +28158,88 @@ define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: .LBB88_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v6, v30, v6
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v4, v28, v4
-; SI-NEXT: v_or_b32_e32 v2, v26, v2
-; SI-NEXT: v_or_b32_e32 v0, v24, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v27
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v12
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v26
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v25
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v6, v31, v6
-; SI-NEXT: v_or_b32_e32 v4, v29, v4
-; SI-NEXT: v_or_b32_e32 v2, v27, v2
-; SI-NEXT: v_or_b32_e32 v0, v25, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v19, v17, v22, 16
-; SI-NEXT: v_alignbit_b32 v20, v15, v18, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v16, 16
-; SI-NEXT: v_alignbit_b32 v23, v8, v12, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_alignbit_b32 v18, v17, v22, 16
+; SI-NEXT: v_alignbit_b32 v20, v15, v19, 16
+; SI-NEXT: v_alignbit_b32 v21, v14, v16, 16
+; SI-NEXT: v_alignbit_b32 v23, v8, v13, 16
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v8
; SI-NEXT: .LBB88_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v18
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v20
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v21
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v23
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -28921,42 +29109,51 @@ define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v16i16_to_v16bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB92_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v31
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -28965,34 +29162,50 @@ define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: .LBB92_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v30
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v29
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_or_b32_e32 v5, v8, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_or_b32_e32 v4, v8, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v27
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v3, v8, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v8, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v8, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v7, v15, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v24
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v6, v14, v6
-; SI-NEXT: v_or_b32_e32 v5, v13, v5
-; SI-NEXT: v_or_b32_e32 v4, v12, v4
-; SI-NEXT: v_or_b32_e32 v3, v11, v3
-; SI-NEXT: v_or_b32_e32 v2, v10, v2
-; SI-NEXT: v_or_b32_e32 v1, v9, v1
; SI-NEXT: v_or_b32_e32 v0, v8, v0
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
@@ -29002,55 +29215,55 @@ define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v6
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v7
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v11
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v16
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v13
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v18
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v20
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v15
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v20
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v17
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v22
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v19
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v23
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v21
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -29435,173 +29648,189 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v16bf16_to_v16i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v7
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v6
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v4
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v3
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v2
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v1
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v9
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v22
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v20
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v18
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB94_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v28
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v28
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v2
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v26
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v12
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v26
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v24
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v18
; SI-NEXT: v_alignbit_b32 v6, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v16
; SI-NEXT: v_alignbit_b32 v7, v8, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v15
; SI-NEXT: v_alignbit_b32 v5, v9, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v14
; SI-NEXT: v_alignbit_b32 v3, v10, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
-; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v1, v11, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; SI-NEXT: v_alignbit_b32 v12, v1, v12, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_alignbit_b32 v1, v12, v1, 16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_alignbit_b32 v11, v1, v11, 16
; SI-NEXT: v_alignbit_b32 v13, v3, v13, 16
-; SI-NEXT: v_alignbit_b32 v14, v5, v14, 16
-; SI-NEXT: v_alignbit_b32 v17, v7, v17, 16
+; SI-NEXT: v_alignbit_b32 v17, v5, v16, 16
+; SI-NEXT: v_alignbit_b32 v23, v7, v18, 16
; SI-NEXT: .LBB94_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v1, v1, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v13
; SI-NEXT: v_or_b32_e32 v3, v3, v10
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT: v_or_b32_e32 v5, v5, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v23
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v12
; SI-NEXT: v_or_b32_e32 v2, v2, v11
; SI-NEXT: v_or_b32_e32 v4, v4, v10
; SI-NEXT: v_or_b32_e32 v6, v6, v9
@@ -31067,22 +31296,14 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v32, v1
; SI-NEXT: v_mov_b32_e32 v36, v0
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v36
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v30
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -31122,21 +31343,29 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB96_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v8, v5, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v49
+; SI-NEXT: v_or_b32_e32 v8, v5, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v12, v5, v50
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; SI-NEXT: v_or_b32_e32 v12, v5, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v38
-; SI-NEXT: v_or_b32_e32 v16, v5, v53
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v16, v5, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v34
-; SI-NEXT: v_or_b32_e32 v20, v5, v52
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v48
+; SI-NEXT: v_or_b32_e32 v20, v5, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v24, v5, v55
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v24, v5, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_or_b32_e32 v4, v1, v48
-; SI-NEXT: v_or_b32_e32 v28, v5, v54
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v4, v1, v2
+; SI-NEXT: v_or_b32_e32 v28, v5, v7
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -31165,48 +31394,52 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: .LBB96_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v53, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v22
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v50, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v36
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v48
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
@@ -31240,35 +31473,35 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
-; VI-NEXT: ; implicit-def: $vgpr50
-; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: ; implicit-def: $vgpr50
+; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr9
-; VI-NEXT: ; implicit-def: $vgpr35
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr13
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr21
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
-; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr27
@@ -31277,29 +31510,37 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI-NEXT: s_cbranch_execz .LBB96_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
+; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
+; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v5
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v5
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v4
; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v39, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v50, v0
-; VI-NEXT: v_mov_b32_e32 v48, v1
+; VI-NEXT: v_mov_b32_e32 v48, v0
; VI-NEXT: v_mov_b32_e32 v8, v2
-; VI-NEXT: v_mov_b32_e32 v35, v3
+; VI-NEXT: v_mov_b32_e32 v34, v3
; VI-NEXT: v_mov_b32_e32 v16, v4
; VI-NEXT: v_mov_b32_e32 v49, v5
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v51, v7
+; VI-NEXT: v_mov_b32_e32 v36, v1
+; VI-NEXT: v_lshrrev_b64 v[32:33], 24, v[0:1]
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
@@ -31309,19 +31550,19 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
-; VI-NEXT: v_add_u16_sdwa v36, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v32, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v35, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v50, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v14, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v22, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v18, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v30, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v26, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v48, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
-; VI-NEXT: v_add_u16_e32 v50, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v32
-; VI-NEXT: v_add_u16_e32 v35, 3, v3
+; VI-NEXT: v_add_u16_e32 v36, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
+; VI-NEXT: v_add_u16_e32 v48, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v50
+; VI-NEXT: v_add_u16_e32 v34, 3, v3
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
@@ -31333,9 +31574,9 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
; VI-NEXT: v_add_u16_e32 v24, 3, v6
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v26
-; VI-NEXT: v_or_b32_e32 v1, v48, v1
-; VI-NEXT: v_or_b32_e32 v0, v50, v0
-; VI-NEXT: v_or_b32_e32 v3, v35, v3
+; VI-NEXT: v_or_b32_e32 v1, v36, v1
+; VI-NEXT: v_or_b32_e32 v0, v48, v0
+; VI-NEXT: v_or_b32_e32 v3, v34, v3
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_or_b32_e32 v5, v49, v5
; VI-NEXT: v_or_b32_e32 v4, v16, v4
@@ -31344,7 +31585,7 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
-; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[0:1]
+; VI-NEXT: v_lshrrev_b64 v[32:33], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v5
@@ -31356,18 +31597,18 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; VI-NEXT: v_bfe_u32 v31, v30, 8, 8
; VI-NEXT: v_bfe_u32 v23, v22, 8, 8
; VI-NEXT: v_bfe_u32 v15, v14, 8, 8
-; VI-NEXT: v_bfe_u32 v39, v36, 8, 8
+; VI-NEXT: v_bfe_u32 v39, v35, 8, 8
; VI-NEXT: .LBB96_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v0, v50
+; VI-NEXT: v_mov_b32_e32 v0, v48
; VI-NEXT: v_mov_b32_e32 v1, v38
-; VI-NEXT: v_mov_b32_e32 v2, v32
-; VI-NEXT: v_mov_b32_e32 v3, v33
-; VI-NEXT: v_mov_b32_e32 v4, v48
+; VI-NEXT: v_mov_b32_e32 v2, v50
+; VI-NEXT: v_mov_b32_e32 v3, v32
+; VI-NEXT: v_mov_b32_e32 v4, v36
; VI-NEXT: v_mov_b32_e32 v5, v37
-; VI-NEXT: v_mov_b32_e32 v6, v36
+; VI-NEXT: v_mov_b32_e32 v6, v35
; VI-NEXT: v_mov_b32_e32 v7, v39
-; VI-NEXT: v_mov_b32_e32 v12, v35
+; VI-NEXT: v_mov_b32_e32 v12, v34
; VI-NEXT: v_mov_b32_e32 v20, v49
; VI-NEXT: v_mov_b32_e32 v28, v51
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -32325,271 +32566,289 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v16i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
-; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v35, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v39
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v19
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v34, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v23, v0, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v36, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_or_b32_e32 v34, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v27
-; SI-NEXT: v_or_b32_e32 v9, v36, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v10, v37, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v15, v0, v9
+; SI-NEXT: v_or_b32_e32 v33, v6, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v49, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v38, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v31, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v5, v5, v10
-; SI-NEXT: v_or_b32_e32 v11, v51, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
-; SI-NEXT: v_or_b32_e32 v7, v7, v53
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v11, v0, v11
+; SI-NEXT: v_or_b32_e32 v31, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v35, v0, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v12, v52, v12
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v7, v7, v12
-; SI-NEXT: v_or_b32_e32 v14, v54, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v27
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v13, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v17, v3, v9, 16
-; SI-NEXT: v_alignbit_b32 v25, v7, v14, 16
-; SI-NEXT: v_or_b32_e32 v9, v0, v14
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12
+; SI-NEXT: v_alignbit_b32 v37, v36, v2, 16
+; SI-NEXT: v_alignbit_b32 v39, v34, v3, 16
+; SI-NEXT: v_alignbit_b32 v48, v33, v6, 16
+; SI-NEXT: v_alignbit_b32 v50, v31, v10, 16
+; SI-NEXT: v_or_b32_e32 v32, v0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v11
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: .LBB98_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v1, v55, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v53, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v49, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v51, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v27, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v1, v35, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v19, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x300, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v28
+; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v29
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v21
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v55
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v13, v1, v23, 16
-; SI-NEXT: v_alignbit_b32 v17, v3, v15, 16
-; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v25, v7, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v37, v36, v49, 16
+; SI-NEXT: v_alignbit_b32 v39, v34, v38, 16
+; SI-NEXT: v_alignbit_b32 v48, v33, v35, 16
+; SI-NEXT: v_alignbit_b32 v50, v31, v32, 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v31
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v51
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v17
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v38
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v52
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v35
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v54
; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16i16:
@@ -32768,25 +33027,18 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32i8_to_v16i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v37, v1
-; GFX9-NEXT: v_mov_b32_e32 v36, v0
+; GFX9-NEXT: v_mov_b32_e32 v35, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v38, v7
-; GFX9-NEXT: v_mov_b32_e32 v31, v6
-; GFX9-NEXT: v_mov_b32_e32 v33, v5
-; GFX9-NEXT: v_mov_b32_e32 v34, v4
-; GFX9-NEXT: v_mov_b32_e32 v32, v3
-; GFX9-NEXT: v_mov_b32_e32 v35, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v17
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v19
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
-; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
-; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32
+; GFX9-NEXT: v_mov_b32_e32 v37, v7
+; GFX9-NEXT: v_mov_b32_e32 v36, v6
+; GFX9-NEXT: v_mov_b32_e32 v34, v5
+; GFX9-NEXT: v_mov_b32_e32 v38, v4
+; GFX9-NEXT: v_mov_b32_e32 v33, v3
+; GFX9-NEXT: v_mov_b32_e32 v31, v2
+; GFX9-NEXT: v_mov_b32_e32 v32, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -32796,15 +33048,16 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: s_cbranch_execnz .LBB98_4
; GFX9-NEXT: .LBB98_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB98_3: ; %cmp.false
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v0, v36, v37, s6
-; GFX9-NEXT: v_perm_b32 v1, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v0, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v1, v31, v33, s6
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
-; GFX9-NEXT: v_perm_b32 v1, v34, v33, s6
-; GFX9-NEXT: v_perm_b32 v2, v31, v38, s6
+; GFX9-NEXT: v_perm_b32 v1, v38, v34, s6
+; GFX9-NEXT: v_perm_b32 v2, v36, v37, s6
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s7
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
@@ -32812,26 +33065,33 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v12, v13, s6
; GFX9-NEXT: v_perm_b32 v4, v14, v15, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: v_or_b32_sdwa v4, v16, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v5, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v17
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v4, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v18, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: v_or_b32_sdwa v5, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v5, v22, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v20, v21, s6
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v25
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v6, v24, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v7, v26, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v7, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
@@ -32841,21 +33101,21 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr16
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr19
-; GFX9-NEXT: ; implicit-def: $vgpr25
-; GFX9-NEXT: ; implicit-def: $vgpr23
-; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB98_2
; GFX9-NEXT: .LBB98_4: ; %cmp.true
@@ -32864,26 +33124,33 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
-; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
-; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
-; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
-; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v13
@@ -32901,19 +33168,19 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v33
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v38
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v35
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v32
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v31
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
@@ -32923,9 +33190,9 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v12, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
-; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
-; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
-; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
+; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
+; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
+; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -32933,43 +33200,31 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v25.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v27.h
+; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v48
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
@@ -32977,139 +33232,154 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_4
; GFX11-TRUE16-NEXT: .LBB98_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v21, v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v35, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v15, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v20, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v14, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
+; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v12, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
-; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
-; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v7.l, v7.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v8.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.h
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-TRUE16-NEXT: .LBB98_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v16.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v18.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v8.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v18.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v35.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v28.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v12.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v21.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v15.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v10.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.h, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.l, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.l, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
@@ -33122,22 +33392,15 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v34, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v2 :: v_dual_mov_b32 v33, v0
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v38, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v36, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v32, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v27
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v3 :: v_dual_mov_b32 v31, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -33148,46 +33411,54 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB98_4
; GFX11-FAKE16-NEXT: .LBB98_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v34, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v32, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v38, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v34, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v32, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v3, v39
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v13, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v14, v15, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v3, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v25
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v11, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v10, v13, 0x5040100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v14, v15, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v30
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v39
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
@@ -33197,106 +33468,113 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v27, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v16, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v23, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v25, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v39, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v19, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v36, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v9, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v12, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v8, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v31, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v17, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v33, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v35
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v31
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v38
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v15, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v20, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v14, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v18, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v13, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v14, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v19, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v13, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v14, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v24, v7, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -34788,52 +35066,36 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v16bf16_to_v16f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v7
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v5
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v4
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v3
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v2
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v6
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
@@ -34841,112 +35103,147 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; SI-NEXT: v_alignbit_b32 v11, v1, v17, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v18
-; SI-NEXT: v_alignbit_b32 v12, v11, v0, 16
-; SI-NEXT: v_alignbit_b32 v10, v3, v19, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v26
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v20
-; SI-NEXT: v_alignbit_b32 v13, v10, v0, 16
-; SI-NEXT: v_alignbit_b32 v6, v5, v21, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; SI-NEXT: v_alignbit_b32 v14, v6, v0, 16
-; SI-NEXT: v_alignbit_b32 v8, v7, v25, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v23
-; SI-NEXT: v_alignbit_b32 v15, v8, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v23
-; SI-NEXT: v_alignbit_b32 v0, v0, v31, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v30, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v29, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v28, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v11, v1, v0, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; SI-NEXT: v_alignbit_b32 v12, v11, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v9, v3, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; SI-NEXT: v_alignbit_b32 v13, v9, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v6, v5, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v29
+; SI-NEXT: v_alignbit_b32 v14, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v23
+; SI-NEXT: v_alignbit_b32 v0, v0, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v25
+; SI-NEXT: v_alignbit_b32 v2, v2, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v8, v7, v8, 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v10
+; SI-NEXT: v_alignbit_b32 v4, v4, v16, 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
+; SI-NEXT: v_alignbit_b32 v15, v8, v15, 16
+; SI-NEXT: v_alignbit_b32 v10, v10, v16, 16
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB102_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v29
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v30
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v28
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v25
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_alignbit_b32 v9, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; SI-NEXT: v_alignbit_b32 v10, v6, v1, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v21
; SI-NEXT: v_alignbit_b32 v8, v7, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
; SI-NEXT: v_alignbit_b32 v6, v5, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_alignbit_b32 v10, v3, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17
+; SI-NEXT: v_alignbit_b32 v9, v3, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v11, v1, v11, 16
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_alignbit_b32 v12, v11, v12, 16
-; SI-NEXT: v_alignbit_b32 v13, v10, v13, 16
+; SI-NEXT: v_alignbit_b32 v13, v9, v13, 16
; SI-NEXT: v_alignbit_b32 v14, v6, v14, 16
; SI-NEXT: v_alignbit_b32 v15, v8, v15, 16
; SI-NEXT: .LBB102_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v14
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -34954,17 +35251,14 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v11, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v13
-; SI-NEXT: v_or_b32_e32 v3, v10, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v15
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v0, v0, v12
; SI-NEXT: v_or_b32_e32 v2, v2, v11
-; SI-NEXT: v_or_b32_e32 v4, v4, v10
; SI-NEXT: v_or_b32_e32 v6, v6, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -36680,30 +36974,30 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
; VI-LABEL: bitcast_v16f16_to_v32i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v35, v5
-; VI-NEXT: v_mov_b32_e32 v34, v4
-; VI-NEXT: v_mov_b32_e32 v33, v3
-; VI-NEXT: v_mov_b32_e32 v32, v2
+; VI-NEXT: v_mov_b32_e32 v33, v5
+; VI-NEXT: v_mov_b32_e32 v32, v4
+; VI-NEXT: v_mov_b32_e32 v35, v3
+; VI-NEXT: v_mov_b32_e32 v34, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v35
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v34
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v33
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v32
-; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; VI-NEXT: ; implicit-def: $vgpr38
-; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr36
+; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr13
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr21
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr11
@@ -36714,56 +37008,64 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
; VI-NEXT: s_cbranch_execz .LBB104_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v7
+; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v7
+; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v6
-; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v35
-; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v35
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v34
-; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v33
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v33
-; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v32
-; VI-NEXT: v_lshrrev_b32_e32 v37, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v23, 24, v33
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
+; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v33
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v32
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v32
+; VI-NEXT: v_lshrrev_b32_e32 v15, 24, v35
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v35
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v34
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v34
+; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v0
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[34:35]
-; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[32:33]
+; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[32:33]
+; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[34:35]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v0
; VI-NEXT: .LBB104_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v5, 0x200
-; VI-NEXT: v_add_f16_sdwa v14, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v14, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v36, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
-; VI-NEXT: v_add_f16_sdwa v10, v32, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
+; VI-NEXT: v_add_f16_sdwa v10, v34, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v36
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_or_b32_e32 v12, v33, v8
+; VI-NEXT: v_or_b32_e32 v12, v35, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
-; VI-NEXT: v_add_f16_sdwa v22, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
+; VI-NEXT: v_add_f16_sdwa v22, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v1, v2
; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v11, v32, v8
+; VI-NEXT: v_or_b32_e32 v11, v34, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
-; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
-; VI-NEXT: v_add_f16_sdwa v18, v34, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
+; VI-NEXT: v_add_f16_sdwa v18, v32, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v30, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v26, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
-; VI-NEXT: v_or_b32_e32 v9, v35, v8
+; VI-NEXT: v_or_b32_e32 v9, v33, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
-; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
+; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v30
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_or_b32_e32 v3, v0, v3
-; VI-NEXT: v_or_b32_e32 v8, v34, v8
+; VI-NEXT: v_or_b32_e32 v8, v32, v8
; VI-NEXT: v_or_b32_e32 v16, v7, v13
; VI-NEXT: v_or_b32_e32 v15, v6, v5
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
@@ -36773,7 +37075,7 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v11
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v38, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v3
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v15
@@ -36781,19 +37083,19 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
; VI-NEXT: v_bfe_u32 v31, v30, 8, 8
; VI-NEXT: v_bfe_u32 v23, v22, 8, 8
; VI-NEXT: v_bfe_u32 v15, v14, 8, 8
-; VI-NEXT: v_bfe_u32 v37, v36, 8, 8
+; VI-NEXT: v_bfe_u32 v38, v36, 8, 8
; VI-NEXT: .LBB104_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, v1
-; VI-NEXT: v_mov_b32_e32 v8, v32
-; VI-NEXT: v_mov_b32_e32 v12, v33
-; VI-NEXT: v_mov_b32_e32 v16, v34
-; VI-NEXT: v_mov_b32_e32 v20, v35
+; VI-NEXT: v_mov_b32_e32 v8, v34
+; VI-NEXT: v_mov_b32_e32 v12, v35
+; VI-NEXT: v_mov_b32_e32 v16, v32
+; VI-NEXT: v_mov_b32_e32 v20, v33
; VI-NEXT: v_mov_b32_e32 v24, v6
; VI-NEXT: v_mov_b32_e32 v28, v7
-; VI-NEXT: v_mov_b32_e32 v1, v38
+; VI-NEXT: v_mov_b32_e32 v1, v37
; VI-NEXT: v_mov_b32_e32 v6, v36
-; VI-NEXT: v_mov_b32_e32 v7, v37
+; VI-NEXT: v_mov_b32_e32 v7, v38
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v16f16_to_v32i8:
@@ -37784,271 +38086,289 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v16f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
-; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v35, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v39
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v19
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v34, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v23, v0, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v36, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_or_b32_e32 v34, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v27
-; SI-NEXT: v_or_b32_e32 v9, v36, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v33, v6, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v49, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v10, v37, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v15, v0, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v38, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v31, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v5, v5, v10
-; SI-NEXT: v_or_b32_e32 v11, v51, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
-; SI-NEXT: v_or_b32_e32 v7, v7, v53
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v11, v0, v11
+; SI-NEXT: v_or_b32_e32 v31, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v35, v0, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v12, v52, v12
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v7, v7, v12
-; SI-NEXT: v_or_b32_e32 v14, v54, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v27
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v13, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v17, v3, v9, 16
-; SI-NEXT: v_alignbit_b32 v25, v7, v14, 16
-; SI-NEXT: v_or_b32_e32 v9, v0, v14
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12
+; SI-NEXT: v_alignbit_b32 v37, v36, v2, 16
+; SI-NEXT: v_alignbit_b32 v39, v34, v3, 16
+; SI-NEXT: v_alignbit_b32 v48, v33, v6, 16
+; SI-NEXT: v_alignbit_b32 v50, v31, v10, 16
+; SI-NEXT: v_or_b32_e32 v32, v0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v11
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: .LBB106_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v1, v55, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v53, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v49, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v51, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v27, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v1, v35, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v19, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x300, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v28
+; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v29
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v21
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v55
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v13, v1, v23, 16
-; SI-NEXT: v_alignbit_b32 v17, v3, v15, 16
-; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v25, v7, v9, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v37, v36, v49, 16
+; SI-NEXT: v_alignbit_b32 v39, v34, v38, 16
+; SI-NEXT: v_alignbit_b32 v48, v33, v35, 16
+; SI-NEXT: v_alignbit_b32 v50, v31, v32, 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v31
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v51
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v17
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v38
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v52
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v35
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v54
; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16f16:
@@ -38227,25 +38547,18 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32i8_to_v16f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v37, v1
-; GFX9-NEXT: v_mov_b32_e32 v36, v0
+; GFX9-NEXT: v_mov_b32_e32 v35, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v38, v7
-; GFX9-NEXT: v_mov_b32_e32 v31, v6
-; GFX9-NEXT: v_mov_b32_e32 v33, v5
-; GFX9-NEXT: v_mov_b32_e32 v34, v4
-; GFX9-NEXT: v_mov_b32_e32 v32, v3
-; GFX9-NEXT: v_mov_b32_e32 v35, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v17
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v19
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
-; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
-; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32
+; GFX9-NEXT: v_mov_b32_e32 v37, v7
+; GFX9-NEXT: v_mov_b32_e32 v36, v6
+; GFX9-NEXT: v_mov_b32_e32 v34, v5
+; GFX9-NEXT: v_mov_b32_e32 v38, v4
+; GFX9-NEXT: v_mov_b32_e32 v33, v3
+; GFX9-NEXT: v_mov_b32_e32 v31, v2
+; GFX9-NEXT: v_mov_b32_e32 v32, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -38255,15 +38568,16 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: s_cbranch_execnz .LBB106_4
; GFX9-NEXT: .LBB106_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB106_3: ; %cmp.false
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v0, v36, v37, s6
-; GFX9-NEXT: v_perm_b32 v1, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v0, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v1, v31, v33, s6
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
-; GFX9-NEXT: v_perm_b32 v1, v34, v33, s6
-; GFX9-NEXT: v_perm_b32 v2, v31, v38, s6
+; GFX9-NEXT: v_perm_b32 v1, v38, v34, s6
+; GFX9-NEXT: v_perm_b32 v2, v36, v37, s6
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s7
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
@@ -38271,26 +38585,33 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v12, v13, s6
; GFX9-NEXT: v_perm_b32 v4, v14, v15, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: v_or_b32_sdwa v4, v16, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v5, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v17
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v4, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v18, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: v_or_b32_sdwa v5, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v5, v22, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v20, v21, s6
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v25
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v6, v24, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v7, v26, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v7, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
@@ -38300,21 +38621,21 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr16
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr19
-; GFX9-NEXT: ; implicit-def: $vgpr25
-; GFX9-NEXT: ; implicit-def: $vgpr23
-; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB106_2
; GFX9-NEXT: .LBB106_4: ; %cmp.true
@@ -38323,26 +38644,33 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
-; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
-; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
-; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
-; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v13
@@ -38360,19 +38688,19 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v33
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v38
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v35
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v32
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v31
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
@@ -38382,9 +38710,9 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v12, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
-; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
-; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
-; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
+; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
+; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
+; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -38392,43 +38720,31 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v25.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v27.h
+; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v48
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
@@ -38436,139 +38752,154 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_4
; GFX11-TRUE16-NEXT: .LBB106_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v21, v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v35, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v15, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v20, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v14, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
+; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v12, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
-; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
-; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v7.l, v7.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v8.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.h
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-TRUE16-NEXT: .LBB106_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v16.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v18.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v8.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v18.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v35.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v28.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v12.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v21.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v15.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v10.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.h, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.l, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.l, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
@@ -38581,22 +38912,15 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v34, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v2 :: v_dual_mov_b32 v33, v0
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v38, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v36, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v32, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v27
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v3 :: v_dual_mov_b32 v31, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -38607,46 +38931,54 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB106_4
; GFX11-FAKE16-NEXT: .LBB106_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v34, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v32, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v38, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v34, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v32, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v3, v39
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v13, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v14, v15, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v3, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v25
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v11, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v10, v13, 0x5040100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v14, v15, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v30
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v39
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
@@ -38656,106 +38988,113 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v27, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v16, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v23, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v25, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v39, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v19, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v36, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v9, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v12, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v8, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v31, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v17, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v33, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v35
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v31
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v38
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v15, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v20, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v14, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v18, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v13, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v14, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v19, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v13, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v14, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v24, v7, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -39671,39 +40010,23 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v16bf16_to_v32i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v7
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v6
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v4
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v2
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v16
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v7
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -39746,22 +40069,38 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB108_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v39
-; SI-NEXT: v_alignbit_b32 v8, v5, v48, 16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v33
-; SI-NEXT: v_alignbit_b32 v16, v5, v52, 16
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v49
-; SI-NEXT: v_alignbit_b32 v0, v0, v36, 16
-; SI-NEXT: v_alignbit_b32 v4, v6, v34, 16
-; SI-NEXT: v_alignbit_b32 v12, v14, v38, 16
-; SI-NEXT: v_alignbit_b32 v20, v22, v50, 16
-; SI-NEXT: v_alignbit_b32 v24, v5, v55, 16
-; SI-NEXT: v_alignbit_b32 v28, v30, v53, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v8, v7, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v12, v14, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v16, v7, v15, 16
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v21
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v20, v22, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v32
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_alignbit_b32 v24, v7, v15, 16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v49
+; SI-NEXT: v_alignbit_b32 v4, v6, v1, 16
+; SI-NEXT: v_alignbit_b32 v28, v30, v7, 16
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -39774,77 +40113,93 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) {
; SI-NEXT: v_alignbit_b32 v27, v28, v24, 24
; SI-NEXT: v_alignbit_b32 v26, v28, v24, 16
; SI-NEXT: v_alignbit_b32 v25, v28, v24, 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v32
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v33
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v13
; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v37
+; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v21
; SI-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v49
+; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v29
; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB108_2
; SI-NEXT: .LBB108_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v24, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v53
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
; SI-NEXT: v_alignbit_b32 v28, v30, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v16, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
; SI-NEXT: v_alignbit_b32 v20, v22, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v48
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v8, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v33
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v38
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v15
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
; SI-NEXT: v_alignbit_b32 v12, v14, v0, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v32
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v32
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
@@ -42168,39 +42523,26 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v32i8_to_v16bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32
-; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v29
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v33
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v34
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
@@ -42208,235 +42550,262 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; SI-NEXT: v_or_b32_e32 v3, v1, v0
+; SI-NEXT: v_or_b32_e32 v31, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v5, v31, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_or_b32_e32 v32, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v36
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v11, v32, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_or_b32_e32 v34, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
-; SI-NEXT: v_or_b32_e32 v13, v1, v0
+; SI-NEXT: v_or_b32_e32 v35, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v15, v35, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
+; SI-NEXT: v_or_b32_e32 v36, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v50
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v21, v48, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v15
+; SI-NEXT: v_or_b32_e32 v38, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v17
-; SI-NEXT: v_or_b32_e32 v23, v1, v0
+; SI-NEXT: v_or_b32_e32 v39, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v18
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v27, v49, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v19
+; SI-NEXT: v_or_b32_e32 v48, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v53
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v21
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v22
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v33, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v23
+; SI-NEXT: v_or_b32_e32 v50, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v25
-; SI-NEXT: v_or_b32_e32 v34, v1, v0
+; SI-NEXT: v_or_b32_e32 v51, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v37, v52, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v27
+; SI-NEXT: v_or_b32_e32 v52, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v29
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v39, v54, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v55
+; SI-NEXT: v_or_b32_e32 v54, v1, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v3, v55, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v54, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v25
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v52, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v3, v53, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v51, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v49, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v50, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v48, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v35, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v29, 8, v29
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x300, v28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v55
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; SI-NEXT: v_or_b32_e32 v29, v29, v30
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
+; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
+; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v8
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v12
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v16
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v24
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v28
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v0
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v12
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v16
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v20
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v24
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v28
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v32
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v36
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v35
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v38
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v37
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v27
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v50
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v49
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v52
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v51
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v54
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v38
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v53
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i8_to_v16bf16:
@@ -42615,25 +42984,18 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32i8_to_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v37, v1
-; GFX9-NEXT: v_mov_b32_e32 v36, v0
+; GFX9-NEXT: v_mov_b32_e32 v35, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v38, v7
-; GFX9-NEXT: v_mov_b32_e32 v31, v6
-; GFX9-NEXT: v_mov_b32_e32 v33, v5
-; GFX9-NEXT: v_mov_b32_e32 v34, v4
-; GFX9-NEXT: v_mov_b32_e32 v32, v3
-; GFX9-NEXT: v_mov_b32_e32 v35, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v17
-; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v19
-; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v23
-; GFX9-NEXT: v_lshlrev_b16_e32 v25, 8, v25
-; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v27
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32
+; GFX9-NEXT: v_mov_b32_e32 v37, v7
+; GFX9-NEXT: v_mov_b32_e32 v36, v6
+; GFX9-NEXT: v_mov_b32_e32 v34, v5
+; GFX9-NEXT: v_mov_b32_e32 v38, v4
+; GFX9-NEXT: v_mov_b32_e32 v33, v3
+; GFX9-NEXT: v_mov_b32_e32 v31, v2
+; GFX9-NEXT: v_mov_b32_e32 v32, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v27, 8, v1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -42643,15 +43005,16 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: s_cbranch_execnz .LBB110_4
; GFX9-NEXT: .LBB110_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB110_3: ; %cmp.false
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v0, v36, v37, s6
-; GFX9-NEXT: v_perm_b32 v1, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v0, v35, v32, s6
+; GFX9-NEXT: v_perm_b32 v1, v31, v33, s6
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
-; GFX9-NEXT: v_perm_b32 v1, v34, v33, s6
-; GFX9-NEXT: v_perm_b32 v2, v31, v38, s6
+; GFX9-NEXT: v_perm_b32 v1, v38, v34, s6
+; GFX9-NEXT: v_perm_b32 v2, v36, v37, s6
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s7
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
@@ -42659,26 +43022,33 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v12, v13, s6
; GFX9-NEXT: v_perm_b32 v4, v14, v15, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
-; GFX9-NEXT: v_or_b32_sdwa v4, v16, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v5, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v17
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v4, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v18, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
-; GFX9-NEXT: v_or_b32_sdwa v5, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v5, v22, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v20, v21, s6
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v25
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v6, v24, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v7, v26, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
-; GFX9-NEXT: v_or_b32_sdwa v7, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s7
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr32
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr38
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr8
; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; implicit-def: $vgpr10
@@ -42688,21 +43058,21 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr16
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; implicit-def: $vgpr21
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr39
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr19
-; GFX9-NEXT: ; implicit-def: $vgpr25
-; GFX9-NEXT: ; implicit-def: $vgpr23
-; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB110_2
; GFX9-NEXT: .LBB110_4: ; %cmp.true
@@ -42711,26 +43081,33 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v39
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
-; GFX9-NEXT: v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
-; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
-; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
-; GFX9-NEXT: v_or_b32_sdwa v0, v39, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v19
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v13
@@ -42748,19 +43125,19 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v34
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v33
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v38
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v31
-; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v38
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
-; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v32
; GFX9-NEXT: v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v35
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v32
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v31
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
@@ -42770,9 +43147,9 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v2, v8, v2, s6
; GFX9-NEXT: v_perm_b32 v3, v12, v3, s6
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
-; GFX9-NEXT: v_perm_b32 v5, v19, v5, s6
-; GFX9-NEXT: v_perm_b32 v6, v23, v6, s6
-; GFX9-NEXT: v_perm_b32 v7, v27, v7, s6
+; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
+; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
+; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -42780,43 +43157,31 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v25.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v27.h
+; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.h
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v48
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
@@ -42824,139 +43189,154 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_4
; GFX11-TRUE16-NEXT: .LBB110_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v21, v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v35, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v15, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v20, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v14, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
+; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v12, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
-; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
-; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v7.l, v7.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v8.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.h
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-TRUE16-NEXT: .LBB110_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v16.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v18.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v8.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v18.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v17.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v35.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v28.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v12.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v21.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v15.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v10.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.h, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.l, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.l, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
@@ -42969,22 +43349,15 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16bf16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v34, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v2 :: v_dual_mov_b32 v33, v0
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v38, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v36, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v32, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v27
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v3 :: v_dual_mov_b32 v31, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -42995,46 +43368,54 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB110_4
; GFX11-FAKE16-NEXT: .LBB110_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v34, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v32, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v38, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v34, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v32, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v3, v39
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v13, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v14, v15, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v3, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v25
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v11, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v10, v13, 0x5040100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v14, v15, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v30
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v39
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
@@ -43044,106 +43425,113 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v30, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v27, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v16, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v23, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v25, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v39, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v19, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v36, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v9, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v12, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v8, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v31, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v17, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v33, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v35
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v31
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v38
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v15, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v20, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v14, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v18, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v13, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v8, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v14, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v19, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v13, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v14, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v24, v7, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
index 6656733d53e51..93807c593e7ff 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
@@ -861,25 +861,16 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v15, v2
; SI-NEXT: v_mov_b32_e32 v16, v1
; SI-NEXT: v_mov_b32_e32 v17, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -892,22 +883,31 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v26
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v22
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v26
-; SI-NEXT: v_or_b32_e32 v1, v1, v25
-; SI-NEXT: v_or_b32_e32 v2, v2, v24
-; SI-NEXT: v_or_b32_e32 v3, v3, v23
-; SI-NEXT: v_or_b32_e32 v4, v4, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v21
-; SI-NEXT: v_or_b32_e32 v6, v6, v20
-; SI-NEXT: v_or_b32_e32 v7, v7, v19
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
@@ -918,6 +918,7 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
@@ -926,37 +927,45 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v21
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v26, v0
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v25, v1
-; SI-NEXT: v_or_b32_e32 v2, v24, v2
-; SI-NEXT: v_or_b32_e32 v3, v23, v3
-; SI-NEXT: v_or_b32_e32 v4, v22, v4
-; SI-NEXT: v_or_b32_e32 v5, v21, v5
-; SI-NEXT: v_or_b32_e32 v6, v20, v6
-; SI-NEXT: v_or_b32_e32 v7, v19, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -2620,25 +2629,16 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v15, v2
; SI-NEXT: v_mov_b32_e32 v16, v1
; SI-NEXT: v_mov_b32_e32 v17, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2651,22 +2651,31 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v17
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v26
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v22
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v26
-; SI-NEXT: v_or_b32_e32 v1, v1, v25
-; SI-NEXT: v_or_b32_e32 v2, v2, v24
-; SI-NEXT: v_or_b32_e32 v3, v3, v23
-; SI-NEXT: v_or_b32_e32 v4, v4, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v21
-; SI-NEXT: v_or_b32_e32 v6, v6, v20
-; SI-NEXT: v_or_b32_e32 v7, v7, v19
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
@@ -2677,6 +2686,7 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
@@ -2685,37 +2695,45 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v21
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v26, v0
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v25, v1
-; SI-NEXT: v_or_b32_e32 v2, v24, v2
-; SI-NEXT: v_or_b32_e32 v3, v23, v3
-; SI-NEXT: v_or_b32_e32 v4, v22, v4
-; SI-NEXT: v_or_b32_e32 v5, v21, v5
-; SI-NEXT: v_or_b32_e32 v6, v20, v6
-; SI-NEXT: v_or_b32_e32 v7, v19, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -4017,34 +4035,25 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v10
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr26
@@ -4053,27 +4062,36 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB20_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v11
+; SI-NEXT: v_or_b32_e32 v19, v1, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v19, v1, v29
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v22, v0, v28
+; SI-NEXT: v_or_b32_e32 v17, v3, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; SI-NEXT: v_or_b32_e32 v23, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v17, v1, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v20, v0, v30
+; SI-NEXT: v_or_b32_e32 v16, v5, v9
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; SI-NEXT: v_or_b32_e32 v20, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v15, v1, v33
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v18, v0, v32
+; SI-NEXT: v_or_b32_e32 v9, v7, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v18, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v9, v1, v35
-; SI-NEXT: v_or_b32_e32 v14, v0, v34
+; SI-NEXT: v_alignbit_b32 v21, v19, v1, 16
+; SI-NEXT: v_or_b32_e32 v15, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_alignbit_b32 v21, v19, v28, 16
-; SI-NEXT: v_alignbit_b32 v23, v17, v30, 16
-; SI-NEXT: v_alignbit_b32 v24, v15, v32, 16
-; SI-NEXT: v_alignbit_b32 v25, v9, v34, 16
-; SI-NEXT: v_or_b32_e32 v26, v0, v27
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_alignbit_b32 v22, v17, v3, 16
+; SI-NEXT: v_alignbit_b32 v24, v16, v5, 16
+; SI-NEXT: v_alignbit_b32 v25, v9, v7, 16
+; SI-NEXT: v_or_b32_e32 v26, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -4083,90 +4101,94 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: .LBB20_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v28, v0
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v6, v34, v6
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v2, v30, v2
-; SI-NEXT: v_or_b32_e32 v0, v29, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v30
+; SI-NEXT: v_or_b32_e32 v6, v9, v6
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v29
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v13
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v28
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v6, v35, v6
-; SI-NEXT: v_or_b32_e32 v4, v33, v4
-; SI-NEXT: v_or_b32_e32 v2, v31, v2
-; SI-NEXT: v_or_b32_e32 v0, v27, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v21, v19, v22, 16
-; SI-NEXT: v_alignbit_b32 v23, v17, v20, 16
-; SI-NEXT: v_alignbit_b32 v24, v15, v18, 16
-; SI-NEXT: v_alignbit_b32 v25, v9, v14, 16
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; SI-NEXT: v_alignbit_b32 v21, v19, v23, 16
+; SI-NEXT: v_alignbit_b32 v22, v17, v20, 16
+; SI-NEXT: v_alignbit_b32 v24, v16, v18, 16
+; SI-NEXT: v_alignbit_b32 v25, v9, v15, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
; SI-NEXT: .LBB20_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v12
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v14
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v25
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v26
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index 9ae6700ac1825..f9c9967516842 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -915,27 +915,17 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v17, v2
; SI-NEXT: v_mov_b32_e32 v18, v1
; SI-NEXT: v_mov_b32_e32 v19, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -948,24 +938,34 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v27
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v24
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v23
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v22
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v29
-; SI-NEXT: v_or_b32_e32 v1, v1, v28
-; SI-NEXT: v_or_b32_e32 v2, v2, v27
-; SI-NEXT: v_or_b32_e32 v3, v3, v26
-; SI-NEXT: v_or_b32_e32 v4, v4, v25
-; SI-NEXT: v_or_b32_e32 v5, v5, v24
-; SI-NEXT: v_or_b32_e32 v6, v6, v23
-; SI-NEXT: v_or_b32_e32 v7, v7, v22
-; SI-NEXT: v_or_b32_e32 v8, v8, v21
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
@@ -977,6 +977,7 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -986,40 +987,49 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v27
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v24
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v23
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v22
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v29, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v28, v1
-; SI-NEXT: v_or_b32_e32 v2, v27, v2
-; SI-NEXT: v_or_b32_e32 v3, v26, v3
-; SI-NEXT: v_or_b32_e32 v4, v25, v4
-; SI-NEXT: v_or_b32_e32 v5, v24, v5
-; SI-NEXT: v_or_b32_e32 v6, v23, v6
-; SI-NEXT: v_or_b32_e32 v7, v22, v7
-; SI-NEXT: v_or_b32_e32 v8, v21, v8
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -4053,154 +4063,161 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v40i8_to_v10i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v35, v8
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v48, v0
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v29
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v0
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v31, v9
+; SI-NEXT: v_mov_b32_e32 v32, v8
+; SI-NEXT: v_mov_b32_e32 v33, v7
+; SI-NEXT: v_mov_b32_e32 v34, v6
+; SI-NEXT: v_mov_b32_e32 v35, v5
+; SI-NEXT: v_mov_b32_e32 v36, v4
+; SI-NEXT: v_mov_b32_e32 v37, v3
+; SI-NEXT: v_mov_b32_e32 v38, v2
+; SI-NEXT: v_mov_b32_e32 v39, v1
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v4
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v44
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v43
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v37
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v35
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v41
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v33
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v31
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v55
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v53
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v52, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v49
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v48, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v25
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v23, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v21
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v19, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v39
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v38
-; SI-NEXT: v_or_b32_e32 v8, v8, v17
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v55
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v54
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v15, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v37
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v36
-; SI-NEXT: v_or_b32_e32 v9, v9, v13
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v51
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v50
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v49
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -4208,120 +4225,131 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: .LBB14_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v43, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v35
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v55, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v31
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v53, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v52, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v49, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v48, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v25, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v23, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v21, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v19, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v39
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v38
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v54
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v53
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v15, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v37
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v36
-; SI-NEXT: v_or_b32_e32 v9, v13, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v51
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x300, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -4336,11 +4364,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7523,27 +7548,17 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v17, v2
; SI-NEXT: v_mov_b32_e32 v18, v1
; SI-NEXT: v_mov_b32_e32 v19, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -7556,24 +7571,34 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v27
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v24
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v23
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v22
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v29
-; SI-NEXT: v_or_b32_e32 v1, v1, v28
-; SI-NEXT: v_or_b32_e32 v2, v2, v27
-; SI-NEXT: v_or_b32_e32 v3, v3, v26
-; SI-NEXT: v_or_b32_e32 v4, v4, v25
-; SI-NEXT: v_or_b32_e32 v5, v5, v24
-; SI-NEXT: v_or_b32_e32 v6, v6, v23
-; SI-NEXT: v_or_b32_e32 v7, v7, v22
-; SI-NEXT: v_or_b32_e32 v8, v8, v21
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr18
@@ -7585,6 +7610,7 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -7594,40 +7620,49 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v27
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v24
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v23
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v11
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v22
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v29, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v28, v1
-; SI-NEXT: v_or_b32_e32 v2, v27, v2
-; SI-NEXT: v_or_b32_e32 v3, v26, v3
-; SI-NEXT: v_or_b32_e32 v4, v25, v4
-; SI-NEXT: v_or_b32_e32 v5, v24, v5
-; SI-NEXT: v_or_b32_e32 v6, v23, v6
-; SI-NEXT: v_or_b32_e32 v7, v22, v7
-; SI-NEXT: v_or_b32_e32 v8, v21, v8
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -10773,154 +10808,161 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v40i8_to_v10f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v35, v8
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v48, v0
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v29
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v0
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v31, v9
+; SI-NEXT: v_mov_b32_e32 v32, v8
+; SI-NEXT: v_mov_b32_e32 v33, v7
+; SI-NEXT: v_mov_b32_e32 v34, v6
+; SI-NEXT: v_mov_b32_e32 v35, v5
+; SI-NEXT: v_mov_b32_e32 v36, v4
+; SI-NEXT: v_mov_b32_e32 v37, v3
+; SI-NEXT: v_mov_b32_e32 v38, v2
+; SI-NEXT: v_mov_b32_e32 v39, v1
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v4
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v44
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v43
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v37
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v35
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v41
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v33
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v31
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v55
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v3, v3, v53
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v15
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v52, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v49
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v48, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v25
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v23, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v21
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v19, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v39
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v38
-; SI-NEXT: v_or_b32_e32 v8, v8, v17
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v55
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v54
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v15, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v37
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v36
-; SI-NEXT: v_or_b32_e32 v9, v9, v13
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v51
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v50
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v49
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -10928,120 +10970,131 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: .LBB34_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v43, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v39
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v35
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v55, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v31
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v54, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v3, v53, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v52, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v49, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v48, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v25, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v23, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v21, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v19, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v39
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v38
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v54
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v53
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v15, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v37
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v36
-; SI-NEXT: v_or_b32_e32 v9, v13, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v51
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x300, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -11056,11 +11109,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -13870,71 +13920,71 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v20i16_to_v20f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v6
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v14
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v22, v1, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; SI-NEXT: v_or_b32_e32 v21, v1, v10
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v30
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v20, v1, v33
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v29, v0, v30
+; SI-NEXT: v_or_b32_e32 v20, v3, v10
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v13
+; SI-NEXT: v_or_b32_e32 v28, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v17, v1, v35
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v24, v0, v32
+; SI-NEXT: v_or_b32_e32 v18, v5, v10
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; SI-NEXT: v_or_b32_e32 v25, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v14, v1, v37
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v21, v0, v34
+; SI-NEXT: v_or_b32_e32 v16, v7, v10
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v15
+; SI-NEXT: v_or_b32_e32 v22, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v10, v1, v39
-; SI-NEXT: v_or_b32_e32 v19, v0, v36
+; SI-NEXT: v_or_b32_e32 v10, v9, v10
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v34
+; SI-NEXT: v_or_b32_e32 v19, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_alignbit_b32 v23, v22, v30, 16
-; SI-NEXT: v_alignbit_b32 v25, v20, v32, 16
-; SI-NEXT: v_alignbit_b32 v26, v17, v34, 16
-; SI-NEXT: v_alignbit_b32 v27, v14, v36, 16
-; SI-NEXT: v_alignbit_b32 v28, v10, v38, 16
-; SI-NEXT: v_or_b32_e32 v15, v0, v38
+; SI-NEXT: v_alignbit_b32 v23, v21, v1, 16
+; SI-NEXT: v_alignbit_b32 v24, v20, v3, 16
+; SI-NEXT: v_alignbit_b32 v26, v18, v5, 16
+; SI-NEXT: v_alignbit_b32 v27, v16, v7, 16
+; SI-NEXT: v_alignbit_b32 v29, v10, v9, 16
+; SI-NEXT: v_or_b32_e32 v17, v0, v9
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -13945,102 +13995,107 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: .LBB44_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v8, v38, v8
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v6, v36, v6
-; SI-NEXT: v_or_b32_e32 v4, v34, v4
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v0, v30, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v15
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v33
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v13
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_or_b32_e32 v4, v35, v4
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_or_b32_e32 v0, v31, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v31
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v23, v22, v29, 16
-; SI-NEXT: v_alignbit_b32 v25, v20, v24, 16
-; SI-NEXT: v_alignbit_b32 v26, v17, v21, 16
-; SI-NEXT: v_alignbit_b32 v27, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v28, v10, v15, 16
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v23, v21, v28, 16
+; SI-NEXT: v_alignbit_b32 v24, v20, v25, 16
+; SI-NEXT: v_alignbit_b32 v26, v18, v22, 16
+; SI-NEXT: v_alignbit_b32 v27, v16, v19, 16
+; SI-NEXT: v_alignbit_b32 v29, v10, v17, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v10
; SI-NEXT: .LBB44_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v28
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v21
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v17
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v13
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v28
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v29
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v15
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -15080,128 +15135,120 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v20i16_to_v40i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v9
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v24
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v19
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v12
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB48_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v30, v1, v44
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v43
+; SI-NEXT: v_or_b32_e32 v24, v1, v11
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v31, v1, v43
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v26, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v22, v1, v46
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v22, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v21, v1, v45
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; SI-NEXT: v_or_b32_e32 v23, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v20, v1, v56
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v45
+; SI-NEXT: v_or_b32_e32 v20, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v18, v1, v47
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_or_b32_e32 v21, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v17, v1, v58
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v18, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v16, v1, v57
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_or_b32_e32 v19, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v14, v1, v60
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v47
+; SI-NEXT: v_or_b32_e32 v11, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v11, v1, v59
-; SI-NEXT: v_alignbit_b32 v35, v31, v30, 24
-; SI-NEXT: v_alignbit_b32 v38, v31, v30, 16
-; SI-NEXT: v_alignbit_b32 v50, v31, v30, 8
-; SI-NEXT: v_alignbit_b32 v34, v21, v22, 24
-; SI-NEXT: v_alignbit_b32 v36, v21, v22, 16
-; SI-NEXT: v_alignbit_b32 v39, v21, v22, 8
-; SI-NEXT: v_alignbit_b32 v29, v18, v20, 24
-; SI-NEXT: v_alignbit_b32 v32, v18, v20, 16
-; SI-NEXT: v_alignbit_b32 v37, v18, v20, 8
-; SI-NEXT: v_alignbit_b32 v26, v16, v17, 24
-; SI-NEXT: v_alignbit_b32 v27, v16, v17, 16
-; SI-NEXT: v_alignbit_b32 v33, v16, v17, 8
-; SI-NEXT: v_alignbit_b32 v23, v11, v14, 24
-; SI-NEXT: v_alignbit_b32 v25, v11, v14, 16
-; SI-NEXT: v_alignbit_b32 v28, v11, v14, 8
-; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v31
-; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v18
-; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v16
-; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; SI-NEXT: v_bfe_u32 v42, v24, 8, 8
-; SI-NEXT: v_bfe_u32 v40, v19, 8, 8
-; SI-NEXT: v_bfe_u32 v54, v15, 8, 8
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; SI-NEXT: v_or_b32_e32 v16, v1, v2
+; SI-NEXT: v_alignbit_b32 v32, v26, v24, 24
+; SI-NEXT: v_alignbit_b32 v37, v26, v24, 16
+; SI-NEXT: v_alignbit_b32 v48, v26, v24, 8
+; SI-NEXT: v_alignbit_b32 v31, v23, v22, 24
+; SI-NEXT: v_alignbit_b32 v35, v23, v22, 16
+; SI-NEXT: v_alignbit_b32 v39, v23, v22, 8
+; SI-NEXT: v_alignbit_b32 v29, v21, v20, 24
+; SI-NEXT: v_alignbit_b32 v33, v21, v20, 16
+; SI-NEXT: v_alignbit_b32 v38, v21, v20, 8
+; SI-NEXT: v_alignbit_b32 v27, v19, v18, 24
+; SI-NEXT: v_alignbit_b32 v30, v19, v18, 16
+; SI-NEXT: v_alignbit_b32 v36, v19, v18, 8
+; SI-NEXT: v_alignbit_b32 v25, v16, v11, 24
+; SI-NEXT: v_alignbit_b32 v28, v16, v11, 16
+; SI-NEXT: v_alignbit_b32 v34, v16, v11, 8
+; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v26
+; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v23
+; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v21
+; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v19
+; SI-NEXT: v_lshrrev_b32_e32 v49, 8, v16
+; SI-NEXT: v_bfe_u32 v42, v17, 8, 8
+; SI-NEXT: v_bfe_u32 v40, v15, 8, 8
+; SI-NEXT: v_bfe_u32 v54, v14, 8, 8
; SI-NEXT: v_bfe_u32 v52, v13, 8, 8
-; SI-NEXT: v_bfe_u32 v49, v12, 8, 8
+; SI-NEXT: v_bfe_u32 v50, v12, 8, 8
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
@@ -15212,108 +15259,113 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: .LBB48_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB48_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v9, v60, v9
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v7, v58, v7
-; SI-NEXT: v_or_b32_e32 v5, v56, v5
-; SI-NEXT: v_or_b32_e32 v3, v46, v3
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v12
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v9
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v46
+; SI-NEXT: v_or_b32_e32 v7, v9, v7
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v13
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v7
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v14
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v44
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v9, v59, v9
-; SI-NEXT: v_or_b32_e32 v7, v57, v7
-; SI-NEXT: v_or_b32_e32 v5, v47, v5
-; SI-NEXT: v_or_b32_e32 v3, v45, v3
-; SI-NEXT: v_or_b32_e32 v1, v43, v1
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v1
-; SI-NEXT: v_alignbit_b32 v35, v31, v30, 24
-; SI-NEXT: v_alignbit_b32 v38, v31, v30, 16
-; SI-NEXT: v_alignbit_b32 v50, v31, v30, 8
-; SI-NEXT: v_alignbit_b32 v34, v21, v22, 24
-; SI-NEXT: v_alignbit_b32 v36, v21, v22, 16
-; SI-NEXT: v_alignbit_b32 v39, v21, v22, 8
-; SI-NEXT: v_alignbit_b32 v29, v18, v20, 24
-; SI-NEXT: v_alignbit_b32 v32, v18, v20, 16
-; SI-NEXT: v_alignbit_b32 v37, v18, v20, 8
-; SI-NEXT: v_alignbit_b32 v26, v16, v17, 24
-; SI-NEXT: v_alignbit_b32 v27, v16, v17, 16
-; SI-NEXT: v_alignbit_b32 v33, v16, v17, 8
-; SI-NEXT: v_alignbit_b32 v23, v11, v14, 24
-; SI-NEXT: v_alignbit_b32 v25, v11, v14, 16
-; SI-NEXT: v_alignbit_b32 v28, v11, v14, 8
-; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v31
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v31
-; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v21
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v54, 24, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v18
-; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v11
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v11
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v1
+; SI-NEXT: v_alignbit_b32 v32, v26, v24, 24
+; SI-NEXT: v_alignbit_b32 v37, v26, v24, 16
+; SI-NEXT: v_alignbit_b32 v48, v26, v24, 8
+; SI-NEXT: v_alignbit_b32 v31, v23, v22, 24
+; SI-NEXT: v_alignbit_b32 v35, v23, v22, 16
+; SI-NEXT: v_alignbit_b32 v39, v23, v22, 8
+; SI-NEXT: v_alignbit_b32 v29, v21, v20, 24
+; SI-NEXT: v_alignbit_b32 v33, v21, v20, 16
+; SI-NEXT: v_alignbit_b32 v38, v21, v20, 8
+; SI-NEXT: v_alignbit_b32 v27, v19, v18, 24
+; SI-NEXT: v_alignbit_b32 v30, v19, v18, 16
+; SI-NEXT: v_alignbit_b32 v36, v19, v18, 8
+; SI-NEXT: v_alignbit_b32 v25, v16, v11, 24
+; SI-NEXT: v_alignbit_b32 v28, v16, v11, 16
+; SI-NEXT: v_alignbit_b32 v34, v16, v11, 8
+; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v26
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v26
+; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v23
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v23
+; SI-NEXT: v_lshrrev_b32_e32 v54, 24, v21
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v21
+; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v19
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v19
+; SI-NEXT: v_lshrrev_b32_e32 v50, 24, v16
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 8, v16
; SI-NEXT: .LBB48_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v50
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v37
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v41
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v42
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -15325,19 +15377,19 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v39
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v34
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v31
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v55
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v19
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v40
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -15347,9 +15399,9 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v38
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v29
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -15358,10 +15410,10 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v53
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v14
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v54
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -15370,19 +15422,19 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v33
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v36
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v26
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v51
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v13
@@ -15394,42 +15446,37 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v28
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v25
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v25
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v12
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v50
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -15437,50 +15484,50 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr55
+; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr15
-; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr53
+; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr41
-; VI-NEXT: ; implicit-def: $vgpr38
-; VI-NEXT: ; implicit-def: $vgpr50
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr49
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: ; implicit-def: $vgpr52
+; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr51
+; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr36
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr13
-; VI-NEXT: ; implicit-def: $vgpr49
-; VI-NEXT: ; implicit-def: $vgpr34
-; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr50
+; VI-NEXT: ; implicit-def: $vgpr35
+; VI-NEXT: ; implicit-def: $vgpr19
+; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr31
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: ; implicit-def: $vgpr29
-; VI-NEXT: ; implicit-def: $vgpr35
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: ; implicit-def: $vgpr42
-; VI-NEXT: ; implicit-def: $vgpr27
-; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_2
@@ -15489,28 +15536,38 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
-; VI-NEXT: v_lshrrev_b32_e32 v30, 24, v10
-; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v29, 24, v10
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v9
-; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v8
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v32, 24, v8
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v30, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v7
-; VI-NEXT: v_lshrrev_b32_e32 v39, 24, v6
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v6
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v5
-; VI-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v3
; VI-NEXT: v_lshrrev_b32_e32 v41, 24, v2
+; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v1
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT: v_mov_b32_e32 v33, v1
-; VI-NEXT: v_mov_b32_e32 v32, v2
-; VI-NEXT: v_mov_b32_e32 v38, v3
+; VI-NEXT: v_mov_b32_e32 v34, v1
+; VI-NEXT: v_mov_b32_e32 v33, v2
+; VI-NEXT: v_mov_b32_e32 v39, v3
; VI-NEXT: v_mov_b32_e32 v37, v4
-; VI-NEXT: v_mov_b32_e32 v51, v5
-; VI-NEXT: v_mov_b32_e32 v49, v6
+; VI-NEXT: v_mov_b32_e32 v52, v5
+; VI-NEXT: v_mov_b32_e32 v50, v6
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v54, v8
; VI-NEXT: v_mov_b32_e32 v43, v9
@@ -15542,83 +15599,83 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v10, v42, v10
; VI-NEXT: v_or_b32_e32 v9, v43, v9
; VI-NEXT: v_add_u16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v27, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v49, 3, v6
+; VI-NEXT: v_add_u16_sdwa v26, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v50, 3, v6
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
-; VI-NEXT: v_add_u16_e32 v51, 3, v5
+; VI-NEXT: v_add_u16_e32 v52, 3, v5
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
; VI-NEXT: v_or_b32_e32 v8, v54, v8
; VI-NEXT: v_or_b32_e32 v7, v40, v7
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT: v_add_u16_e32 v37, 3, v4
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
-; VI-NEXT: v_add_u16_e32 v38, 3, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
-; VI-NEXT: v_or_b32_e32 v6, v49, v6
-; VI-NEXT: v_or_b32_e32 v5, v51, v5
+; VI-NEXT: v_add_u16_e32 v39, 3, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v26
+; VI-NEXT: v_or_b32_e32 v6, v50, v6
+; VI-NEXT: v_or_b32_e32 v5, v52, v5
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[7:8]
-; VI-NEXT: v_add_u16_e32 v32, 3, v2
+; VI-NEXT: v_add_u16_e32 v33, 3, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
-; VI-NEXT: v_add_u16_e32 v33, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_add_u16_e32 v34, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
; VI-NEXT: v_or_b32_e32 v4, v37, v4
-; VI-NEXT: v_or_b32_e32 v3, v38, v3
+; VI-NEXT: v_or_b32_e32 v3, v39, v3
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT: v_or_b32_e32 v2, v32, v2
-; VI-NEXT: v_or_b32_e32 v1, v33, v1
+; VI-NEXT: v_or_b32_e32 v2, v33, v2
+; VI-NEXT: v_or_b32_e32 v1, v34, v1
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v25, 8, v10
; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v9
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v30, 8, v8
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v7
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v6
; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v5
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v1
-; VI-NEXT: v_bfe_u32 v30, v17, 8, 8
-; VI-NEXT: v_bfe_u32 v35, v18, 8, 8
-; VI-NEXT: v_bfe_u32 v39, v19, 8, 8
-; VI-NEXT: v_bfe_u32 v52, v21, 8, 8
+; VI-NEXT: v_bfe_u32 v29, v17, 8, 8
+; VI-NEXT: v_bfe_u32 v32, v18, 8, 8
+; VI-NEXT: v_bfe_u32 v38, v19, 8, 8
+; VI-NEXT: v_bfe_u32 v51, v21, 8, 8
; VI-NEXT: v_bfe_u32 v41, v23, 8, 8
; VI-NEXT: .LBB48_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v2, v26, v15, s4
-; VI-NEXT: v_perm_b32 v1, v33, v55, s4
+; VI-NEXT: v_perm_b32 v2, v27, v15, s4
+; VI-NEXT: v_perm_b32 v1, v34, v55, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_perm_b32 v2, v23, v41, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v32, v53, s4
+; VI-NEXT: v_perm_b32 v1, v33, v53, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v14, s4
-; VI-NEXT: v_perm_b32 v1, v38, v50, s4
+; VI-NEXT: v_perm_b32 v2, v26, v14, s4
+; VI-NEXT: v_perm_b32 v1, v39, v49, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v21, v52, s4
+; VI-NEXT: v_perm_b32 v2, v21, v51, s4
; VI-NEXT: v_perm_b32 v1, v37, v48, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v24, v13, s4
-; VI-NEXT: v_perm_b32 v1, v51, v36, s4
+; VI-NEXT: v_perm_b32 v1, v52, v36, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v19, v39, s4
-; VI-NEXT: v_perm_b32 v1, v49, v34, s4
+; VI-NEXT: v_perm_b32 v2, v19, v38, s4
+; VI-NEXT: v_perm_b32 v1, v50, v35, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
@@ -15629,8 +15686,8 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v35, s4
-; VI-NEXT: v_perm_b32 v1, v54, v29, s4
+; VI-NEXT: v_perm_b32 v2, v18, v32, s4
+; VI-NEXT: v_perm_b32 v1, v54, v30, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
@@ -15641,8 +15698,8 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v17, v30, s4
-; VI-NEXT: v_perm_b32 v1, v42, v27, s4
+; VI-NEXT: v_perm_b32 v2, v17, v29, s4
+; VI-NEXT: v_perm_b32 v1, v42, v25, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
@@ -17098,347 +17155,342 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v37, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v38, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v19
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v29
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v25
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: s_waitcnt vmcnt(9) expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v35
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v53
-; SI-NEXT: s_waitcnt vmcnt(7) expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v54
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v55
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:4
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v40
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 8, v41
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v36, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v29, v0, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v34
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v37, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_or_b32_e32 v36, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v10, v38, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v23
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
+; SI-NEXT: v_or_b32_e32 v34, v6, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v18
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v31, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v39, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v21, v0, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v52, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v54
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v32, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v49, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v18, v56, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v48
-; SI-NEXT: v_or_b32_e32 v11, v52, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v27
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v57
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
-; SI-NEXT: v_or_b32_e32 v7, v7, v45
-; SI-NEXT: v_or_b32_e32 v14, v47, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v20, v59, v15
-; SI-NEXT: v_or_b32_e32 v15, v0, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
+; SI-NEXT: v_or_b32_e32 v39, v0, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
-; SI-NEXT: v_or_b32_e32 v7, v7, v14
-; SI-NEXT: v_or_b32_e32 v13, v46, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v5, v5, v51
-; SI-NEXT: v_alignbit_b32 v27, v7, v13, 16
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v13, v0, v13
+; SI-NEXT: v_or_b32_e32 v31, v12, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
+; SI-NEXT: v_or_b32_e32 v35, v0, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v0, v57
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v5, v5, v12
-; SI-NEXT: v_or_b32_e32 v9, v9, v18
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v44
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v56
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v17, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v19, v3, v10, 16
-; SI-NEXT: v_alignbit_b32 v25, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v35, v9, v20, 16
-; SI-NEXT: v_or_b32_e32 v11, v0, v20
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v18
+; SI-NEXT: v_alignbit_b32 v38, v37, v2, 16
+; SI-NEXT: v_alignbit_b32 v48, v36, v3, 16
+; SI-NEXT: v_alignbit_b32 v50, v34, v6, 16
+; SI-NEXT: v_alignbit_b32 v51, v32, v10, 16
+; SI-NEXT: v_alignbit_b32 v53, v31, v12, 16
+; SI-NEXT: v_or_b32_e32 v33, v0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v13
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: .LBB50_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v43
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v59, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v50
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v46, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v1, v45, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v47, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v1, v37, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v44
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v56
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v31
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v59
+; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v28
+; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v52, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v57
+; SI-NEXT: v_add_i32_e32 v34, vcc, 3, v47
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v29
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v21
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_and_b32_e32 v34, 0xff, v34
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v32, v32, v34
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v17, v1, v29, 16
-; SI-NEXT: v_alignbit_b32 v19, v3, v21, 16
-; SI-NEXT: v_alignbit_b32 v25, v5, v15, 16
-; SI-NEXT: v_alignbit_b32 v27, v7, v13, 16
-; SI-NEXT: v_alignbit_b32 v35, v9, v11, 16
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v9
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v38, v37, v52, 16
+; SI-NEXT: v_alignbit_b32 v48, v36, v49, 16
+; SI-NEXT: v_alignbit_b32 v50, v34, v39, 16
+; SI-NEXT: v_alignbit_b32 v51, v32, v35, 16
+; SI-NEXT: v_alignbit_b32 v53, v31, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v31
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v53
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v19
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v55
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v27
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v40
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v43
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
@@ -17451,7 +17503,31 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v38
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v50
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v35
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v51
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v32
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v53
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -17704,22 +17780,19 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v36, v3
-; GFX9-NEXT: v_mov_b32_e32 v34, v2
-; GFX9-NEXT: v_mov_b32_e32 v31, v1
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v38, v0
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:4
; GFX9-NEXT: v_mov_b32_e32 v39, v15
; GFX9-NEXT: v_mov_b32_e32 v53, v14
; GFX9-NEXT: v_mov_b32_e32 v52, v13
@@ -17732,14 +17805,11 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: v_mov_b32_e32 v48, v6
; GFX9-NEXT: v_mov_b32_e32 v37, v5
; GFX9-NEXT: v_mov_b32_e32 v51, v4
+; GFX9-NEXT: v_mov_b32_e32 v36, v3
+; GFX9-NEXT: v_mov_b32_e32 v34, v2
+; GFX9-NEXT: v_mov_b32_e32 v31, v1
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b16_e32 v47, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v46, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -17771,12 +17841,16 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v45
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v41
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v8, v42, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v9, v40, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v8, v44, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v40, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v44, v43, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v10, v47, v46, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr31
@@ -17810,31 +17884,35 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr55
-; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr44
-; GFX9-NEXT: ; implicit-def: $vgpr43
-; GFX9-NEXT: ; implicit-def: $vgpr41
-; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr42
+; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: .LBB50_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB50_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v41
-; GFX9-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT: v_or_b32_sdwa v0, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
@@ -17928,56 +18006,51 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v27.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v20.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v33.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v34.h
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v70
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v69
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
@@ -17988,180 +18061,185 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v24, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v51, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v29, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v24, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v27, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v68, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v26, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v33.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v53, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v8.l, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v34, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v67, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v8.h, v9.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v30, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v48, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v49, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v54, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v16.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v35, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v11.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v33.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v64.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v16.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v16.h, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v52.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v53.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v67.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v48.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v54.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v53.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v51.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v50.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v28.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v26.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v36.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v49.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v38.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v29.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v23.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v16.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v20.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v18.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v11.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.h, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v12.l, v10.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v10.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v10.h
@@ -18171,33 +18249,27 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v35, v2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_b32 v1, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v31, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v39, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(9)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v66, 8, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v2
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v64, 8, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -18213,9 +18285,9 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v48, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v35, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v52, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
@@ -18227,35 +18299,38 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v67
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v70
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v69
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v66
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v30, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v65
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v64
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v66
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v67, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v8, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v12, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
@@ -18279,90 +18354,92 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v69, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v69, 3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v71, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v66
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v70
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v68, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v65, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v66, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v64, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v20, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v13, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v32, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v54, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v53
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v52
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v50
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v16, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v49, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v17, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v13, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v13, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v53, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v37, 3
@@ -18387,8 +18464,8 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v16, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
@@ -19538,27 +19615,17 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v23, v2
; SI-NEXT: v_mov_b32_e32 v24, v1
; SI-NEXT: v_mov_b32_e32 v25, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v25
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -19571,25 +19638,35 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB52_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v25
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v30
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v29
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: v_or_b32_e32 v2, v2, v33
-; SI-NEXT: v_or_b32_e32 v3, v3, v32
-; SI-NEXT: v_or_b32_e32 v4, v4, v31
-; SI-NEXT: v_or_b32_e32 v5, v5, v30
-; SI-NEXT: v_or_b32_e32 v6, v6, v29
-; SI-NEXT: v_or_b32_e32 v7, v7, v28
-; SI-NEXT: v_or_b32_e32 v8, v8, v27
-; SI-NEXT: v_or_b32_e32 v9, v9, v26
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -19614,36 +19691,46 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB52_2
; SI-NEXT: .LBB52_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v34
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v30
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v29
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_or_b32_e32 v3, v32, v3
-; SI-NEXT: v_or_b32_e32 v4, v31, v4
-; SI-NEXT: v_or_b32_e32 v5, v30, v5
-; SI-NEXT: v_or_b32_e32 v6, v29, v6
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: v_or_b32_e32 v8, v27, v8
-; SI-NEXT: v_or_b32_e32 v9, v26, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -20457,27 +20544,17 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v23, v2
; SI-NEXT: v_mov_b32_e32 v24, v1
; SI-NEXT: v_mov_b32_e32 v25, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v25
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -20490,25 +20567,35 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB56_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v25
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v30
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v29
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: v_or_b32_e32 v2, v2, v33
-; SI-NEXT: v_or_b32_e32 v3, v3, v32
-; SI-NEXT: v_or_b32_e32 v4, v4, v31
-; SI-NEXT: v_or_b32_e32 v5, v5, v30
-; SI-NEXT: v_or_b32_e32 v6, v6, v29
-; SI-NEXT: v_or_b32_e32 v7, v7, v28
-; SI-NEXT: v_or_b32_e32 v8, v8, v27
-; SI-NEXT: v_or_b32_e32 v9, v9, v26
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -20533,36 +20620,46 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: .LBB56_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v34
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v30
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v29
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_or_b32_e32 v3, v32, v3
-; SI-NEXT: v_or_b32_e32 v4, v31, v4
-; SI-NEXT: v_or_b32_e32 v5, v30, v5
-; SI-NEXT: v_or_b32_e32 v6, v29, v6
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: v_or_b32_e32 v8, v27, v8
-; SI-NEXT: v_or_b32_e32 v9, v26, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -21749,35 +21846,35 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; VI-NEXT: ; implicit-def: $vgpr16
+; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr36
+; VI-NEXT: ; implicit-def: $vgpr21
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr13
-; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr31
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr12
-; VI-NEXT: ; implicit-def: $vgpr29
-; VI-NEXT: ; implicit-def: $vgpr33
-; VI-NEXT: ; implicit-def: $vgpr28
-; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -21788,20 +21885,30 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v30, 24, v10
-; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v29, 24, v10
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
+; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v9
-; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v8
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v32, 24, v8
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v30, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v6
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v5
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v3
; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v2
+; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; VI-NEXT: .LBB60_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
@@ -21811,9 +21918,9 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_add_f16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v23
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT: v_add_f16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v27, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v39, v2, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v38, v1, v12
@@ -21828,50 +21935,50 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v34, v6, v12
+; VI-NEXT: v_or_b32_e32 v33, v6, v12
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v24
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_add_f16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v33, v5, v12
+; VI-NEXT: v_or_b32_e32 v32, v5, v12
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_add_f16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v31, v8, v12
+; VI-NEXT: v_or_b32_e32 v30, v8, v12
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v30, v7, v12
+; VI-NEXT: v_or_b32_e32 v29, v7, v12
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v17
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_or_b32_e32 v29, v10, v12
-; VI-NEXT: v_or_b32_e32 v28, v9, v11
-; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[28:29]
-; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[30:31]
-; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[33:34]
+; VI-NEXT: v_or_b32_e32 v49, v10, v12
+; VI-NEXT: v_or_b32_e32 v48, v9, v11
+; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[48:49]
+; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[29:30]
+; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[32:33]
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[35:36]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[38:39]
-; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v29
-; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v28
-; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v31
-; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v30
-; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v34
-; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v33
+; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v49
+; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v48
+; VI-NEXT: v_lshrrev_b32_e32 v30, 8, v30
+; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v29
+; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v33
+; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v32
; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v36
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v35
; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v39
; VI-NEXT: v_lshrrev_b32_e32 v16, 8, v38
-; VI-NEXT: v_bfe_u32 v30, v17, 8, 8
-; VI-NEXT: v_bfe_u32 v33, v18, 8, 8
+; VI-NEXT: v_bfe_u32 v29, v17, 8, 8
+; VI-NEXT: v_bfe_u32 v32, v18, 8, 8
; VI-NEXT: v_bfe_u32 v35, v19, 8, 8
; VI-NEXT: v_bfe_u32 v38, v21, 8, 8
; VI-NEXT: v_bfe_u32 v48, v23, 8, 8
; VI-NEXT: .LBB60_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v15, v26, v15, s4
+; VI-NEXT: v_perm_b32 v15, v27, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_or_b32_e32 v1, v1, v15
@@ -21901,7 +22008,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v19, v35, s4
-; VI-NEXT: v_perm_b32 v1, v6, v32, s4
+; VI-NEXT: v_perm_b32 v1, v6, v33, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
@@ -21912,8 +22019,8 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v33, s4
-; VI-NEXT: v_perm_b32 v1, v8, v29, s4
+; VI-NEXT: v_perm_b32 v2, v18, v32, s4
+; VI-NEXT: v_perm_b32 v1, v8, v30, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
@@ -21924,8 +22031,8 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v17, v30, s4
-; VI-NEXT: v_perm_b32 v1, v10, v27, s4
+; VI-NEXT: v_perm_b32 v2, v17, v29, s4
+; VI-NEXT: v_perm_b32 v1, v10, v26, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
@@ -23440,347 +23547,342 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
-; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v37, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v38, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v19
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v29
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v25
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: s_waitcnt vmcnt(9) expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v35
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v53
-; SI-NEXT: s_waitcnt vmcnt(7) expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v54
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v55
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:4
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v40
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 8, v41
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB62_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v23
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v36, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v29, v0, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v34
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v37, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_or_b32_e32 v36, v3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v10, v38, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v21
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v22
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v23
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v10, v7
+; SI-NEXT: v_or_b32_e32 v34, v6, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v18
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v6, v10, v6
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v29
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v31, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v39, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v21, v0, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v52, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v54
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v32, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v49, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v18, v56, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v48
-; SI-NEXT: v_or_b32_e32 v11, v52, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v27
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v57
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
-; SI-NEXT: v_or_b32_e32 v7, v7, v45
-; SI-NEXT: v_or_b32_e32 v14, v47, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v20, v59, v15
-; SI-NEXT: v_or_b32_e32 v15, v0, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v47
+; SI-NEXT: v_or_b32_e32 v39, v0, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
-; SI-NEXT: v_or_b32_e32 v7, v7, v14
-; SI-NEXT: v_or_b32_e32 v13, v46, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v5, v5, v51
-; SI-NEXT: v_alignbit_b32 v27, v7, v13, 16
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v13, v0, v13
+; SI-NEXT: v_or_b32_e32 v31, v12, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
+; SI-NEXT: v_or_b32_e32 v35, v0, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v0, v57
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v5, v5, v12
-; SI-NEXT: v_or_b32_e32 v9, v9, v18
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v44
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v56
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v17, v1, v2, 16
-; SI-NEXT: v_alignbit_b32 v19, v3, v10, 16
-; SI-NEXT: v_alignbit_b32 v25, v5, v11, 16
-; SI-NEXT: v_alignbit_b32 v35, v9, v20, 16
-; SI-NEXT: v_or_b32_e32 v11, v0, v20
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v18
+; SI-NEXT: v_alignbit_b32 v38, v37, v2, 16
+; SI-NEXT: v_alignbit_b32 v48, v36, v3, 16
+; SI-NEXT: v_alignbit_b32 v50, v34, v6, 16
+; SI-NEXT: v_alignbit_b32 v51, v32, v10, 16
+; SI-NEXT: v_alignbit_b32 v53, v31, v12, 16
+; SI-NEXT: v_or_b32_e32 v33, v0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v13
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: .LBB62_2: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB62_4
-; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v43
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v59, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v50
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v46, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v1, v45, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v47, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v1, v51, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v1, v37, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: .LBB62_2: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB62_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v44
+; SI-NEXT: v_add_i32_e32 v33, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v33, 0xff, v33
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x300, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v56
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v32, v32, v33
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v31
+; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v59
+; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v28
+; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v49, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v52, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v57
+; SI-NEXT: v_add_i32_e32 v34, vcc, 3, v47
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v29
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v21
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v13
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_and_b32_e32 v34, 0xff, v34
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v31
+; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v54
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v32, v32, v34
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v25, v25, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v17, v1, v29, 16
-; SI-NEXT: v_alignbit_b32 v19, v3, v21, 16
-; SI-NEXT: v_alignbit_b32 v25, v5, v15, 16
-; SI-NEXT: v_alignbit_b32 v27, v7, v13, 16
-; SI-NEXT: v_alignbit_b32 v35, v9, v11, 16
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v9
+; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
+; SI-NEXT: v_add_i32_e32 v32, vcc, s7, v24
+; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
+; SI-NEXT: v_alignbit_b32 v38, v37, v52, 16
+; SI-NEXT: v_alignbit_b32 v48, v36, v49, 16
+; SI-NEXT: v_alignbit_b32 v50, v34, v39, 16
+; SI-NEXT: v_alignbit_b32 v51, v32, v35, 16
+; SI-NEXT: v_alignbit_b32 v53, v31, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v31
; SI-NEXT: .LBB62_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v53
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v19
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v55
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v27
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v40
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v43
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
@@ -23793,7 +23895,31 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v38
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v50
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v35
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v51
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v32
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v53
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -24048,20 +24174,17 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v36, v3
-; GFX9-NEXT: v_mov_b32_e32 v34, v2
-; GFX9-NEXT: v_mov_b32_e32 v31, v1
; GFX9-NEXT: v_mov_b32_e32 v38, v0
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:4
; GFX9-NEXT: v_mov_b32_e32 v39, v15
; GFX9-NEXT: v_mov_b32_e32 v53, v14
; GFX9-NEXT: v_mov_b32_e32 v52, v13
@@ -24074,14 +24197,11 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: v_mov_b32_e32 v48, v6
; GFX9-NEXT: v_mov_b32_e32 v37, v5
; GFX9-NEXT: v_mov_b32_e32 v51, v4
+; GFX9-NEXT: v_mov_b32_e32 v36, v3
+; GFX9-NEXT: v_mov_b32_e32 v34, v2
+; GFX9-NEXT: v_mov_b32_e32 v31, v1
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b16_e32 v47, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b16_e32 v46, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -24113,12 +24233,16 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v8, v30, v55, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v45
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v41
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v8, v42, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v9, v40, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v8, v44, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v40, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v44, v43, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v10, v47, v46, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr31
@@ -24152,31 +24276,35 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr55
-; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr44
-; GFX9-NEXT: ; implicit-def: $vgpr43
-; GFX9-NEXT: ; implicit-def: $vgpr41
-; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr42
+; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: .LBB62_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB62_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v41
-; GFX9-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT: v_or_b32_sdwa v0, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
@@ -24270,56 +24398,51 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v27.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v20.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v33.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v34.h
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v70
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v69
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB62_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
@@ -24330,180 +24453,185 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB62_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v24, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v51, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v29, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v24, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v27, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v68, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v26, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v33.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v53, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v8.l, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v34, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v67, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v8.h, v9.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v30, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v48, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v49, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v54, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v16.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v35, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v11.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_2
; GFX11-TRUE16-NEXT: .LBB62_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v33.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v64.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v16.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v16.h, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v52.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v53.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v67.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v48.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v54.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v53.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v51.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v50.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v28.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v26.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v36.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v49.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v38.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v29.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v23.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v16.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v20.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v18.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v11.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.h, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v12.l, v10.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v10.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v10.h
@@ -24513,33 +24641,27 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v35, v2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_b32 v1, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v31, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v39, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(9)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v66, 8, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v2
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v64, 8, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -24555,9 +24677,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: .LBB62_3: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v48, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v35, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v52, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
@@ -24569,35 +24691,38 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v67
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v70
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v69
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v66
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v30, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v65
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v64
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v66
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v67, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v8, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v12, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
@@ -24621,90 +24746,92 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB62_2
; GFX11-FAKE16-NEXT: .LBB62_4: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v69, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v69, 3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v71, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v66
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v70
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v68, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v65, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v66, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v64, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v20, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v13, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v32, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v54, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v53
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v52
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v50
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v16, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v49, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v17, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v13, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v13, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v53, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v37, 3
@@ -24729,8 +24856,8 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v16, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
@@ -27892,157 +28019,173 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v40i8_to_v5f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v36, v10
-; SI-NEXT: v_mov_b32_e32 v35, v8
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v38, v14
-; SI-NEXT: v_mov_b32_e32 v37, v12
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v54, v0
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v29
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v10
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB72_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v47, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v46
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v39
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v45, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v44
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v43, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v37
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v38
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v41, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v40
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v55, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v54
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v53, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v52
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v51, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v27
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v25, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v50
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_or_b32_e32 v8, v8, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v45
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v44
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v21, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v48
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v19
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v41
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v40
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -28050,121 +28193,131 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: .LBB72_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB72_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v47, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v46, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v45, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v36
-; SI-NEXT: v_or_b32_e32 v2, v44, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v43, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v37
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v38
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v41, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v40, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v55, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v54, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v53, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v52, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v51, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v27, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v25, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_or_b32_e32 v8, v23, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v45
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v43
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v21, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_or_b32_e32 v9, v19, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v41
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v55
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -28179,15 +28332,14 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB72_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -31736,157 +31888,173 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v40i8_to_v5i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v36, v10
-; SI-NEXT: v_mov_b32_e32 v35, v8
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v38, v14
-; SI-NEXT: v_mov_b32_e32 v37, v12
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v54, v0
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v29
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v0
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v4
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v10
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:4
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB76_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v47, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v1, v1, v46
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v39
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v45, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v44
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v43, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v37
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v38
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v41, v4
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
-; SI-NEXT: v_or_b32_e32 v4, v4, v40
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v55, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
-; SI-NEXT: v_or_b32_e32 v5, v5, v54
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v53, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
-; SI-NEXT: v_or_b32_e32 v6, v6, v52
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v51, v7
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v7, v7, v27
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v25, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v50
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
-; SI-NEXT: v_or_b32_e32 v8, v8, v23
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v45
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v44
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v21, v9
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v48
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v19
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v41
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v40
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -31894,121 +32062,131 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: .LBB76_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB76_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v47, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v46, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v45, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v35
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v36
-; SI-NEXT: v_or_b32_e32 v2, v44, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v43, v3
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v37
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v38
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v41, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v4, v40, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v5, v55, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v22
-; SI-NEXT: v_or_b32_e32 v5, v54, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v53, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v6, v52, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v7, v51, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v30
-; SI-NEXT: v_or_b32_e32 v7, v27, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v30
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v8, v25, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v50
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
-; SI-NEXT: v_or_b32_e32 v8, v23, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v45
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v44
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v43
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v9, v21, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_or_b32_e32 v9, v19, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v41
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v55
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
@@ -32023,15 +32201,14 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB76_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 0a8af1ab3e547..cb2b1c9451304 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -480,9 +480,8 @@ define i32 @bitcast_v2i16_to_i32(<2 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -495,14 +494,16 @@ define i32 @bitcast_v2i16_to_i32(<2 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -1197,10 +1198,8 @@ define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1212,15 +1211,19 @@ define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -2172,8 +2175,6 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2186,25 +2187,29 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB22_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: .LBB22_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2729,9 +2734,8 @@ define float @bitcast_v2i16_to_f32(<2 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2744,14 +2748,16 @@ define float @bitcast_v2i16_to_f32(<2 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -3455,10 +3461,8 @@ define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3470,15 +3474,19 @@ define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB34_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_2
; SI-NEXT: .LBB34_4: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -4435,8 +4443,6 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -4449,25 +4455,29 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB42_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: .LBB42_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -5197,22 +5207,30 @@ define <2 x bfloat> @bitcast_v2i16_to_v2bf16(<2 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v2i16_to_v2bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: ; %bb.1: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
-; SI-NEXT: ; %bb.2: ; %end
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: ; %bb.4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v2i16_to_v2bf16:
@@ -5375,24 +5393,26 @@ define <2 x i16> @bitcast_v2bf16_to_v2i16(<2 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -5742,9 +5762,8 @@ define <1 x i32> @bitcast_v2i16_to_v1i32(<2 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5757,14 +5776,16 @@ define <1 x i32> @bitcast_v2i16_to_v1i32(<2 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB52_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB52_2
; SI-NEXT: .LBB52_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -6133,9 +6154,9 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
; VI-NEXT: ; implicit-def: $vgpr0
; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6148,6 +6169,7 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB56_3: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v4
; VI-NEXT: v_mov_b32_e32 v0, v4
; VI-NEXT: ; implicit-def: $vgpr4
@@ -6415,45 +6437,48 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_or_b32_e32 v2, v1, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_or_b32_e32 v4, v0, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: .LBB58_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_or_b32_e32 v4, v0, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1
; SI-NEXT: .LBB58_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7012,25 +7037,27 @@ define <2 x half> @bitcast_v2bf16_to_v2f16(<2 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v0, v3, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_alignbit_b32 v1, v0, v1, 16
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: v_alignbit_b32 v1, v0, v1, 16
@@ -7791,8 +7818,8 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -7805,6 +7832,7 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB68_3: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB68_2
@@ -8074,45 +8102,48 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_or_b32_e32 v2, v1, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_or_b32_e32 v4, v0, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: .LBB70_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_or_b32_e32 v4, v0, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1
; SI-NEXT: .LBB70_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -8469,10 +8500,8 @@ define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -8484,15 +8513,19 @@ define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB72_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB72_2
; SI-NEXT: .LBB72_4: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -9020,11 +9053,9 @@ define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v2bf16_to_v4i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -9039,17 +9070,21 @@ define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB76_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v2, v5, 16
-; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB76_2
; SI-NEXT: .LBB76_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
@@ -9520,42 +9555,44 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v1, v4, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v4, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v5, v3, v0
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_or_b32_e32 v5, v1, v0
; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB78_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v2, v3, v1
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v2
; SI-NEXT: .LBB78_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -10202,8 +10239,6 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -10216,25 +10251,29 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB82_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB82_2
; SI-NEXT: .LBB82_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
index 70ed2ca42b706..73f4130d5cfac 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
@@ -964,29 +964,18 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v19, v2
; SI-NEXT: v_mov_b32_e32 v20, v1
; SI-NEXT: v_mov_b32_e32 v21, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -999,26 +988,37 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v28
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: v_or_b32_e32 v1, v1, v31
-; SI-NEXT: v_or_b32_e32 v2, v2, v30
-; SI-NEXT: v_or_b32_e32 v3, v3, v29
-; SI-NEXT: v_or_b32_e32 v4, v4, v28
-; SI-NEXT: v_or_b32_e32 v5, v5, v27
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
-; SI-NEXT: v_or_b32_e32 v7, v7, v25
-; SI-NEXT: v_or_b32_e32 v8, v8, v24
-; SI-NEXT: v_or_b32_e32 v9, v9, v23
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
@@ -1031,6 +1031,7 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -1041,43 +1042,53 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v28
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
-; SI-NEXT: v_or_b32_e32 v2, v30, v2
-; SI-NEXT: v_or_b32_e32 v3, v29, v3
-; SI-NEXT: v_or_b32_e32 v4, v28, v4
-; SI-NEXT: v_or_b32_e32 v5, v27, v5
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
-; SI-NEXT: v_or_b32_e32 v7, v25, v7
-; SI-NEXT: v_or_b32_e32 v8, v24, v8
-; SI-NEXT: v_or_b32_e32 v9, v23, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -2976,29 +2987,18 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v19, v2
; SI-NEXT: v_mov_b32_e32 v20, v1
; SI-NEXT: v_mov_b32_e32 v21, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3011,26 +3011,37 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v28
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: v_or_b32_e32 v1, v1, v31
-; SI-NEXT: v_or_b32_e32 v2, v2, v30
-; SI-NEXT: v_or_b32_e32 v3, v3, v29
-; SI-NEXT: v_or_b32_e32 v4, v4, v28
-; SI-NEXT: v_or_b32_e32 v5, v5, v27
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
-; SI-NEXT: v_or_b32_e32 v7, v7, v25
-; SI-NEXT: v_or_b32_e32 v8, v8, v24
-; SI-NEXT: v_or_b32_e32 v9, v9, v23
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
@@ -3043,6 +3054,7 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -3053,43 +3065,53 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v28
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v32, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v31, v1
-; SI-NEXT: v_or_b32_e32 v2, v30, v2
-; SI-NEXT: v_or_b32_e32 v3, v29, v3
-; SI-NEXT: v_or_b32_e32 v4, v28, v4
-; SI-NEXT: v_or_b32_e32 v5, v27, v5
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
-; SI-NEXT: v_or_b32_e32 v7, v25, v7
-; SI-NEXT: v_or_b32_e32 v8, v24, v8
-; SI-NEXT: v_or_b32_e32 v9, v23, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -4574,41 +4596,30 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v12
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr32
@@ -4617,32 +4628,43 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB20_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v13
+; SI-NEXT: v_or_b32_e32 v23, v1, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v24, v1, v35
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v29, v0, v33
+; SI-NEXT: v_or_b32_e32 v22, v3, v11
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; SI-NEXT: v_or_b32_e32 v29, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v22, v1, v37
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v25, v0, v36
+; SI-NEXT: v_or_b32_e32 v20, v5, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v16
+; SI-NEXT: v_or_b32_e32 v26, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v19, v1, v39
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v23, v0, v38
+; SI-NEXT: v_or_b32_e32 v18, v7, v11
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; SI-NEXT: v_or_b32_e32 v24, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v16, v1, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v20, v0, v48
+; SI-NEXT: v_or_b32_e32 v11, v9, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v37
+; SI-NEXT: v_or_b32_e32 v21, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v11, v1, v51
-; SI-NEXT: v_or_b32_e32 v17, v0, v50
+; SI-NEXT: v_alignbit_b32 v25, v23, v1, 16
+; SI-NEXT: v_or_b32_e32 v19, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_alignbit_b32 v26, v24, v33, 16
-; SI-NEXT: v_alignbit_b32 v27, v22, v36, 16
-; SI-NEXT: v_alignbit_b32 v28, v19, v38, 16
-; SI-NEXT: v_alignbit_b32 v30, v16, v48, 16
-; SI-NEXT: v_alignbit_b32 v31, v11, v50, 16
-; SI-NEXT: v_or_b32_e32 v32, v0, v34
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_alignbit_b32 v27, v22, v3, 16
+; SI-NEXT: v_alignbit_b32 v28, v20, v5, 16
+; SI-NEXT: v_alignbit_b32 v30, v18, v7, 16
+; SI-NEXT: v_alignbit_b32 v31, v11, v9, 16
+; SI-NEXT: v_or_b32_e32 v32, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -4654,108 +4676,113 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: .LBB20_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v37
+; SI-NEXT: v_or_b32_e32 v8, v11, v8
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v17
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v8, v50, v8
-; SI-NEXT: v_or_b32_e32 v6, v48, v6
-; SI-NEXT: v_or_b32_e32 v4, v38, v4
-; SI-NEXT: v_or_b32_e32 v2, v36, v2
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v13
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v8, v51, v8
-; SI-NEXT: v_or_b32_e32 v6, v49, v6
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v2, v37, v2
-; SI-NEXT: v_or_b32_e32 v0, v34, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v26, v24, v29, 16
-; SI-NEXT: v_alignbit_b32 v27, v22, v25, 16
-; SI-NEXT: v_alignbit_b32 v28, v19, v23, 16
-; SI-NEXT: v_alignbit_b32 v30, v16, v20, 16
-; SI-NEXT: v_alignbit_b32 v31, v11, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v11
+; SI-NEXT: v_alignbit_b32 v25, v23, v29, 16
+; SI-NEXT: v_alignbit_b32 v27, v22, v26, 16
+; SI-NEXT: v_alignbit_b32 v28, v20, v24, 16
+; SI-NEXT: v_alignbit_b32 v30, v18, v21, 16
+; SI-NEXT: v_alignbit_b32 v31, v11, v19, 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v32
; SI-NEXT: .LBB20_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v26
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v27
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v24
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v28
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v19
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v15
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v20
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v16
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v17
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v32
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
index 60c5431f7e4c6..44f3f82b4d60f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
@@ -2091,31 +2091,19 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v21, v2
; SI-NEXT: v_mov_b32_e32 v22, v1
; SI-NEXT: v_mov_b32_e32 v23, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2128,28 +2116,40 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v31
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v28
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v26
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: v_or_b32_e32 v2, v2, v33
-; SI-NEXT: v_or_b32_e32 v3, v3, v32
-; SI-NEXT: v_or_b32_e32 v4, v4, v31
-; SI-NEXT: v_or_b32_e32 v5, v5, v30
-; SI-NEXT: v_or_b32_e32 v6, v6, v29
-; SI-NEXT: v_or_b32_e32 v7, v7, v28
-; SI-NEXT: v_or_b32_e32 v8, v8, v27
-; SI-NEXT: v_or_b32_e32 v9, v9, v26
-; SI-NEXT: v_or_b32_e32 v10, v10, v25
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
@@ -2163,6 +2163,7 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
@@ -2174,46 +2175,57 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v31
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v29
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v28
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v26
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_or_b32_e32 v3, v32, v3
-; SI-NEXT: v_or_b32_e32 v4, v31, v4
-; SI-NEXT: v_or_b32_e32 v5, v30, v5
-; SI-NEXT: v_or_b32_e32 v6, v29, v6
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: v_or_b32_e32 v8, v27, v8
-; SI-NEXT: v_or_b32_e32 v9, v26, v9
-; SI-NEXT: v_or_b32_e32 v10, v25, v10
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -5334,31 +5346,19 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v21, v2
; SI-NEXT: v_mov_b32_e32 v22, v1
; SI-NEXT: v_mov_b32_e32 v23, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5371,28 +5371,40 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB30_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v31
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v28
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v26
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: v_or_b32_e32 v2, v2, v33
-; SI-NEXT: v_or_b32_e32 v3, v3, v32
-; SI-NEXT: v_or_b32_e32 v4, v4, v31
-; SI-NEXT: v_or_b32_e32 v5, v5, v30
-; SI-NEXT: v_or_b32_e32 v6, v6, v29
-; SI-NEXT: v_or_b32_e32 v7, v7, v28
-; SI-NEXT: v_or_b32_e32 v8, v8, v27
-; SI-NEXT: v_or_b32_e32 v9, v9, v26
-; SI-NEXT: v_or_b32_e32 v10, v10, v25
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr22
@@ -5406,6 +5418,7 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
@@ -5417,46 +5430,57 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: .LBB30_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v31
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v29
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v28
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v26
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v34, v1
-; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_or_b32_e32 v3, v32, v3
-; SI-NEXT: v_or_b32_e32 v4, v31, v4
-; SI-NEXT: v_or_b32_e32 v5, v30, v5
-; SI-NEXT: v_or_b32_e32 v6, v29, v6
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: v_or_b32_e32 v8, v27, v8
-; SI-NEXT: v_or_b32_e32 v9, v26, v9
-; SI-NEXT: v_or_b32_e32 v10, v25, v10
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -7984,31 +8008,19 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v25, v2
; SI-NEXT: v_mov_b32_e32 v26, v1
; SI-NEXT: v_mov_b32_e32 v27, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v27
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -8021,29 +8033,41 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB42_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v27
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v39
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v37
-; SI-NEXT: v_or_b32_e32 v3, v3, v36
-; SI-NEXT: v_or_b32_e32 v4, v4, v35
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v32
-; SI-NEXT: v_or_b32_e32 v8, v8, v31
-; SI-NEXT: v_or_b32_e32 v9, v9, v30
-; SI-NEXT: v_or_b32_e32 v10, v10, v29
-; SI-NEXT: v_or_b32_e32 v11, v11, v28
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -8072,42 +8096,54 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: .LBB42_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v37, v2
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v4, v35, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v32, v7
-; SI-NEXT: v_or_b32_e32 v8, v31, v8
-; SI-NEXT: v_or_b32_e32 v9, v30, v9
-; SI-NEXT: v_or_b32_e32 v10, v29, v10
-; SI-NEXT: v_or_b32_e32 v11, v28, v11
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -10148,31 +10184,19 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v25, v2
; SI-NEXT: v_mov_b32_e32 v26, v1
; SI-NEXT: v_mov_b32_e32 v27, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v27
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -10185,29 +10209,41 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v27
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v39
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v37
-; SI-NEXT: v_or_b32_e32 v3, v3, v36
-; SI-NEXT: v_or_b32_e32 v4, v4, v35
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
-; SI-NEXT: v_or_b32_e32 v7, v7, v32
-; SI-NEXT: v_or_b32_e32 v8, v8, v31
-; SI-NEXT: v_or_b32_e32 v9, v9, v30
-; SI-NEXT: v_or_b32_e32 v10, v10, v29
-; SI-NEXT: v_or_b32_e32 v11, v11, v28
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -10236,42 +10272,54 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v37, v2
-; SI-NEXT: v_or_b32_e32 v3, v36, v3
-; SI-NEXT: v_or_b32_e32 v4, v35, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
-; SI-NEXT: v_or_b32_e32 v7, v32, v7
-; SI-NEXT: v_or_b32_e32 v8, v31, v8
-; SI-NEXT: v_or_b32_e32 v9, v30, v9
-; SI-NEXT: v_or_b32_e32 v10, v29, v10
-; SI-NEXT: v_or_b32_e32 v11, v28, v11
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -11891,47 +11939,35 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v24i16_to_v24f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v16
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -11939,35 +11975,47 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v27, v1, v38
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; SI-NEXT: v_or_b32_e32 v26, v1, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v25, v1, v48
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v35, v0, v36
+; SI-NEXT: v_or_b32_e32 v24, v3, v12
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v15
+; SI-NEXT: v_or_b32_e32 v35, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v22, v1, v49
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v30, v0, v37
+; SI-NEXT: v_or_b32_e32 v23, v5, v12
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v38
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; SI-NEXT: v_or_b32_e32 v31, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v19, v1, v51
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v26, v0, v39
+; SI-NEXT: v_or_b32_e32 v21, v7, v12
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v17
+; SI-NEXT: v_or_b32_e32 v28, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v16, v1, v53
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v24, v0, v50
+; SI-NEXT: v_or_b32_e32 v19, v9, v12
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
+; SI-NEXT: v_or_b32_e32 v25, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v12, v1, v55
-; SI-NEXT: v_or_b32_e32 v21, v0, v52
+; SI-NEXT: v_or_b32_e32 v12, v11, v12
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v49
+; SI-NEXT: v_or_b32_e32 v22, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_alignbit_b32 v28, v27, v36, 16
-; SI-NEXT: v_alignbit_b32 v29, v25, v37, 16
-; SI-NEXT: v_alignbit_b32 v31, v22, v39, 16
-; SI-NEXT: v_alignbit_b32 v32, v19, v50, 16
-; SI-NEXT: v_alignbit_b32 v33, v16, v52, 16
-; SI-NEXT: v_alignbit_b32 v34, v12, v54, 16
-; SI-NEXT: v_or_b32_e32 v18, v0, v54
+; SI-NEXT: v_alignbit_b32 v27, v26, v1, 16
+; SI-NEXT: v_alignbit_b32 v29, v24, v3, 16
+; SI-NEXT: v_alignbit_b32 v30, v23, v5, 16
+; SI-NEXT: v_alignbit_b32 v32, v21, v7, 16
+; SI-NEXT: v_alignbit_b32 v33, v19, v9, 16
+; SI-NEXT: v_alignbit_b32 v34, v12, v11, 16
+; SI-NEXT: v_or_b32_e32 v20, v0, v11
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -11980,120 +12028,126 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v10, v54, v10
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v8, v52, v8
-; SI-NEXT: v_or_b32_e32 v6, v50, v6
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v2, v37, v2
-; SI-NEXT: v_or_b32_e32 v0, v36, v0
-; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v49
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v18
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v17
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v37
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v10, v55, v10
-; SI-NEXT: v_or_b32_e32 v8, v53, v8
-; SI-NEXT: v_or_b32_e32 v6, v51, v6
-; SI-NEXT: v_or_b32_e32 v4, v49, v4
-; SI-NEXT: v_or_b32_e32 v2, v48, v2
-; SI-NEXT: v_or_b32_e32 v0, v38, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v28, v27, v35, 16
-; SI-NEXT: v_alignbit_b32 v29, v25, v30, 16
-; SI-NEXT: v_alignbit_b32 v31, v22, v26, 16
-; SI-NEXT: v_alignbit_b32 v32, v19, v24, 16
-; SI-NEXT: v_alignbit_b32 v33, v16, v21, 16
-; SI-NEXT: v_alignbit_b32 v34, v12, v18, 16
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v13
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v27, v26, v35, 16
+; SI-NEXT: v_alignbit_b32 v29, v24, v31, 16
+; SI-NEXT: v_alignbit_b32 v30, v23, v28, 16
+; SI-NEXT: v_alignbit_b32 v32, v21, v25, 16
+; SI-NEXT: v_alignbit_b32 v33, v19, v22, 16
+; SI-NEXT: v_alignbit_b32 v34, v12, v20, 16
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v12
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v35
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v31
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v29
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v25
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v30
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v17
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v15
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v24
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v15
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v16
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v21
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v18
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v34
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
index cd47411c7e51c..0071a4e3d44ed 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
@@ -2306,35 +2306,21 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v27, v2
; SI-NEXT: v_mov_b32_e32 v28, v1
; SI-NEXT: v_mov_b32_e32 v29, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v29
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2347,33 +2333,47 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v51
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
-; SI-NEXT: v_or_b32_e32 v2, v2, v49
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_or_b32_e32 v4, v4, v39
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v37
-; SI-NEXT: v_or_b32_e32 v7, v7, v36
-; SI-NEXT: v_or_b32_e32 v8, v8, v35
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v33
-; SI-NEXT: v_or_b32_e32 v11, v11, v32
-; SI-NEXT: v_or_b32_e32 v12, v12, v31
-; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -2406,48 +2406,62 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_or_b32_e32 v7, v36, v7
-; SI-NEXT: v_or_b32_e32 v8, v35, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v33, v10
-; SI-NEXT: v_or_b32_e32 v11, v32, v11
-; SI-NEXT: v_or_b32_e32 v12, v31, v12
-; SI-NEXT: v_or_b32_e32 v13, v30, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -5957,35 +5971,21 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v27, v2
; SI-NEXT: v_mov_b32_e32 v28, v1
; SI-NEXT: v_mov_b32_e32 v29, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v29
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5998,33 +5998,47 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB30_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v51
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
-; SI-NEXT: v_or_b32_e32 v2, v2, v49
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_or_b32_e32 v4, v4, v39
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v37
-; SI-NEXT: v_or_b32_e32 v7, v7, v36
-; SI-NEXT: v_or_b32_e32 v8, v8, v35
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v33
-; SI-NEXT: v_or_b32_e32 v11, v11, v32
-; SI-NEXT: v_or_b32_e32 v12, v12, v31
-; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -6057,48 +6071,62 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: .LBB30_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_or_b32_e32 v7, v36, v7
-; SI-NEXT: v_or_b32_e32 v8, v35, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v33, v10
-; SI-NEXT: v_or_b32_e32 v11, v32, v11
-; SI-NEXT: v_or_b32_e32 v12, v31, v12
-; SI-NEXT: v_or_b32_e32 v13, v30, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -8985,35 +9013,21 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v27, v2
; SI-NEXT: v_mov_b32_e32 v28, v1
; SI-NEXT: v_mov_b32_e32 v29, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v29
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -9026,33 +9040,47 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB42_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v51
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
-; SI-NEXT: v_or_b32_e32 v2, v2, v49
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_or_b32_e32 v4, v4, v39
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v37
-; SI-NEXT: v_or_b32_e32 v7, v7, v36
-; SI-NEXT: v_or_b32_e32 v8, v8, v35
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v33
-; SI-NEXT: v_or_b32_e32 v11, v11, v32
-; SI-NEXT: v_or_b32_e32 v12, v12, v31
-; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -9085,48 +9113,62 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: .LBB42_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_or_b32_e32 v7, v36, v7
-; SI-NEXT: v_or_b32_e32 v8, v35, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v33, v10
-; SI-NEXT: v_or_b32_e32 v11, v32, v11
-; SI-NEXT: v_or_b32_e32 v12, v31, v12
-; SI-NEXT: v_or_b32_e32 v13, v30, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -11391,35 +11433,21 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v27, v2
; SI-NEXT: v_mov_b32_e32 v28, v1
; SI-NEXT: v_mov_b32_e32 v29, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v29
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -11432,33 +11460,47 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v51
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
-; SI-NEXT: v_or_b32_e32 v2, v2, v49
-; SI-NEXT: v_or_b32_e32 v3, v3, v48
-; SI-NEXT: v_or_b32_e32 v4, v4, v39
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v37
-; SI-NEXT: v_or_b32_e32 v7, v7, v36
-; SI-NEXT: v_or_b32_e32 v8, v8, v35
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v33
-; SI-NEXT: v_or_b32_e32 v11, v11, v32
-; SI-NEXT: v_or_b32_e32 v12, v12, v31
-; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -11491,48 +11533,62 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v50, v1
-; SI-NEXT: v_or_b32_e32 v2, v49, v2
-; SI-NEXT: v_or_b32_e32 v3, v48, v3
-; SI-NEXT: v_or_b32_e32 v4, v39, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_or_b32_e32 v7, v36, v7
-; SI-NEXT: v_or_b32_e32 v8, v35, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v33, v10
-; SI-NEXT: v_or_b32_e32 v11, v32, v11
-; SI-NEXT: v_or_b32_e32 v12, v31, v12
-; SI-NEXT: v_or_b32_e32 v13, v30, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -13302,66 +13358,42 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v28i16_to_v28f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v8
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v13
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v8
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v0
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v25
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v22
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v20
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v19
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -13369,40 +13401,54 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v31, v1, v52
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
+; SI-NEXT: v_or_b32_e32 v30, v1, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v50
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v29, v1, v54
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v49, v0, v50
+; SI-NEXT: v_or_b32_e32 v29, v3, v14
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v17
+; SI-NEXT: v_or_b32_e32 v49, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v27, v1, v40
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v37, v0, v51
+; SI-NEXT: v_or_b32_e32 v27, v5, v14
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v18
+; SI-NEXT: v_or_b32_e32 v37, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v25, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v32, v0, v53
+; SI-NEXT: v_or_b32_e32 v25, v7, v14
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v53
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v19
+; SI-NEXT: v_or_b32_e32 v34, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v22, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v30, v0, v55
+; SI-NEXT: v_or_b32_e32 v24, v9, v14
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v54
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v20
+; SI-NEXT: v_or_b32_e32 v31, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v19, v1, v45
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v28, v0, v41
+; SI-NEXT: v_or_b32_e32 v22, v11, v14
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v55
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; SI-NEXT: v_or_b32_e32 v28, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v14, v1, v47
-; SI-NEXT: v_or_b32_e32 v23, v0, v43
+; SI-NEXT: v_or_b32_e32 v14, v13, v14
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v40
+; SI-NEXT: v_or_b32_e32 v26, v0, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_alignbit_b32 v33, v31, v50, 16
-; SI-NEXT: v_alignbit_b32 v34, v29, v51, 16
-; SI-NEXT: v_alignbit_b32 v35, v27, v53, 16
-; SI-NEXT: v_alignbit_b32 v36, v25, v55, 16
-; SI-NEXT: v_alignbit_b32 v38, v22, v41, 16
-; SI-NEXT: v_alignbit_b32 v39, v19, v43, 16
-; SI-NEXT: v_alignbit_b32 v48, v14, v46, 16
-; SI-NEXT: v_or_b32_e32 v20, v0, v46
+; SI-NEXT: v_alignbit_b32 v32, v30, v1, 16
+; SI-NEXT: v_alignbit_b32 v33, v29, v3, 16
+; SI-NEXT: v_alignbit_b32 v35, v27, v5, 16
+; SI-NEXT: v_alignbit_b32 v36, v25, v7, 16
+; SI-NEXT: v_alignbit_b32 v38, v24, v9, 16
+; SI-NEXT: v_alignbit_b32 v39, v22, v11, 16
+; SI-NEXT: v_alignbit_b32 v48, v14, v13, 16
+; SI-NEXT: v_or_b32_e32 v23, v0, v13
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -13417,124 +13463,124 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v46, v12
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v10, v43, v10
-; SI-NEXT: v_or_b32_e32 v8, v41, v8
-; SI-NEXT: v_or_b32_e32 v6, v55, v6
-; SI-NEXT: v_or_b32_e32 v4, v53, v4
-; SI-NEXT: v_or_b32_e32 v2, v51, v2
-; SI-NEXT: v_or_b32_e32 v0, v50, v0
-; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v40
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v21
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v55
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v54
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v53
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v17
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v51
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v50
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: v_or_b32_e32 v10, v45, v10
-; SI-NEXT: v_or_b32_e32 v8, v44, v8
-; SI-NEXT: v_or_b32_e32 v6, v42, v6
-; SI-NEXT: v_or_b32_e32 v4, v40, v4
-; SI-NEXT: v_or_b32_e32 v2, v54, v2
-; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v33, v31, v49, 16
-; SI-NEXT: v_alignbit_b32 v34, v29, v37, 16
-; SI-NEXT: v_alignbit_b32 v35, v27, v32, 16
-; SI-NEXT: v_alignbit_b32 v36, v25, v30, 16
-; SI-NEXT: v_alignbit_b32 v38, v22, v28, 16
-; SI-NEXT: v_alignbit_b32 v39, v19, v23, 16
-; SI-NEXT: v_alignbit_b32 v48, v14, v20, 16
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v32, v30, v49, 16
+; SI-NEXT: v_alignbit_b32 v33, v29, v37, 16
+; SI-NEXT: v_alignbit_b32 v35, v27, v34, 16
+; SI-NEXT: v_alignbit_b32 v36, v25, v31, 16
+; SI-NEXT: v_alignbit_b32 v38, v24, v28, 16
+; SI-NEXT: v_alignbit_b32 v39, v22, v26, 16
+; SI-NEXT: v_alignbit_b32 v48, v14, v23, 16
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v27
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v14
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v31
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v37
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v16
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v32
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v34
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v27
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v17
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v30
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v31
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v25
@@ -13543,20 +13589,20 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v28
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v38
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v19
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v26
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v39
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v20
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v20
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v48
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index 5697cb1e909c8..b82509c751325 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -10,39 +10,42 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v3bf16_to_v3f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; SI-NEXT: v_alignbit_b32 v2, v1, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
+; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB0_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
@@ -734,22 +737,22 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v3bf16_to_v3i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr3
@@ -757,14 +760,17 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB4_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: v_alignbit_b32 v0, v2, v0, 16
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
@@ -1211,33 +1217,39 @@ define <3 x bfloat> @bitcast_v3i16_to_v3bf16(<3 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v3i16_to_v3bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_alignbit_b32 v3, v1, v0, 16
+; SI-NEXT: v_alignbit_b32 v5, v1, v0, 16
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v1
; SI-NEXT: ; %bb.4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1625,18 +1637,18 @@ define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v3, v1
-; SI-NEXT: v_alignbit_b32 v1, v3, v0, 16
+; SI-NEXT: v_alignbit_b32 v5, v3, v0, 16
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v4, v3, v5, 16
-; SI-NEXT: v_or_b32_e32 v2, v0, v5
+; SI-NEXT: v_alignbit_b32 v4, v3, v1, 16
+; SI-NEXT: v_or_b32_e32 v2, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr5
@@ -1646,7 +1658,8 @@ define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) {
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index ef584301602e2..c77136514c8dc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -2586,81 +2586,77 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v29, v2
; SI-NEXT: v_mov_b32_e32 v30, v1
; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB14_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB14_4
-; SI-NEXT: .LBB14_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB14_3: ; %cmp.false
+; SI-NEXT: s_cbranch_execz .LBB14_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_or_b32_e32 v3, v3, v52
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v6, v6, v49
-; SI-NEXT: v_or_b32_e32 v7, v7, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v38
-; SI-NEXT: v_or_b32_e32 v10, v10, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v36
-; SI-NEXT: v_or_b32_e32 v12, v12, v35
-; SI-NEXT: v_or_b32_e32 v13, v13, v34
-; SI-NEXT: v_or_b32_e32 v14, v14, v33
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -2678,6 +2674,7 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -2693,58 +2690,74 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: .LBB14_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB14_2
-; SI-NEXT: .LBB14_4: ; %cmp.true
+; SI-NEXT: s_cbranch_execz .LBB14_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
-; SI-NEXT: v_or_b32_e32 v6, v49, v6
-; SI-NEXT: v_or_b32_e32 v7, v48, v7
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v9, v38, v9
-; SI-NEXT: v_or_b32_e32 v10, v37, v10
-; SI-NEXT: v_or_b32_e32 v11, v36, v11
-; SI-NEXT: v_or_b32_e32 v12, v35, v12
-; SI-NEXT: v_or_b32_e32 v13, v34, v13
-; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -2762,7 +2775,10 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i16_to_v16i32:
@@ -5429,154 +5445,155 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v16i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v14
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v10
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v9
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v4
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v3
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v2
+; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v1
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB22_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB22_4
-; SI-NEXT: .LBB22_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB22_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
-; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_cbranch_execz .LBB22_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v52
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v32
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v28
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: .LBB22_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB22_2
-; SI-NEXT: .LBB22_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
+; SI-NEXT: s_cbranch_execz .LBB22_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -5584,91 +5601,122 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v49
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v33
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v29
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v25
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v23
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: .LBB22_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32bf16_to_v16i32:
@@ -11379,554 +11427,615 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: v_mov_b32_e32 v54, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v2, v2, v39
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v39
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v30
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
-; SI-NEXT: v_or_b32_e32 v9, v9, v59
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
-; SI-NEXT: v_or_b32_e32 v10, v10, v46
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v41
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
-; SI-NEXT: v_or_b32_e32 v12, v12, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v13, v13, v19
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
-; SI-NEXT: v_or_b32_e32 v14, v14, v25
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB26_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
-; SI-NEXT: v_or_b32_e32 v1, v39, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v35, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_or_b32_e32 v2, v36, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v18, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v30, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v59, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v46, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v43
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v41, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v55
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v30
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v63
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_or_b32_e32 v13, v19, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v14, v25, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: .LBB26_4: ; %end
@@ -17258,81 +17367,77 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v29, v2
; SI-NEXT: v_mov_b32_e32 v30, v1
; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB38_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB38_4
-; SI-NEXT: .LBB38_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB38_3: ; %cmp.false
+; SI-NEXT: s_cbranch_execz .LBB38_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_or_b32_e32 v3, v3, v52
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v6, v6, v49
-; SI-NEXT: v_or_b32_e32 v7, v7, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v38
-; SI-NEXT: v_or_b32_e32 v10, v10, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v36
-; SI-NEXT: v_or_b32_e32 v12, v12, v35
-; SI-NEXT: v_or_b32_e32 v13, v13, v34
-; SI-NEXT: v_or_b32_e32 v14, v14, v33
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -17350,6 +17455,7 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -17365,58 +17471,74 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: .LBB38_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB38_2
-; SI-NEXT: .LBB38_4: ; %cmp.true
+; SI-NEXT: s_cbranch_execz .LBB38_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
-; SI-NEXT: v_or_b32_e32 v6, v49, v6
-; SI-NEXT: v_or_b32_e32 v7, v48, v7
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v9, v38, v9
-; SI-NEXT: v_or_b32_e32 v10, v37, v10
-; SI-NEXT: v_or_b32_e32 v11, v36, v11
-; SI-NEXT: v_or_b32_e32 v12, v35, v12
-; SI-NEXT: v_or_b32_e32 v13, v34, v13
-; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -17434,7 +17556,10 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: .LBB38_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i16_to_v16f32:
@@ -20197,154 +20322,155 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v16f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v14
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v10
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v9
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v4
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v3
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v2
+; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v1
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB46_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB46_4
-; SI-NEXT: .LBB46_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB46_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
-; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_cbranch_execz .LBB46_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v52
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v32
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v28
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: .LBB46_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB46_2
-; SI-NEXT: .LBB46_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
+; SI-NEXT: s_cbranch_execz .LBB46_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -20352,91 +20478,122 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v49
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v33
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v29
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v25
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v23
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32bf16_to_v16f32:
@@ -26372,554 +26529,615 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: v_mov_b32_e32 v54, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v2, v2, v39
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v39
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v30
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
-; SI-NEXT: v_or_b32_e32 v9, v9, v59
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
-; SI-NEXT: v_or_b32_e32 v10, v10, v46
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v41
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
-; SI-NEXT: v_or_b32_e32 v12, v12, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v13, v13, v19
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
-; SI-NEXT: v_or_b32_e32 v14, v14, v25
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB50_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
-; SI-NEXT: v_or_b32_e32 v1, v39, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v35, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_or_b32_e32 v2, v36, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v18, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v30, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v59, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v46, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v43
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v41, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v55
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v30
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v63
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_or_b32_e32 v13, v19, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v14, v25, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: .LBB50_4: ; %end
@@ -31472,81 +31690,77 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v29, v2
; SI-NEXT: v_mov_b32_e32 v30, v1
; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB58_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB58_4
-; SI-NEXT: .LBB58_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB58_3: ; %cmp.false
+; SI-NEXT: s_cbranch_execz .LBB58_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_or_b32_e32 v3, v3, v52
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v6, v6, v49
-; SI-NEXT: v_or_b32_e32 v7, v7, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v38
-; SI-NEXT: v_or_b32_e32 v10, v10, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v36
-; SI-NEXT: v_or_b32_e32 v12, v12, v35
-; SI-NEXT: v_or_b32_e32 v13, v13, v34
-; SI-NEXT: v_or_b32_e32 v14, v14, v33
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -31564,6 +31778,7 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -31579,58 +31794,74 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: .LBB58_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB58_2
-; SI-NEXT: .LBB58_4: ; %cmp.true
+; SI-NEXT: s_cbranch_execz .LBB58_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
-; SI-NEXT: v_or_b32_e32 v6, v49, v6
-; SI-NEXT: v_or_b32_e32 v7, v48, v7
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v9, v38, v9
-; SI-NEXT: v_or_b32_e32 v10, v37, v10
-; SI-NEXT: v_or_b32_e32 v11, v36, v11
-; SI-NEXT: v_or_b32_e32 v12, v35, v12
-; SI-NEXT: v_or_b32_e32 v13, v34, v13
-; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -31648,7 +31879,10 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: .LBB58_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i16_to_v8i64:
@@ -34323,154 +34557,155 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v8i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v14
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v10
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v9
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v4
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v3
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v2
+; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v1
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB66_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB66_4
-; SI-NEXT: .LBB66_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB66_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
-; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_cbranch_execz .LBB66_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v52
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v32
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v28
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: .LBB66_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB66_2
-; SI-NEXT: .LBB66_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
+; SI-NEXT: s_cbranch_execz .LBB66_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -34478,91 +34713,122 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v49
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v33
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v29
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v25
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v23
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: .LBB66_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32bf16_to_v8i64:
@@ -40283,554 +40549,615 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: v_mov_b32_e32 v54, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v2, v2, v39
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v39
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v30
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
-; SI-NEXT: v_or_b32_e32 v9, v9, v59
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
-; SI-NEXT: v_or_b32_e32 v10, v10, v46
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v41
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
-; SI-NEXT: v_or_b32_e32 v12, v12, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v13, v13, v19
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
-; SI-NEXT: v_or_b32_e32 v14, v14, v25
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB70_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
-; SI-NEXT: v_or_b32_e32 v1, v39, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v35, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_or_b32_e32 v2, v36, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v18, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v30, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v59, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v46, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v43
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v41, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v55
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v30
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v63
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_or_b32_e32 v13, v19, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v14, v25, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: .LBB70_4: ; %end
@@ -44710,81 +45037,77 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v29, v2
; SI-NEXT: v_mov_b32_e32 v30, v1
; SI-NEXT: v_mov_b32_e32 v31, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB74_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB74_4
-; SI-NEXT: .LBB74_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB74_3: ; %cmp.false
+; SI-NEXT: s_cbranch_execz .LBB74_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_or_b32_e32 v1, v1, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
-; SI-NEXT: v_or_b32_e32 v3, v3, v52
-; SI-NEXT: v_or_b32_e32 v4, v4, v51
-; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v6, v6, v49
-; SI-NEXT: v_or_b32_e32 v7, v7, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v39
-; SI-NEXT: v_or_b32_e32 v9, v9, v38
-; SI-NEXT: v_or_b32_e32 v10, v10, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v36
-; SI-NEXT: v_or_b32_e32 v12, v12, v35
-; SI-NEXT: v_or_b32_e32 v13, v13, v34
-; SI-NEXT: v_or_b32_e32 v14, v14, v33
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
@@ -44802,6 +45125,7 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
@@ -44817,58 +45141,74 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: .LBB74_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB74_2
-; SI-NEXT: .LBB74_4: ; %cmp.true
+; SI-NEXT: s_cbranch_execz .LBB74_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v55
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
-; SI-NEXT: v_or_b32_e32 v3, v52, v3
-; SI-NEXT: v_or_b32_e32 v4, v51, v4
-; SI-NEXT: v_or_b32_e32 v5, v50, v5
-; SI-NEXT: v_or_b32_e32 v6, v49, v6
-; SI-NEXT: v_or_b32_e32 v7, v48, v7
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v9, v38, v9
-; SI-NEXT: v_or_b32_e32 v10, v37, v10
-; SI-NEXT: v_or_b32_e32 v11, v36, v11
-; SI-NEXT: v_or_b32_e32 v12, v35, v12
-; SI-NEXT: v_or_b32_e32 v13, v34, v13
-; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
@@ -44886,7 +45226,10 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: .LBB74_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i16_to_v8f64:
@@ -47529,154 +47872,155 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v8f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v14
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v12
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v11
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v10
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v9
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v6
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v4
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v3
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v2
+; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v1
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB82_3
-; SI-NEXT: ; %bb.1: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execnz .LBB82_4
-; SI-NEXT: .LBB82_2: ; %end
-; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB82_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
-; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
-; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
-; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
-; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
-; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
-; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
-; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
-; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
-; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: s_cbranch_execz .LBB82_2
+; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v52
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v32
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v30
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v28
+; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
+; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v22
+; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v20
+; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v18
+; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: .LBB82_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB82_2
-; SI-NEXT: .LBB82_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
+; SI-NEXT: s_cbranch_execz .LBB82_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -47684,91 +48028,122 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v49
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v35
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v33
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v29
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v25
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v23
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
+; SI-NEXT: .LBB82_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32bf16_to_v8f64:
@@ -53661,554 +54036,615 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v34, v6
-; SI-NEXT: v_mov_b32_e32 v33, v4
-; SI-NEXT: v_mov_b32_e32 v32, v2
-; SI-NEXT: v_mov_b32_e32 v31, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v53, v1
+; SI-NEXT: v_mov_b32_e32 v54, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44
+; SI-NEXT: v_mov_b32_e32 v31, v15
+; SI-NEXT: v_mov_b32_e32 v32, v14
+; SI-NEXT: v_mov_b32_e32 v33, v13
+; SI-NEXT: v_mov_b32_e32 v34, v12
+; SI-NEXT: v_mov_b32_e32 v35, v11
+; SI-NEXT: v_mov_b32_e32 v36, v10
+; SI-NEXT: v_mov_b32_e32 v37, v9
+; SI-NEXT: v_mov_b32_e32 v38, v8
+; SI-NEXT: v_mov_b32_e32 v39, v7
+; SI-NEXT: v_mov_b32_e32 v48, v6
+; SI-NEXT: v_mov_b32_e32 v49, v5
+; SI-NEXT: v_mov_b32_e32 v50, v4
+; SI-NEXT: v_mov_b32_e32 v51, v3
+; SI-NEXT: v_mov_b32_e32 v52, v2
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v54
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
-; SI-NEXT: v_or_b32_e32 v0, v0, v49
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v52
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v2, v2, v39
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v51
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v49
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v48
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v39
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v36
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v35
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v32
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v3, v38
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v31
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v18
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v5, v22
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v26
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v27
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v7, v30
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
-; SI-NEXT: v_or_b32_e32 v9, v9, v59
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
-; SI-NEXT: v_or_b32_e32 v10, v10, v46
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v41
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
-; SI-NEXT: v_or_b32_e32 v12, v12, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v13, v13, v19
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
-; SI-NEXT: v_or_b32_e32 v14, v14, v25
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB86_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
-; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v53
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v52
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v51
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
-; SI-NEXT: v_or_b32_e32 v1, v39, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v48
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v35, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v43, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v54, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v21, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v27, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_or_b32_e32 v2, v36, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v37
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v36
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v16, v4
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v34
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v31
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v20, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v24, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v28, v7
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v17, v8
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v18, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v21
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v22
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v25
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v30, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v62
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v61
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v59, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v57
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v46, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v44
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v43
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v41, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v40
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v55
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v30
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v63
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_or_b32_e32 v13, v19, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v14, v25, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: .LBB86_4: ; %end
@@ -57558,81 +57994,54 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v32i16_to_v32f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v15
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v27
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v26
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v24
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -57640,45 +58049,61 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB88_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v36, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; SI-NEXT: v_or_b32_e32 v35, v1, v16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v34, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v55, v0, v40
+; SI-NEXT: v_or_b32_e32 v33, v3, v16
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v19
+; SI-NEXT: v_or_b32_e32 v55, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v32, v1, v46
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v51, v0, v41
+; SI-NEXT: v_or_b32_e32 v32, v5, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v42
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v20
+; SI-NEXT: v_or_b32_e32 v52, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v29, v1, v56
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v39, v0, v43
+; SI-NEXT: v_or_b32_e32 v30, v7, v16
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v43
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
+; SI-NEXT: v_or_b32_e32 v48, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v26, v1, v58
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v35, v0, v45
+; SI-NEXT: v_or_b32_e32 v28, v9, v16
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v22
+; SI-NEXT: v_or_b32_e32 v37, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v23, v1, v60
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v33, v0, v47
+; SI-NEXT: v_or_b32_e32 v26, v11, v16
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v45
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v23
+; SI-NEXT: v_or_b32_e32 v34, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v21, v1, v62
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v30, v0, v57
+; SI-NEXT: v_or_b32_e32 v25, v13, v16
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v46
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v24
+; SI-NEXT: v_or_b32_e32 v31, v0, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v16, v1, v63
-; SI-NEXT: v_or_b32_e32 v27, v0, v59
+; SI-NEXT: v_or_b32_e32 v16, v15, v16
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v47
+; SI-NEXT: v_or_b32_e32 v29, v0, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_alignbit_b32 v37, v36, v40, 16
-; SI-NEXT: v_alignbit_b32 v38, v34, v41, 16
-; SI-NEXT: v_alignbit_b32 v48, v32, v43, 16
-; SI-NEXT: v_alignbit_b32 v49, v29, v45, 16
-; SI-NEXT: v_alignbit_b32 v50, v26, v47, 16
-; SI-NEXT: v_alignbit_b32 v52, v23, v57, 16
-; SI-NEXT: v_alignbit_b32 v53, v21, v59, 16
-; SI-NEXT: v_alignbit_b32 v54, v16, v61, 16
-; SI-NEXT: v_or_b32_e32 v24, v0, v61
+; SI-NEXT: v_alignbit_b32 v36, v35, v1, 16
+; SI-NEXT: v_alignbit_b32 v38, v33, v3, 16
+; SI-NEXT: v_alignbit_b32 v39, v32, v5, 16
+; SI-NEXT: v_alignbit_b32 v49, v30, v7, 16
+; SI-NEXT: v_alignbit_b32 v50, v28, v9, 16
+; SI-NEXT: v_alignbit_b32 v51, v26, v11, 16
+; SI-NEXT: v_alignbit_b32 v53, v25, v13, 16
+; SI-NEXT: v_alignbit_b32 v54, v16, v15, 16
+; SI-NEXT: v_or_b32_e32 v27, v0, v15
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -57695,172 +58120,172 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: .LBB88_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v14, v61, v14
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v12, v59, v12
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v8, v47, v8
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_or_b32_e32 v4, v43, v4
-; SI-NEXT: v_or_b32_e32 v2, v41, v2
-; SI-NEXT: v_or_b32_e32 v0, v40, v0
-; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v47
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v24
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v23
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v45
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v22
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v44
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v43
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v42
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v41
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v18
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v40
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v14, v63, v14
-; SI-NEXT: v_or_b32_e32 v12, v62, v12
-; SI-NEXT: v_or_b32_e32 v10, v60, v10
-; SI-NEXT: v_or_b32_e32 v8, v58, v8
-; SI-NEXT: v_or_b32_e32 v6, v56, v6
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
-; SI-NEXT: v_or_b32_e32 v2, v44, v2
-; SI-NEXT: v_or_b32_e32 v0, v42, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v37, v36, v55, 16
-; SI-NEXT: v_alignbit_b32 v38, v34, v51, 16
-; SI-NEXT: v_alignbit_b32 v48, v32, v39, 16
-; SI-NEXT: v_alignbit_b32 v49, v29, v35, 16
-; SI-NEXT: v_alignbit_b32 v50, v26, v33, 16
-; SI-NEXT: v_alignbit_b32 v52, v23, v30, 16
-; SI-NEXT: v_alignbit_b32 v53, v21, v27, 16
-; SI-NEXT: v_alignbit_b32 v54, v16, v24, 16
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v36, v35, v55, 16
+; SI-NEXT: v_alignbit_b32 v38, v33, v52, 16
+; SI-NEXT: v_alignbit_b32 v39, v32, v48, 16
+; SI-NEXT: v_alignbit_b32 v49, v30, v37, 16
+; SI-NEXT: v_alignbit_b32 v50, v28, v34, 16
+; SI-NEXT: v_alignbit_b32 v51, v26, v31, 16
+; SI-NEXT: v_alignbit_b32 v53, v25, v29, 16
+; SI-NEXT: v_alignbit_b32 v54, v16, v27, 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v33
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v30
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v16
; SI-NEXT: .LBB88_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v36
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v31
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v51
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v52
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v34
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v39
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v32
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v35
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v37
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v49
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v33
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v34
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v50
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v20
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v30
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v52
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v23
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v27
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v29
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v53
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v18
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v23
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v24
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v54
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v24
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -59387,75 +59812,108 @@ define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v32i16_to_v32bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v44
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v45
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v46
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v47
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v56
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v57
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v58
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v59
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v60
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v61
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v62
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v63
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -59472,58 +59930,90 @@ define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB92_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v63
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v62
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v61
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_or_b32_e32 v13, v16, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v60
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
+; SI-NEXT: v_or_b32_e32 v12, v16, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v59
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v11, v16, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v58
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_or_b32_e32 v10, v16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v57
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_or_b32_e32 v9, v16, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v56
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_or_b32_e32 v8, v16, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v47
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v7, v16, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v46
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_or_b32_e32 v6, v16, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v45
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_or_b32_e32 v5, v16, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v44
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_or_b32_e32 v4, v16, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v43
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v3, v16, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v42
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v16, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v41
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v15, v31, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v40
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v14, v30, v14
-; SI-NEXT: v_or_b32_e32 v13, v29, v13
-; SI-NEXT: v_or_b32_e32 v12, v28, v12
-; SI-NEXT: v_or_b32_e32 v11, v27, v11
-; SI-NEXT: v_or_b32_e32 v10, v26, v10
-; SI-NEXT: v_or_b32_e32 v9, v25, v9
-; SI-NEXT: v_or_b32_e32 v8, v24, v8
-; SI-NEXT: v_or_b32_e32 v7, v23, v7
-; SI-NEXT: v_or_b32_e32 v6, v22, v6
-; SI-NEXT: v_or_b32_e32 v5, v21, v5
-; SI-NEXT: v_or_b32_e32 v4, v20, v4
-; SI-NEXT: v_or_b32_e32 v3, v19, v3
-; SI-NEXT: v_or_b32_e32 v2, v18, v2
-; SI-NEXT: v_or_b32_e32 v1, v17, v1
; SI-NEXT: v_or_b32_e32 v0, v16, v0
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
@@ -59541,104 +60031,121 @@ define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v3
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v6
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v7
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v8
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v9
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v10
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v11
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v12
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v13
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v15
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v18
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v34
-; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v24
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v21
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v20
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v26
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v36
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v23
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v28
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v25
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v30
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v38
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v27
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v32
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v29
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v48
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v25
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v36
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v49
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v33
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v38
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v35
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v48
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v37
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v50
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v39
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v29
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v52
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v49
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v54
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v51
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v31
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v55
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v53
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v32i16_to_v32bf16:
@@ -60312,38 +60819,6 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v32i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -60360,44 +60835,50 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v15
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v14
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v13
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v12
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v10
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v9
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v8
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v7
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v6
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v6
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v4
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v4
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v3
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v2
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v2
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v1
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v17
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v0
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr3
@@ -60407,211 +60888,279 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v62
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v61
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v54
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v28
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v60
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v31
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v56
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v46
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v44
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v42
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v59
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v57
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v47
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v45
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v11
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v51
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v12
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v43
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v13
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v14
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v41
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v15
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: .LBB94_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v62
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v60
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v2
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v61
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v58
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v59
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v56
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v56
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v46
; SI-NEXT: v_alignbit_b32 v6, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v44
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v44
; SI-NEXT: v_alignbit_b32 v8, v8, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v45
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v42
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v42
; SI-NEXT: v_alignbit_b32 v10, v10, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v40
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v55
; SI-NEXT: v_alignbit_b32 v12, v12, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v54
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v39
; SI-NEXT: v_alignbit_b32 v14, v14, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v52
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v37
; SI-NEXT: v_alignbit_b32 v15, v16, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v13
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v35
; SI-NEXT: v_alignbit_b32 v13, v17, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v48
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v33
; SI-NEXT: v_alignbit_b32 v11, v18, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v38
+; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v32
; SI-NEXT: v_alignbit_b32 v9, v19, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v7
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v31
; SI-NEXT: v_alignbit_b32 v7, v20, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v30
; SI-NEXT: v_alignbit_b32 v5, v21, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v27
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v28
; SI-NEXT: v_alignbit_b32 v3, v22, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_alignbit_b32 v1, v23, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; SI-NEXT: v_alignbit_b32 v24, v1, v24, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_alignbit_b32 v1, v24, v1, 16
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_alignbit_b32 v23, v1, v23, 16
; SI-NEXT: v_alignbit_b32 v25, v3, v25, 16
; SI-NEXT: v_alignbit_b32 v26, v5, v26, 16
-; SI-NEXT: v_alignbit_b32 v29, v7, v29, 16
-; SI-NEXT: v_alignbit_b32 v30, v9, v30, 16
-; SI-NEXT: v_alignbit_b32 v31, v11, v31, 16
-; SI-NEXT: v_alignbit_b32 v32, v13, v32, 16
-; SI-NEXT: v_alignbit_b32 v35, v15, v35, 16
+; SI-NEXT: v_alignbit_b32 v27, v7, v27, 16
+; SI-NEXT: v_alignbit_b32 v29, v9, v29, 16
+; SI-NEXT: v_alignbit_b32 v48, v11, v35, 16
+; SI-NEXT: v_alignbit_b32 v54, v13, v37, 16
+; SI-NEXT: v_alignbit_b32 v40, v15, v39, 16
; SI-NEXT: .LBB94_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v13, v13, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v40
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -60628,8 +61177,11 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_or_b32_e32 v0, v0, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
@@ -60640,10 +61192,6 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v1, v1, v23
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v25
@@ -60652,22 +61200,19 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; SI-NEXT: v_or_b32_e32 v5, v5, v21
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v27
; SI-NEXT: v_or_b32_e32 v7, v7, v20
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
; SI-NEXT: v_or_b32_e32 v9, v9, v19
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v48
; SI-NEXT: v_or_b32_e32 v11, v11, v18
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; SI-NEXT: v_or_b32_e32 v13, v13, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v54
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v35
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v24
; SI-NEXT: v_or_b32_e32 v2, v2, v23
; SI-NEXT: v_or_b32_e32 v4, v4, v22
; SI-NEXT: v_or_b32_e32 v6, v6, v21
@@ -63470,26 +64015,11 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; kill: killed $vgpr17
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr17
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; kill: killed $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -63507,213 +64037,202 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
-; SI-NEXT: ; kill: killed $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v44
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v35
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v18
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1
; SI-NEXT: ; kill: killed $vgpr17
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; kill: killed $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; kill: killed $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; kill: killed $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; kill: killed $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; kill: killed $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; kill: killed $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v58, v1, v59
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v58
+; SI-NEXT: v_or_b32_e32 v43, v1, v17
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v57, v1, v56
-; SI-NEXT: v_alignbit_b32 v1, v57, v58, 24
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
+; SI-NEXT: v_or_b32_e32 v46, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v57, v58, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v51, v1, v61
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v59
+; SI-NEXT: v_or_b32_e32 v38, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v39, v1, v60
-; SI-NEXT: v_alignbit_b32 v1, v39, v51, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
+; SI-NEXT: v_or_b32_e32 v37, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v39, v51, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v34, v1, v63
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v60
+; SI-NEXT: v_or_b32_e32 v35, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v33, v1, v62
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
+; SI-NEXT: v_or_b32_e32 v36, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 16
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v32, v1, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v61
+; SI-NEXT: v_or_b32_e32 v33, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v31, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_or_b32_e32 v34, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 16
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v29, v1, v48
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v62
+; SI-NEXT: v_or_b32_e32 v31, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v28, v1, v38
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: v_or_b32_e32 v32, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 16
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v26, v1, v50
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v63
+; SI-NEXT: v_or_b32_e32 v28, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v25, v1, v49
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; SI-NEXT: v_or_b32_e32 v29, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 16
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v24, v1, v53
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
+; SI-NEXT: v_or_b32_e32 v25, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v22, v1, v52
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
+; SI-NEXT: v_or_b32_e32 v26, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v21, v1, v55
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v48
+; SI-NEXT: v_or_b32_e32 v17, v1, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v17, v1, v54
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 24
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
+; SI-NEXT: v_or_b32_e32 v22, v1, v2
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
+; SI-NEXT: v_lshrrev_b32_e32 v56, 8, v46
+; SI-NEXT: v_lshrrev_b32_e32 v45, 8, v37
+; SI-NEXT: v_lshrrev_b32_e32 v42, 8, v36
+; SI-NEXT: v_lshrrev_b32_e32 v40, 8, v34
+; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v32
+; SI-NEXT: v_lshrrev_b32_e32 v52, 8, v29
+; SI-NEXT: v_lshrrev_b32_e32 v50, 8, v26
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v27, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v23, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v20, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v19, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_bfe_u32 v1, v18, 8, 8
-; SI-NEXT: v_alignbit_b32 v41, v57, v58, 8
-; SI-NEXT: v_alignbit_b32 v40, v39, v51, 8
-; SI-NEXT: v_lshrrev_b32_e32 v46, 8, v57
-; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v39
-; SI-NEXT: v_bfe_u32 v47, v44, 8, 8
-; SI-NEXT: v_bfe_u32 v45, v35, 8, 8
-; SI-NEXT: v_bfe_u32 v42, v30, 8, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_bfe_u32 v57, v30, 8, 8
+; SI-NEXT: v_bfe_u32 v47, v27, 8, 8
+; SI-NEXT: v_bfe_u32 v44, v24, 8, 8
+; SI-NEXT: v_bfe_u32 v41, v23, 8, 8
+; SI-NEXT: v_bfe_u32 v55, v21, 8, 8
+; SI-NEXT: v_bfe_u32 v53, v20, 8, 8
+; SI-NEXT: v_bfe_u32 v51, v19, 8, 8
+; SI-NEXT: v_bfe_u32 v49, v18, 8, 8
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
@@ -63730,266 +64249,262 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: .LBB96_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v48
+; SI-NEXT: v_or_b32_e32 v15, v17, v15
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v18
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v15
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v39
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v19
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
+; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v13
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v63
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v20
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
+; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v21
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v9
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v61
+; SI-NEXT: v_or_b32_e32 v7, v9, v7
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v23
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_or_b32_e32 v3, v61, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
-; SI-NEXT: v_or_b32_e32 v1, v56, v1
-; SI-NEXT: v_or_b32_e32 v5, v63, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v7, v5
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v3, v60, v3
-; SI-NEXT: v_alignbit_b32 v1, v57, v58, 24
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v3
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v24
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v27
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v57, v58, 16
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: v_or_b32_e32 v5, v62, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v1
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v39, v51, 24
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v39, v51, 16
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v46, v43, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 24
-; SI-NEXT: v_or_b32_e32 v9, v48, v9
-; SI-NEXT: v_or_b32_e32 v7, v36, v7
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 16
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v33, v34, 8
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 24
-; SI-NEXT: v_or_b32_e32 v11, v50, v11
-; SI-NEXT: v_or_b32_e32 v9, v38, v9
+; SI-NEXT: v_alignbit_b32 v1, v37, v38, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 16
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v31, v32, 8
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v36, v35, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 24
-; SI-NEXT: v_or_b32_e32 v13, v53, v13
-; SI-NEXT: v_or_b32_e32 v11, v49, v11
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 16
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v28, v29, 8
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v34, v33, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 24
-; SI-NEXT: v_or_b32_e32 v15, v55, v15
-; SI-NEXT: v_or_b32_e32 v13, v52, v13
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 16
-; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v25, v26, 8
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 24
-; SI-NEXT: v_or_b32_e32 v15, v54, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v32, v31, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v15
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v22, v24, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v29, v28, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 16
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v17, v21, 8
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v31
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v28
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v26, v25, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v22
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v22, v17, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v57, 24, v46
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v56, 8, v46
+; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v37
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v45, 8, v37
+; SI-NEXT: v_lshrrev_b32_e32 v44, 24, v36
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v42, 8, v36
+; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v34
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v40, 8, v34
+; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v32
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v32
+; SI-NEXT: v_lshrrev_b32_e32 v53, 24, v29
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v52, 8, v29
+; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v26
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v50, 8, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 24, v22
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v22
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v17
-; SI-NEXT: v_alignbit_b32 v41, v57, v58, 8
-; SI-NEXT: v_alignbit_b32 v40, v39, v51, 8
-; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v57
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v46, 8, v57
-; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v39
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v39
-; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v33
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v22
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: .LBB96_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v41
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v43
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v46
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v56
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v44
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v47
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v57
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v51
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v40
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v39
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v45
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v47
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v35
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -64004,24 +64519,22 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v42
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v42
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v44
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -64036,26 +64549,22 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v40
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v23
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v41
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v29
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -64070,26 +64579,22 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v23
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v55
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v26
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -64104,30 +64609,26 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v52
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v53
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v24
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v25
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -64138,30 +64639,26 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v50
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v51
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
@@ -64172,18 +64669,16 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -64209,60 +64704,39 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
;
; VI-LABEL: bitcast_v32i16_to_v64i8:
; VI: ; %bb.0:
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; kill: killed $vgpr19
; VI-NEXT: ; implicit-def: $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; kill: killed $vgpr19
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr19
-; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
; VI-NEXT: ; kill: killed $vgpr19
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr19
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -64280,108 +64754,149 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr55
-; VI-NEXT: ; implicit-def: $vgpr57
-; VI-NEXT: ; implicit-def: $vgpr53
-; VI-NEXT: ; implicit-def: $vgpr44
-; VI-NEXT: ; implicit-def: $vgpr63
-; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr42
+; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr46
-; VI-NEXT: ; implicit-def: $vgpr61
-; VI-NEXT: ; implicit-def: $vgpr59
-; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: ; implicit-def: $vgpr52
-; VI-NEXT: ; implicit-def: $vgpr50
-; VI-NEXT: ; implicit-def: $vgpr43
-; VI-NEXT: ; implicit-def: $vgpr41
+; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr47
+; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr45
+; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: ; implicit-def: $vgpr50
+; VI-NEXT: ; implicit-def: $vgpr44
+; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: ; implicit-def: $vgpr60
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr58
-; VI-NEXT: ; implicit-def: $vgpr51
+; VI-NEXT: ; implicit-def: $vgpr39
+; VI-NEXT: ; implicit-def: $vgpr57
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr61
+; VI-NEXT: ; implicit-def: $vgpr37
+; VI-NEXT: ; implicit-def: $vgpr60
+; VI-NEXT: ; implicit-def: $vgpr36
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: ; implicit-def: $vgpr59
+; VI-NEXT: ; implicit-def: $vgpr33
+; VI-NEXT: ; implicit-def: $vgpr63
+; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr41
+; VI-NEXT: ; implicit-def: $vgpr31
+; VI-NEXT: ; implicit-def: $vgpr53
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr62
-; VI-NEXT: ; kill: killed $vgpr19
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr43
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr21
-; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr19
-; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr19
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB96_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v4
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v14
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[13:14]
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v14
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v13
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v12
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v14
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v11
-; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v13
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v12
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v10
-; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v7
-; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v9
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v6
-; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
-; VI-NEXT: v_lshrrev_b32_e32 v50, 24, v16
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v8
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v5
-; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v12
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v6
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v18, 24, v4
-; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v3
-; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v2
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v1
-; VI-NEXT: v_mov_b32_e32 v25, v50
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v7
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v6
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v6
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v5
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v4
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
+; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
+; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[11:12]
+; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
+; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
+; VI-NEXT: v_lshrrev_b32_e32 v19, 24, v16
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
+; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
+; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v15
+; VI-NEXT: v_lshrrev_b32_e32 v62, 24, v14
+; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v13
+; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v12
+; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v12
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
+; VI-NEXT: v_lshrrev_b32_e32 v59, 8, v11
+; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v10
+; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v9
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v4
+; VI-NEXT: v_mov_b32_e32 v54, v5
+; VI-NEXT: v_mov_b32_e32 v58, v7
+; VI-NEXT: v_mov_b32_e32 v57, v8
+; VI-NEXT: v_mov_b32_e32 v61, v9
+; VI-NEXT: v_mov_b32_e32 v60, v10
+; VI-NEXT: v_mov_b32_e32 v38, v11
+; VI-NEXT: v_mov_b32_e32 v63, v12
+; VI-NEXT: v_mov_b32_e32 v41, v13
+; VI-NEXT: v_mov_b32_e32 v53, v14
+; VI-NEXT: v_mov_b32_e32 v17, v15
+; VI-NEXT: v_mov_b32_e32 v43, v16
+; VI-NEXT: v_mov_b32_e32 v48, v6
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v3
+; VI-NEXT: v_mov_b32_e32 v52, v3
+; VI-NEXT: v_mov_b32_e32 v50, v4
+; VI-NEXT: v_lshrrev_b32_e32 v47, 24, v2
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v1
; VI-NEXT: v_mov_b32_e32 v55, v1
-; VI-NEXT: v_mov_b32_e32 v53, v2
-; VI-NEXT: v_mov_b32_e32 v56, v3
-; VI-NEXT: v_mov_b32_e32 v46, v4
-; VI-NEXT: v_mov_b32_e32 v61, v5
-; VI-NEXT: v_mov_b32_e32 v59, v6
-; VI-NEXT: v_mov_b32_e32 v52, v7
-; VI-NEXT: v_mov_b32_e32 v50, v8
-; VI-NEXT: v_mov_b32_e32 v43, v9
-; VI-NEXT: v_mov_b32_e32 v41, v10
-; VI-NEXT: v_mov_b32_e32 v47, v11
-; VI-NEXT: v_mov_b32_e32 v45, v12
-; VI-NEXT: v_mov_b32_e32 v60, v13
-; VI-NEXT: v_mov_b32_e32 v58, v14
-; VI-NEXT: v_mov_b32_e32 v51, v15
-; VI-NEXT: v_mov_b32_e32 v62, v16
+; VI-NEXT: v_mov_b32_e32 v51, v2
+; VI-NEXT: v_mov_b32_e32 v25, v19
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
@@ -64391,255 +64906,260 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: .LBB96_2: ; %Flow
-; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: s_xor_b64 exec, exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
-; VI-NEXT: v_mov_b32_e32 v17, 3
-; VI-NEXT: v_add_u16_sdwa v28, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v33, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v26, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v29, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v30, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v35, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v45, 3, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
-; VI-NEXT: v_add_u16_e32 v47, 3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
-; VI-NEXT: v_add_u16_e32 v62, 3, v16
+; VI-NEXT: v_mov_b32_e32 v18, 3
+; VI-NEXT: v_add_u16_sdwa v26, v16, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v29, v15, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v43, 3, v16
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; VI-NEXT: v_add_u16_e32 v51, 3, v15
+; VI-NEXT: v_add_u16_e32 v17, 3, v15
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v29
-; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v41, 3, v10
+; VI-NEXT: v_or_b32_e32 v16, v43, v16
+; VI-NEXT: v_or_b32_e32 v15, v17, v15
+; VI-NEXT: v_add_u16_sdwa v27, v14, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v31, v13, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[15:16]
+; VI-NEXT: v_add_u16_e32 v53, 3, v14
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
+; VI-NEXT: v_add_u16_e32 v41, 3, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; VI-NEXT: v_or_b32_e32 v14, v53, v14
+; VI-NEXT: v_or_b32_e32 v13, v41, v13
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v30, v10, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v37, v9, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[13:14]
+; VI-NEXT: v_add_u16_sdwa v32, v8, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v39, v7, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v60, 3, v10
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
-; VI-NEXT: v_add_u16_e32 v43, 3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
-; VI-NEXT: v_or_b32_e32 v12, v45, v12
-; VI-NEXT: v_or_b32_e32 v11, v47, v11
-; VI-NEXT: v_or_b32_e32 v16, v62, v16
-; VI-NEXT: v_or_b32_e32 v15, v51, v15
-; VI-NEXT: v_add_u16_sdwa v38, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v49, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v36, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v48, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v34, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v39, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v50, 3, v8
+; VI-NEXT: v_add_u16_e32 v61, 3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v37
+; VI-NEXT: v_add_u16_sdwa v34, v6, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_add_u16_sdwa v19, v5, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v57, 3, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
-; VI-NEXT: v_add_u16_e32 v52, 3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
-; VI-NEXT: v_or_b32_e32 v10, v41, v10
-; VI-NEXT: v_or_b32_e32 v9, v43, v9
-; VI-NEXT: v_add_u16_sdwa v27, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v31, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
-; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
-; VI-NEXT: v_add_u16_e32 v59, 3, v6
+; VI-NEXT: v_add_u16_e32 v58, 3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v39
+; VI-NEXT: v_or_b32_e32 v10, v60, v10
+; VI-NEXT: v_or_b32_e32 v9, v61, v9
+; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v35, v4, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v40, v3, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v48, 3, v6
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
-; VI-NEXT: v_add_u16_e32 v61, 3, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
-; VI-NEXT: v_or_b32_e32 v8, v50, v8
-; VI-NEXT: v_or_b32_e32 v7, v52, v7
-; VI-NEXT: v_add_u16_e32 v58, 3, v14
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
-; VI-NEXT: v_add_u16_e32 v60, 3, v13
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; VI-NEXT: v_add_u16_e32 v54, 3, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; VI-NEXT: v_or_b32_e32 v8, v57, v8
+; VI-NEXT: v_or_b32_e32 v7, v58, v7
+; VI-NEXT: v_add_u16_sdwa v28, v12, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v33, v11, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
-; VI-NEXT: v_add_u16_e32 v46, 3, v4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
-; VI-NEXT: v_add_u16_e32 v56, 3, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
-; VI-NEXT: v_or_b32_e32 v6, v59, v6
-; VI-NEXT: v_or_b32_e32 v5, v61, v5
-; VI-NEXT: v_or_b32_e32 v14, v58, v14
-; VI-NEXT: v_or_b32_e32 v13, v60, v13
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_sdwa v49, v2, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v42, v1, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v50, 3, v4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v35
+; VI-NEXT: v_add_u16_e32 v52, 3, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
+; VI-NEXT: v_or_b32_e32 v6, v48, v6
+; VI-NEXT: v_or_b32_e32 v5, v54, v5
+; VI-NEXT: v_add_u16_e32 v63, 3, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; VI-NEXT: v_add_u16_e32 v38, 3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; VI-NEXT: v_add_u16_e32 v53, 3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
+; VI-NEXT: v_add_u16_e32 v51, 3, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v49
; VI-NEXT: v_add_u16_e32 v55, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
-; VI-NEXT: v_or_b32_e32 v4, v46, v4
-; VI-NEXT: v_or_b32_e32 v3, v56, v3
-; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v13
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v42
+; VI-NEXT: v_or_b32_e32 v4, v50, v4
+; VI-NEXT: v_or_b32_e32 v3, v52, v3
+; VI-NEXT: v_or_b32_e32 v12, v63, v12
+; VI-NEXT: v_or_b32_e32 v11, v38, v11
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; VI-NEXT: v_or_b32_e32 v2, v53, v2
+; VI-NEXT: v_or_b32_e32 v2, v51, v2
; VI-NEXT: v_or_b32_e32 v1, v55, v1
-; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
+; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v12
+; VI-NEXT: v_lshrrev_b32_e32 v59, 8, v11
+; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
-; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v11
-; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v10
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v1
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
-; VI-NEXT: v_bfe_u32 v1, v27, 8, 8
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v28, 8, 8
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v30, 8, 8
; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v9
+; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v32, 8, 8
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v7
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v6
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v30, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v34, 8, 8
; VI-NEXT: v_lshrrev_b32_e32 v16, 8, v16
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v15
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v14
-; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v13
+; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v10
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v5
-; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v3
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v2
; VI-NEXT: v_bfe_u32 v25, v26, 8, 8
-; VI-NEXT: v_bfe_u32 v54, v28, 8, 8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v1, v32, 8, 8
-; VI-NEXT: v_bfe_u32 v40, v34, 8, 8
-; VI-NEXT: v_bfe_u32 v18, v36, 8, 8
-; VI-NEXT: v_bfe_u32 v63, v38, 8, 8
-; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v62, v27, 8, 8
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: v_bfe_u32 v1, v35, 8, 8
+; VI-NEXT: v_bfe_u32 v47, v49, 8, 8
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: .LBB96_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v49, v24, s4
-; VI-NEXT: v_perm_b32 v2, v55, v57, s4
+; VI-NEXT: v_perm_b32 v1, v42, v24, s4
+; VI-NEXT: v_perm_b32 v2, v55, v18, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
-; VI-NEXT: v_perm_b32 v2, v38, v63, s4
+; VI-NEXT: v_perm_b32 v2, v49, v47, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v53, v44, s4
+; VI-NEXT: v_perm_b32 v1, v51, v46, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v48, v23, s4
-; VI-NEXT: v_perm_b32 v2, v56, v42, s4
+; VI-NEXT: v_perm_b32 v1, v40, v23, s4
+; VI-NEXT: v_perm_b32 v2, v52, v45, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v50, v44, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v46, v1, s4
+; VI-NEXT: v_perm_b32 v2, v35, v2, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v39, v22, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v19, v22, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v61, v1, s4
+; VI-NEXT: v_perm_b32 v1, v54, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v34, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v48, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v59, v1, s4
+; VI-NEXT: v_perm_b32 v2, v34, v2, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v37, v21, s4
+; VI-NEXT: v_perm_b32 v2, v39, v21, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v52, v1, s4
+; VI-NEXT: v_perm_b32 v1, v58, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v1, v50, v17, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v1, v57, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v35, v20, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v37, v20, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v43, v1, s4
+; VI-NEXT: v_perm_b32 v1, v61, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v41, v1, s4
+; VI-NEXT: v_perm_b32 v1, v60, v36, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v30, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v33, v19, s4
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v38, v59, s4
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_perm_b32 v2, v33, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v47, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v28, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v1, v63, v56, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v45, v1, s4
+; VI-NEXT: v_perm_b32 v2, v28, v2, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v31, v2, s4
-; VI-NEXT: v_perm_b32 v1, v60, v1, s4
+; VI-NEXT: v_perm_b32 v1, v41, v1, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v1, v58, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v27, v2, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v27, v62, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v53, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
-; VI-NEXT: v_perm_b32 v1, v51, v1, s4
+; VI-NEXT: v_perm_b32 v1, v17, v1, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v26, v25, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v1, v62, v1, s4
+; VI-NEXT: v_perm_b32 v1, v43, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -67188,735 +67708,761 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; kill: killed $vgpr6
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v16, v16, v13
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v43
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v3, v3, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v6, v6, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v39, v46, v9
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v29, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v23, v0, v29
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v14, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v20, v12
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v6, v12
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_or_b32_e32 v21, v21, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_or_b32_e32 v24, v20, v24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v3, v0, v36
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v6
+; SI-NEXT: v_alignbit_b32 v6, v48, v21, 16
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v39, v6, v20
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v27, v24, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v28, v39, v27, 16
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v37, v7, v5
-; SI-NEXT: v_or_b32_e32 v5, v0, v37
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v54, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
+; SI-NEXT: v_or_b32_e32 v6, v6, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_or_b32_e32 v26, v26, v24
+; SI-NEXT: v_or_b32_e32 v37, v6, v26
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v38, v42, v7
-; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v7, v0, v38
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v29, v24, v6
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v6, v37, v29, 16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v25, v44, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v30
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v9, v0, v39
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v20, v57, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v59, v11
-; SI-NEXT: v_or_b32_e32 v11, v0, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v26, v63, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v13, v0, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v0, v0, v34
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_or_b32_e32 v53, v31, v30
+; SI-NEXT: v_or_b32_e32 v36, v24, v53
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v61
+; SI-NEXT: v_or_b32_e32 v7, v24, v7
+; SI-NEXT: v_or_b32_e32 v35, v3, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v9
+; SI-NEXT: v_or_b32_e32 v3, v8, v3
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v17
+; SI-NEXT: v_or_b32_e32 v0, v8, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v4, v8
-; SI-NEXT: v_or_b32_e32 v15, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v34, v0, v8
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v8, v27, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
-; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v62
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_or_b32_e32 v32, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v14
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v22
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_or_b32_e32 v31, v4, v9
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v4, v10, v4
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v46, v35, v3, 16
+; SI-NEXT: v_alignbit_b32 v57, v34, v0, 16
+; SI-NEXT: v_alignbit_b32 v63, v32, v1, 16
+; SI-NEXT: v_alignbit_b32 v41, v36, v30, 16
+; SI-NEXT: v_alignbit_b32 v51, v31, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v24, v10, v21
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v18
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v58, v10, v27
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v61, v17, v19
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v19, v1, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_or_b32_e32 v1, v1, v51
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v47
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v43, v17, v25
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v31
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v48, v17, v20
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v45, v10, v29
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: v_or_b32_e32 v17, v1, v8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: v_or_b32_e32 v40, v10, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v54
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v52, v10, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v49, v3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v47
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v38, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v33, v0, v4
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v25, v10, v26
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: .LBB98_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v3, v27, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v15
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v12
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v22
+; SI-NEXT: v_or_b32_e32 v6, v12, v6
+; SI-NEXT: s_movk_i32 s7, 0x300
+; SI-NEXT: s_mov_b32 s6, 0x3000000
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v10
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v5
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v47
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v10
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v25
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v44
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v42
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v62
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
-; SI-NEXT: v_or_b32_e32 v0, v18, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v54
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v0, v62, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v31, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v7
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v50
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v61
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v46, v35, v52, 16
+; SI-NEXT: v_alignbit_b32 v57, v34, v49, 16
+; SI-NEXT: v_alignbit_b32 v63, v32, v38, 16
+; SI-NEXT: v_alignbit_b32 v51, v31, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v46, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v47, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v43
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v41, v36, v40, 16
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v36
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v6, v37, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v37
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
+; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v28, v39, v58, 16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v39
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
-; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v48, v24, 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v48
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v41
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v46
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v63
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v48
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v40
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -67933,25 +68479,24 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v52
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v35
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
-; SI-NEXT: v_or_b32_e32 v10, v10, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v32
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v14, v14, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -68436,17 +68981,17 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v19, v12
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:4
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
@@ -68461,55 +69006,32 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
+; GFX9-NEXT: v_mov_b32_e32 v19, v12
; GFX9-NEXT: s_waitcnt vmcnt(23)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(14)
-; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(13)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
-; GFX9-NEXT: s_waitcnt vmcnt(12)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -68521,35 +69043,41 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
-; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
-; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
+; GFX9-NEXT: s_waitcnt vmcnt(24)
+; GFX9-NEXT: v_perm_b32 v8, v30, v55, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v10, v57, v56, s6
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v41
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
-; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
-; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v11, v40, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v61, v60, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v13, v62, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v35, v37, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v15, v51, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr30
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr47
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr43
-; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr33
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr60
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -68585,11 +69113,11 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
-; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
+; GFX9-NEXT: v_perm_b32 v16, v32, v52, s6
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
@@ -68599,21 +69127,29 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v8, v46, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v9, v44, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v10, v36, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v11, v58, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v12, v33, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v14, v53, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v39, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; kill: killed $vgpr16
@@ -68655,86 +69191,93 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
-; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr48
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr44
+; GFX9-NEXT: ; implicit-def: $vgpr45
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr56
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB98_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB98_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
+; GFX9-NEXT: s_waitcnt vmcnt(18)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
-; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
+; GFX9-NEXT: v_add_u16_e32 v1, 3, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
-; GFX9-NEXT: s_waitcnt vmcnt(6)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v1
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
-; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
-; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
-; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v61
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v60
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
-; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
-; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v56
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
-; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
-; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
@@ -68757,23 +69300,28 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v2, 3, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v3, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v3
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
-; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
-; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
-; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
-; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
-; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
-; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
-; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
-; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
+; GFX9-NEXT: v_perm_b32 v8, v37, v8, s6
+; GFX9-NEXT: v_perm_b32 v9, v36, v9, s6
+; GFX9-NEXT: v_perm_b32 v10, v34, v10, s6
+; GFX9-NEXT: v_perm_b32 v11, v33, v11, s6
+; GFX9-NEXT: v_perm_b32 v12, v31, v12, s6
+; GFX9-NEXT: v_perm_b32 v13, v35, v13, s6
+; GFX9-NEXT: v_perm_b32 v14, v39, v14, s6
+; GFX9-NEXT: v_perm_b32 v15, v32, v15, s6
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -68870,89 +69418,75 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_3
@@ -68964,281 +69498,301 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v24, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v66, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v70, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v87, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v16, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v96, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v30, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v29, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v68, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v65, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v81, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v97, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v85, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v31.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v52, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v37.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v55, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v36.l
+; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v15.l, v15.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v83, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v16.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-TRUE16-NEXT: .LBB98_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v49.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v37.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v36.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v33.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v51.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v31.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v87.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v29.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v16.l, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v17.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
@@ -69248,76 +69802,52 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v15 :: v_dual_mov_b32 v32, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v14 :: v_dual_mov_b32 v52, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v13 :: v_dual_mov_b32 v50, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v11 :: v_dual_mov_b32 v34, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v54, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v3 :: v_dual_mov_b32 v48, v1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -69331,83 +69861,96 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v54, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v53, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v31, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v50, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v18, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v22, v23, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v24, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v26, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v66
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v71
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v65
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v67, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v82
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v69
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v83
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v112
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v102
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v99
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v87
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v103
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v113
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v116
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v85, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v100, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v114, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v20, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
@@ -69424,119 +69967,127 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v116
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v99, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v113, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v100, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v85, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v83
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v69
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v71, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v84, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v65
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v70
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v66, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v30, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
@@ -69557,35 +70108,36 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v53, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v52
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v51
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v50, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v54, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
@@ -69594,9 +70146,9 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
@@ -69624,10 +70176,10 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v68, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v85, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v15, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -72727,38 +73279,6 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v32f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -72775,40 +73295,44 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v15
+; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v13
+; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v12
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v11
+; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v10
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v9
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v8
+; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v7
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v6
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v5
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v4
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v3
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_and_b32_e32 v62, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v2
+; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v1
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v32
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v28
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v48, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v19
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v17
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v18
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v62, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v61, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v60, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v59, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v58, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v14
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -72819,228 +73343,292 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v31
-; SI-NEXT: v_alignbit_b32 v23, v1, v33, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v47
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34
-; SI-NEXT: v_alignbit_b32 v24, v23, v0, 16
-; SI-NEXT: v_alignbit_b32 v22, v3, v35, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v46
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
-; SI-NEXT: v_alignbit_b32 v25, v22, v0, 16
-; SI-NEXT: v_alignbit_b32 v21, v5, v37, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v44
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v38
-; SI-NEXT: v_alignbit_b32 v26, v21, v0, 16
-; SI-NEXT: v_alignbit_b32 v20, v7, v39, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v42
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v48
-; SI-NEXT: v_alignbit_b32 v27, v20, v0, 16
-; SI-NEXT: v_alignbit_b32 v19, v9, v49, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v41
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v50
-; SI-NEXT: v_alignbit_b32 v28, v19, v0, 16
-; SI-NEXT: v_alignbit_b32 v17, v11, v51, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v52
-; SI-NEXT: v_alignbit_b32 v29, v17, v0, 16
-; SI-NEXT: v_alignbit_b32 v14, v13, v54, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v43
-; SI-NEXT: v_alignbit_b32 v30, v14, v0, 16
-; SI-NEXT: v_alignbit_b32 v16, v15, v45, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v53
-; SI-NEXT: v_alignbit_b32 v32, v16, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v53
-; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v62, 16
-; SI-NEXT: v_alignbit_b32 v4, v4, v61, 16
-; SI-NEXT: v_alignbit_b32 v6, v6, v60, 16
-; SI-NEXT: v_alignbit_b32 v8, v8, v59, 16
-; SI-NEXT: v_alignbit_b32 v10, v10, v58, 16
-; SI-NEXT: v_alignbit_b32 v12, v12, v57, 16
-; SI-NEXT: v_alignbit_b32 v18, v18, v56, 16
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v33
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v23, v1, v0, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; SI-NEXT: v_alignbit_b32 v24, v23, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v35
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v36
+; SI-NEXT: v_alignbit_b32 v22, v3, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v62
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; SI-NEXT: v_alignbit_b32 v25, v22, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v37
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v20, v5, v4, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v61
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; SI-NEXT: v_alignbit_b32 v26, v20, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v39
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v48
+; SI-NEXT: v_alignbit_b32 v19, v7, v6, 16
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v60
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; SI-NEXT: v_alignbit_b32 v27, v19, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v18, v9, v8, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v58
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; SI-NEXT: v_alignbit_b32 v28, v18, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v53
+; SI-NEXT: v_alignbit_b32 v12, v11, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v59
+; SI-NEXT: v_alignbit_b32 v29, v12, v13, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v0, v0, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v57
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v45
+; SI-NEXT: v_alignbit_b32 v2, v2, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v56
+; SI-NEXT: v_alignbit_b32 v14, v13, v14, 16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
+; SI-NEXT: v_alignbit_b32 v4, v4, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v46
+; SI-NEXT: v_alignbit_b32 v30, v14, v15, 16
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v40
+; SI-NEXT: v_alignbit_b32 v6, v6, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v21, 1.0, v43
+; SI-NEXT: v_alignbit_b32 v8, v8, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v42
+; SI-NEXT: v_alignbit_b32 v16, v15, v16, 16
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v21
+; SI-NEXT: v_alignbit_b32 v10, v10, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_mul_f32_e32 v33, 1.0, v49
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32
+; SI-NEXT: v_alignbit_b32 v31, v16, v31, 16
+; SI-NEXT: v_alignbit_b32 v17, v17, v33, 16
+; SI-NEXT: v_alignbit_b32 v21, v21, v32, 16
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: .LBB102_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v63
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v59
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v46
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v62
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v44
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v61
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v42
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v60
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v41
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v58
; SI-NEXT: v_alignbit_b32 v6, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v59
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v47
; SI-NEXT: v_alignbit_b32 v8, v8, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v58
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v45
; SI-NEXT: v_alignbit_b32 v10, v10, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v53
-; SI-NEXT: v_alignbit_b32 v12, v12, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v56
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_alignbit_b32 v17, v12, v1, 16
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v43
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_alignbit_b32 v18, v14, v1, 16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v45
-; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; SI-NEXT: v_alignbit_b32 v21, v13, v1, 16
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v40
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
-; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v52
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v13
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v54
; SI-NEXT: v_alignbit_b32 v16, v15, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
-; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v52
; SI-NEXT: v_alignbit_b32 v14, v13, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v48
-; SI-NEXT: v_alignbit_b32 v17, v11, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v12, v11, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v38
-; SI-NEXT: v_alignbit_b32 v19, v9, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v18, v9, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
-; SI-NEXT: v_alignbit_b32 v20, v7, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
+; SI-NEXT: v_alignbit_b32 v19, v7, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34
-; SI-NEXT: v_alignbit_b32 v21, v5, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v35
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v20, v5, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v22, v3, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v23
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v23, v1, v23, 16
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; SI-NEXT: v_alignbit_b32 v24, v23, v24, 16
; SI-NEXT: v_alignbit_b32 v25, v22, v25, 16
-; SI-NEXT: v_alignbit_b32 v26, v21, v26, 16
-; SI-NEXT: v_alignbit_b32 v27, v20, v27, 16
-; SI-NEXT: v_alignbit_b32 v28, v19, v28, 16
-; SI-NEXT: v_alignbit_b32 v29, v17, v29, 16
+; SI-NEXT: v_alignbit_b32 v26, v20, v26, 16
+; SI-NEXT: v_alignbit_b32 v27, v19, v27, 16
+; SI-NEXT: v_alignbit_b32 v28, v18, v28, 16
+; SI-NEXT: v_alignbit_b32 v29, v12, v29, 16
; SI-NEXT: v_alignbit_b32 v30, v14, v30, 16
-; SI-NEXT: v_alignbit_b32 v32, v16, v32, 16
+; SI-NEXT: v_alignbit_b32 v31, v16, v31, 16
; SI-NEXT: .LBB102_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -73059,20 +73647,20 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v11, v17, v11
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v30
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
@@ -73084,27 +73672,27 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v3, v22, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v26
-; SI-NEXT: v_or_b32_e32 v5, v21, v5
+; SI-NEXT: v_or_b32_e32 v5, v20, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v27
-; SI-NEXT: v_or_b32_e32 v7, v20, v7
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
+; SI-NEXT: v_or_b32_e32 v7, v19, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
-; SI-NEXT: v_or_b32_e32 v9, v19, v9
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v28
+; SI-NEXT: v_or_b32_e32 v9, v18, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
; SI-NEXT: v_or_b32_e32 v12, v12, v17
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v31
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v0, v0, v24
; SI-NEXT: v_or_b32_e32 v2, v2, v23
; SI-NEXT: v_or_b32_e32 v4, v4, v22
-; SI-NEXT: v_or_b32_e32 v6, v6, v21
-; SI-NEXT: v_or_b32_e32 v8, v8, v20
-; SI-NEXT: v_or_b32_e32 v10, v10, v19
+; SI-NEXT: v_or_b32_e32 v6, v6, v20
+; SI-NEXT: v_or_b32_e32 v8, v8, v19
+; SI-NEXT: v_or_b32_e32 v10, v10, v18
; SI-NEXT: v_or_b32_e32 v14, v14, v17
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -76965,22 +77553,10 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
-; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -76999,33 +77575,47 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: ; implicit-def: $vgpr26
-; VI-NEXT: ; implicit-def: $vgpr22
-; VI-NEXT: ; implicit-def: $vgpr63
+; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: ; implicit-def: $vgpr55
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr54
-; VI-NEXT: ; implicit-def: $vgpr62
+; VI-NEXT: ; implicit-def: $vgpr51
+; VI-NEXT: ; implicit-def: $vgpr41
+; VI-NEXT: ; implicit-def: $vgpr63
+; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr21
+; VI-NEXT: ; implicit-def: $vgpr61
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr60
-; VI-NEXT: ; implicit-def: $vgpr53
+; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr58
-; VI-NEXT: ; implicit-def: $vgpr57
-; VI-NEXT: ; implicit-def: $vgpr61
+; VI-NEXT: ; implicit-def: $vgpr38
+; VI-NEXT: ; implicit-def: $vgpr62
+; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr47
-; VI-NEXT: ; implicit-def: $vgpr46
+; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
+; VI-NEXT: ; implicit-def: $vgpr45
+; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr44
+; VI-NEXT: ; implicit-def: $vgpr34
+; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr43
-; VI-NEXT: ; implicit-def: $vgpr56
+; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr42
-; VI-NEXT: ; implicit-def: $vgpr41
-; VI-NEXT: ; implicit-def: $vgpr45
-; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: ; implicit-def: $vgpr55
-; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr32
+; VI-NEXT: ; implicit-def: $vgpr46
+; VI-NEXT: ; implicit-def: $vgpr35
+; VI-NEXT: ; implicit-def: $vgpr31
+; VI-NEXT: ; implicit-def: $vgpr29
+; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr27
-; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr23
; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
@@ -77038,227 +77628,251 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v14
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v13
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
-; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[7:8]
-; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[5:6]
-; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
-; VI-NEXT: v_lshrrev_b32_e32 v27, 24, v16
-; VI-NEXT: v_lshrrev_b32_e32 v28, 24, v14
-; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v14
-; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v13
-; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v12
-; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v12
-; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v11
-; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v10
-; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v10
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v9
+; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
+; VI-NEXT: v_lshrrev_b32_e32 v28, 24, v16
+; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v16
+; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v15
+; VI-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v13
+; VI-NEXT: v_lshrrev_b32_e32 v46, 24, v12
+; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v12
+; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v12
+; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
+; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v11
+; VI-NEXT: v_lshrrev_b32_e32 v57, 24, v10
+; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v10
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v10
+; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v9
+; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v9
; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v8
-; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v8
-; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v7
-; VI-NEXT: v_lshrrev_b32_e32 v61, 24, v6
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v5
-; VI-NEXT: v_lshrrev_b32_e32 v53, 24, v4
-; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v2
-; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v2
-; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[1:2]
-; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v7
+; VI-NEXT: v_lshrrev_b32_e32 v62, 24, v6
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v6
+; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v5
+; VI-NEXT: v_lshrrev_b32_e32 v50, 24, v4
+; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
+; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v3
+; VI-NEXT: v_lshrrev_b32_e32 v41, 24, v2
+; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v54, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v1
+; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
+; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; VI-NEXT: .LBB104_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
-; VI-NEXT: v_add_f16_sdwa v49, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
+; VI-NEXT: v_add_f16_sdwa v51, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v51
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT: v_add_f16_sdwa v52, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v28, v2, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
+; VI-NEXT: v_add_f16_sdwa v55, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v29, v2, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v55
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_add_f16_sdwa v39, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v27, v1, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
+; VI-NEXT: v_add_f16_sdwa v48, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v28, v1, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT: v_add_f16_sdwa v51, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v23, v4, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v51
+; VI-NEXT: v_add_f16_sdwa v53, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v41, v4, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v53
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT: v_add_f16_sdwa v37, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v22, v3, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
+; VI-NEXT: v_add_f16_sdwa v38, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v40, v3, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v38
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_add_f16_sdwa v50, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v54, v6, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v50
+; VI-NEXT: v_add_f16_sdwa v52, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v26, v6, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_add_f16_sdwa v35, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v53, v5, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
+; VI-NEXT: v_add_f16_sdwa v36, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v25, v5, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v36
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_add_f16_sdwa v48, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v25, v8, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; VI-NEXT: v_add_f16_sdwa v49, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v23, v8, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_add_f16_sdwa v33, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v24, v7, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v33
+; VI-NEXT: v_add_f16_sdwa v34, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v22, v7, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v34
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_add_f16_sdwa v38, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v46, v10, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v38
+; VI-NEXT: v_add_f16_sdwa v39, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v47, v10, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_add_f16_sdwa v31, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v45, v9, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
+; VI-NEXT: v_add_f16_sdwa v32, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v46, v9, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
-; VI-NEXT: v_add_f16_sdwa v36, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v37, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v12, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v36
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
-; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v31, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v20, v11, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v41, v14, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v34
+; VI-NEXT: v_add_f16_sdwa v35, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v43, v14, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v40, v13, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
+; VI-NEXT: v_add_f16_sdwa v30, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v33, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v42, v13, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v33
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
-; VI-NEXT: v_or_b32_e32 v43, v16, v18
-; VI-NEXT: v_or_b32_e32 v42, v15, v17
-; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[42:43]
-; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[40:41]
-; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v43
+; VI-NEXT: v_or_b32_e32 v45, v16, v18
+; VI-NEXT: v_or_b32_e32 v44, v15, v17
+; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[44:45]
+; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[42:43]
+; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v45
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v42
+; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v44
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v20
+; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v43
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v42
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v20
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21]
-; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v41
-; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21
-; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[45:46]
-; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v46
-; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v25
-; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v24
-; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[24:25]
-; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v22
-; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[22:23]
-; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[53:54]
-; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v23
-; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[27:28]
-; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v40
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v45
-; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v54
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v53
-; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v28
-; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v27
-; VI-NEXT: v_bfe_u32 v27, v29, 8, 8
+; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v21
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v47
+; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[46:47]
+; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v23
+; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[22:23]
+; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v22
+; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v26
+; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v25
+; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[25:26]
+; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[40:41]
+; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[28:29]
+; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v46
+; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v41
+; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v40
+; VI-NEXT: v_lshrrev_b32_e32 v54, 8, v29
+; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v28
; VI-NEXT: v_bfe_u32 v28, v30, 8, 8
-; VI-NEXT: v_bfe_u32 v45, v31, 8, 8
-; VI-NEXT: v_bfe_u32 v56, v33, 8, 8
-; VI-NEXT: v_bfe_u32 v59, v35, 8, 8
-; VI-NEXT: v_bfe_u32 v61, v37, 8, 8
-; VI-NEXT: v_bfe_u32 v53, v39, 8, 8
-; VI-NEXT: v_bfe_u32 v54, v49, 8, 8
+; VI-NEXT: v_bfe_u32 v29, v31, 8, 8
+; VI-NEXT: v_bfe_u32 v46, v32, 8, 8
+; VI-NEXT: v_bfe_u32 v57, v34, 8, 8
+; VI-NEXT: v_bfe_u32 v59, v36, 8, 8
+; VI-NEXT: v_bfe_u32 v62, v38, 8, 8
+; VI-NEXT: v_bfe_u32 v50, v48, 8, 8
+; VI-NEXT: v_bfe_u32 v41, v51, 8, 8
; VI-NEXT: .LBB104_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v22, v52, v22, s4
-; VI-NEXT: v_perm_b32 v1, v1, v26, s4
+; VI-NEXT: v_perm_b32 v22, v55, v24, s4
+; VI-NEXT: v_perm_b32 v1, v1, v40, s4
; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_or_b32_e32 v1, v1, v22
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v49, v54, s4
-; VI-NEXT: v_perm_b32 v2, v2, v63, s4
+; VI-NEXT: v_perm_b32 v1, v51, v41, s4
+; VI-NEXT: v_perm_b32 v2, v2, v54, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v51, v21, s4
-; VI-NEXT: v_perm_b32 v2, v3, v62, s4
+; VI-NEXT: v_perm_b32 v1, v53, v21, s4
+; VI-NEXT: v_perm_b32 v2, v3, v63, s4
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v53, s4
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_perm_b32 v2, v48, v50, s4
+; VI-NEXT: v_perm_b32 v1, v4, v61, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v50, v25, s4
-; VI-NEXT: v_perm_b32 v1, v5, v58, s4
+; VI-NEXT: v_perm_b32 v2, v52, v26, s4
+; VI-NEXT: v_perm_b32 v1, v5, v60, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v37, v61, s4
-; VI-NEXT: v_perm_b32 v1, v6, v57, s4
+; VI-NEXT: v_perm_b32 v2, v38, v62, s4
+; VI-NEXT: v_perm_b32 v1, v6, v58, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v48, v24, s4
-; VI-NEXT: v_perm_b32 v1, v7, v47, s4
+; VI-NEXT: v_perm_b32 v2, v49, v23, s4
+; VI-NEXT: v_perm_b32 v1, v7, v56, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v59, s4
-; VI-NEXT: v_perm_b32 v1, v8, v46, s4
+; VI-NEXT: v_perm_b32 v2, v36, v59, s4
+; VI-NEXT: v_perm_b32 v1, v8, v47, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v38, v20, s4
-; VI-NEXT: v_perm_b32 v1, v9, v44, s4
+; VI-NEXT: v_perm_b32 v2, v39, v20, s4
+; VI-NEXT: v_perm_b32 v1, v9, v45, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v56, s4
-; VI-NEXT: v_perm_b32 v1, v10, v43, s4
+; VI-NEXT: v_perm_b32 v2, v34, v57, s4
+; VI-NEXT: v_perm_b32 v1, v10, v44, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v19, s4
-; VI-NEXT: v_perm_b32 v1, v11, v42, s4
+; VI-NEXT: v_perm_b32 v2, v37, v19, s4
+; VI-NEXT: v_perm_b32 v1, v11, v43, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v31, v45, s4
-; VI-NEXT: v_perm_b32 v1, v12, v41, s4
+; VI-NEXT: v_perm_b32 v2, v32, v46, s4
+; VI-NEXT: v_perm_b32 v1, v12, v42, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v18, s4
-; VI-NEXT: v_perm_b32 v1, v13, v40, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v35, v18, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v13, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v28, s4
-; VI-NEXT: v_perm_b32 v1, v14, v55, s4
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v2, v31, v29, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v32, v17, s4
+; VI-NEXT: v_perm_b32 v2, v33, v17, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v15, v1, s4
@@ -77266,7 +77880,7 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v2, v29, v27, s4
+; VI-NEXT: v_perm_b32 v2, v30, v28, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -79946,735 +80560,761 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; kill: killed $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; kill: killed $vgpr6
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v16, v16, v13
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v43
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v3, v3, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v30
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: v_or_b32_e32 v6, v6, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v39, v46, v9
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v29, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v23, v0, v29
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v20, v12
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v6, v12
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v14, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_or_b32_e32 v21, v21, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
+; SI-NEXT: v_or_b32_e32 v24, v20, v24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v6
+; SI-NEXT: v_alignbit_b32 v6, v48, v21, 16
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v39, v6, v20
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v27, v24, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v28, v39, v27, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v3, v0, v36
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
+; SI-NEXT: v_or_b32_e32 v6, v6, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_or_b32_e32 v26, v26, v24
+; SI-NEXT: v_or_b32_e32 v37, v6, v26
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24
+; SI-NEXT: v_or_b32_e32 v29, v24, v6
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v6, v37, v29, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_or_b32_e32 v24, v24, v30
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_or_b32_e32 v53, v31, v30
+; SI-NEXT: v_or_b32_e32 v36, v24, v53
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v30, 24, v30
+; SI-NEXT: v_or_b32_e32 v30, v30, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v61
+; SI-NEXT: v_or_b32_e32 v7, v24, v7
+; SI-NEXT: v_or_b32_e32 v35, v3, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v9
+; SI-NEXT: v_or_b32_e32 v3, v8, v3
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v17
+; SI-NEXT: v_or_b32_e32 v0, v8, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v59
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v37, v7, v5
-; SI-NEXT: v_or_b32_e32 v5, v0, v37
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v34, v0, v8
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v54, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v62
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_or_b32_e32 v32, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v14
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v22
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_or_b32_e32 v31, v4, v9
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v19
+; SI-NEXT: v_or_b32_e32 v4, v10, v4
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v46, v35, v3, 16
+; SI-NEXT: v_alignbit_b32 v57, v34, v0, 16
+; SI-NEXT: v_alignbit_b32 v63, v32, v1, 16
+; SI-NEXT: v_alignbit_b32 v41, v36, v30, 16
+; SI-NEXT: v_alignbit_b32 v51, v31, v4, 16
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v38, v42, v7
-; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v7, v0, v38
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v24, v10, v21
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v25, v44, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v58, v10, v27
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v45, v10, v29
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v40, v10, v30
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v54
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v52, v10, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v49, v3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v47
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v38, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v33, v0, v4
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v9, v0, v39
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v20, v57, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v59, v11
-; SI-NEXT: v_or_b32_e32 v11, v0, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v26, v63, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v13, v0, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
-; SI-NEXT: v_or_b32_e32 v0, v0, v34
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v4, v8
-; SI-NEXT: v_or_b32_e32 v15, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v8, v27, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
-; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v18
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v61, v17, v19
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v19, v1, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_or_b32_e32 v1, v1, v51
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v47
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v43, v17, v25
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v31
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v48, v17, v20
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: v_or_b32_e32 v17, v1, v8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v25, v10, v26
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: .LBB106_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v3, v27, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v15
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v12
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v22
+; SI-NEXT: v_or_b32_e32 v6, v12, v6
+; SI-NEXT: s_movk_i32 s7, 0x300
+; SI-NEXT: s_mov_b32 s6, 0x3000000
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v23
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v10
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v5
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v47
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v14
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v10
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v25
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v16
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v2
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v44
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v42
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v62
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
-; SI-NEXT: v_or_b32_e32 v0, v18, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v60
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v54
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v0, v62, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v31, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v7
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v50
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v61
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v46, v35, v52, 16
+; SI-NEXT: v_alignbit_b32 v57, v34, v49, 16
+; SI-NEXT: v_alignbit_b32 v63, v32, v38, 16
+; SI-NEXT: v_alignbit_b32 v51, v31, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v46, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v47, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v43
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v41, v36, v40, 16
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v36
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v54, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v6, v37, v45, 16
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v37
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
+; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v28, v39, v58, 16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v39
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
-; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v48, v24, 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v48
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v41
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v46
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v63
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v48
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v40
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -80691,25 +81331,24 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v52
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v35
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
-; SI-NEXT: v_or_b32_e32 v10, v10, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v34
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v32
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v14, v14, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -81194,17 +81833,17 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v19, v12
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:4
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
@@ -81219,55 +81858,32 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
+; GFX9-NEXT: v_mov_b32_e32 v19, v12
; GFX9-NEXT: s_waitcnt vmcnt(23)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(14)
-; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(13)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
-; GFX9-NEXT: s_waitcnt vmcnt(12)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -81279,35 +81895,41 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
-; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
-; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
+; GFX9-NEXT: s_waitcnt vmcnt(24)
+; GFX9-NEXT: v_perm_b32 v8, v30, v55, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v10, v57, v56, s6
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v41
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
-; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
-; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v11, v40, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v61, v60, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v13, v62, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v35, v37, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v15, v51, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr30
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr47
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr43
-; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr33
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr60
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -81343,11 +81965,11 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
-; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
+; GFX9-NEXT: v_perm_b32 v16, v32, v52, s6
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
@@ -81357,21 +81979,29 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v8, v46, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v9, v44, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v10, v36, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v11, v58, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v12, v33, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v14, v53, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v39, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; kill: killed $vgpr16
@@ -81413,86 +82043,93 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
-; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr48
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr44
+; GFX9-NEXT: ; implicit-def: $vgpr45
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr56
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB106_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB106_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
+; GFX9-NEXT: s_waitcnt vmcnt(18)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
-; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
+; GFX9-NEXT: v_add_u16_e32 v1, 3, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
-; GFX9-NEXT: s_waitcnt vmcnt(6)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v1
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
-; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
-; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
-; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v61
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v60
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
-; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
-; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v56
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
-; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
-; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
@@ -81515,23 +82152,28 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v2, 3, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v3, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v3
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
-; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
-; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
-; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
-; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
-; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
-; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
-; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
-; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
+; GFX9-NEXT: v_perm_b32 v8, v37, v8, s6
+; GFX9-NEXT: v_perm_b32 v9, v36, v9, s6
+; GFX9-NEXT: v_perm_b32 v10, v34, v10, s6
+; GFX9-NEXT: v_perm_b32 v11, v33, v11, s6
+; GFX9-NEXT: v_perm_b32 v12, v31, v12, s6
+; GFX9-NEXT: v_perm_b32 v13, v35, v13, s6
+; GFX9-NEXT: v_perm_b32 v14, v39, v14, s6
+; GFX9-NEXT: v_perm_b32 v15, v32, v15, s6
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -81628,89 +82270,75 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_3
@@ -81722,281 +82350,301 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v24, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v66, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v70, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v87, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v16, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v96, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v30, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v29, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v68, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v65, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v81, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v97, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v85, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v31.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v52, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v37.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v55, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v36.l
+; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v15.l, v15.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v83, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v16.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-TRUE16-NEXT: .LBB106_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v49.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v37.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v36.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v33.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v51.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v31.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v87.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v29.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v16.l, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v17.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
@@ -82006,76 +82654,52 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v15 :: v_dual_mov_b32 v32, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v14 :: v_dual_mov_b32 v52, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v13 :: v_dual_mov_b32 v50, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v11 :: v_dual_mov_b32 v34, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v54, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v3 :: v_dual_mov_b32 v48, v1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -82089,83 +82713,96 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v54, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v53, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v31, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v50, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v18, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v22, v23, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v24, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v26, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v66
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v71
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v65
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v67, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v82
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v69
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v83
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v112
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v102
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v99
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v87
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v103
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v113
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v116
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v85, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v100, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v114, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v20, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
@@ -82182,119 +82819,127 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v116
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v99, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v113, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v100, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v85, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v83
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v69
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v71, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v84, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v65
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v70
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v66, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v30, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
@@ -82315,35 +82960,36 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v53, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v52
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v51
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v50, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v54, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
@@ -82352,9 +82998,9 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
@@ -82382,10 +83028,10 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v68, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v85, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v15, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -84397,17 +85043,8 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v32bf16_to_v64i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v29, 1.0, v1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
@@ -84455,42 +85092,19 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v2
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -84507,513 +85121,576 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v27
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
-; SI-NEXT: v_mul_f32_e32 v27, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v32, 1.0, v31
-; SI-NEXT: v_mul_f32_e32 v33, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
-; SI-NEXT: v_mul_f32_e32 v31, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v36, 1.0, v34
-; SI-NEXT: v_mul_f32_e32 v38, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
-; SI-NEXT: v_mul_f32_e32 v34, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v49, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v51, 1.0, v7
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v39, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v54, 1.0, v37
-; SI-NEXT: v_mul_f32_e32 v55, 1.0, v9
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
-; SI-NEXT: v_mul_f32_e32 v53, 1.0, v10
-; SI-NEXT: v_mul_f32_e32 v42, 1.0, v35
-; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
-; SI-NEXT: v_mul_f32_e32 v35, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v41, 1.0, v12
-; SI-NEXT: v_mul_f32_e32 v45, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v46, 1.0, v13
-; SI-NEXT: v_mul_f32_e32 v52, 1.0, v20
-; SI-NEXT: v_mul_f32_e32 v44, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v56, 1.0, v19
+; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v16
+; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v15
; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_mul_f32_e32 v57, 1.0, v15
-; SI-NEXT: v_mul_f32_e32 v40, 1.0, v18
-; SI-NEXT: v_mul_f32_e32 v47, 1.0, v16
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v15
+; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v14
+; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v13
+; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v12
+; SI-NEXT: v_and_b32_e32 v44, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v11
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v10
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v9
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v7
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v6
+; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v5
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v4
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: ; kill: killed $vgpr1
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr58
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB108_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_alignbit_b32 v48, v1, v29, 16
-; SI-NEXT: v_alignbit_b32 v50, v37, v27, 16
-; SI-NEXT: v_alignbit_b32 v1, v50, v48, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v25, 1.0, v26
+; SI-NEXT: v_alignbit_b32 v23, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v25
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27
+; SI-NEXT: v_alignbit_b32 v24, v22, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v24, v23, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v50, v48, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v24, v23, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v50, v48, 8
+; SI-NEXT: v_alignbit_b32 v1, v24, v23, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; SI-NEXT: v_alignbit_b32 v23, v1, v33, 16
-; SI-NEXT: v_alignbit_b32 v21, v19, v31, 16
-; SI-NEXT: v_alignbit_b32 v1, v21, v23, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v21, v23, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v21, v23, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28
+; SI-NEXT: v_alignbit_b32 v20, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v26
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29
+; SI-NEXT: v_alignbit_b32 v21, v19, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v21, v20, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v25
-; SI-NEXT: v_alignbit_b32 v17, v1, v38, 16
-; SI-NEXT: v_alignbit_b32 v18, v16, v34, 16
-; SI-NEXT: v_alignbit_b32 v1, v18, v17, 24
+; SI-NEXT: v_alignbit_b32 v1, v21, v20, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v18, v17, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v18, v17, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v21, v20, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
-; SI-NEXT: v_alignbit_b32 v14, v1, v51, 16
-; SI-NEXT: v_alignbit_b32 v15, v13, v39, 16
-; SI-NEXT: v_alignbit_b32 v1, v15, v14, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v49
+; SI-NEXT: v_mul_f32_e32 v27, 1.0, v30
+; SI-NEXT: v_alignbit_b32 v16, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v27
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31
+; SI-NEXT: v_alignbit_b32 v18, v17, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v18, v16, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v15, v14, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v18, v16, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v15, v14, 8
+; SI-NEXT: v_alignbit_b32 v1, v18, v16, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v30
-; SI-NEXT: v_alignbit_b32 v11, v1, v55, 16
-; SI-NEXT: v_alignbit_b32 v12, v10, v53, 16
-; SI-NEXT: v_alignbit_b32 v1, v12, v11, 24
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v34
+; SI-NEXT: v_alignbit_b32 v13, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v28
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35
+; SI-NEXT: v_alignbit_b32 v15, v14, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v15, v13, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v15, v13, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v12, v11, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v15, v13, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v12, v11, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v29, 1.0, v38
+; SI-NEXT: v_alignbit_b32 v10, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v29
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39
+; SI-NEXT: v_alignbit_b32 v12, v11, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v12, v10, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v35
-; SI-NEXT: v_alignbit_b32 v8, v1, v43, 16
-; SI-NEXT: v_alignbit_b32 v9, v7, v41, 16
-; SI-NEXT: v_alignbit_b32 v1, v9, v8, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v12, v10, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v9, v8, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v12, v10, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v9, v8, 8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v45
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v50
+; SI-NEXT: v_alignbit_b32 v7, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51
+; SI-NEXT: v_alignbit_b32 v9, v8, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v9, v7, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v9, v7, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v52
-; SI-NEXT: v_alignbit_b32 v5, v1, v46, 16
-; SI-NEXT: v_alignbit_b32 v6, v4, v44, 16
-; SI-NEXT: v_alignbit_b32 v1, v6, v5, 24
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v9, v7, 8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v6, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v47
+; SI-NEXT: v_mul_f32_e32 v31, 1.0, v54
+; SI-NEXT: v_alignbit_b32 v4, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v31
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55
+; SI-NEXT: v_alignbit_b32 v6, v5, v1, 16
+; SI-NEXT: v_alignbit_b32 v1, v6, v4, 24
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v6, v5, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v6, v4, 16
+; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v26
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
-; SI-NEXT: v_alignbit_b32 v2, v1, v57, 16
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
-; SI-NEXT: v_alignbit_b32 v3, v1, v47, 16
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 24
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v6, v4, 8
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v28
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 8
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v18
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v15
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v57
+; SI-NEXT: v_mul_f32_e32 v32, 1.0, v42
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v26
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v29
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v32
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v43
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v15
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v30
+; SI-NEXT: v_alignbit_b32 v3, v2, v3, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v30
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v32
+; SI-NEXT: v_alignbit_b32 v33, v3, v1, 24
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v35
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v9
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v40
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v33, v3, v1, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v9
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v6
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v6
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v33, v3, v1, 8
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v3
-; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v50
-; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v24
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v3
+; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v24
; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v25
-; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v52
+; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v27
+; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v31
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v12
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: .LBB108_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB108_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v32
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v33
+; SI-NEXT: v_mul_f32_e32 v23, 1.0, v32
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v33
+; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v36
+; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v37
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; SI-NEXT: v_alignbit_b32 v23, v23, v22, 16
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v27
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v48
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; SI-NEXT: v_alignbit_b32 v23, v20, v19, 16
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v31
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v24
-; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v19
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; SI-NEXT: v_alignbit_b32 v21, v19, v20, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v29
-; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v22
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v26
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v49
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_alignbit_b32 v20, v20, v19, 16
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v29
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; SI-NEXT: v_alignbit_b32 v48, v28, v20, 16
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v27
-; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v36
-; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v38
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; SI-NEXT: v_alignbit_b32 v50, v37, v20, 16
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v22
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v52
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_alignbit_b32 v20, v50, v48, 24
-; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v49
-; SI-NEXT: v_alignbit_b32 v17, v17, v16, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v34
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v50, v48, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v51
+; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v19
+; SI-NEXT: v_mul_f32_e32 v19, 1.0, v28
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v25
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v53
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v31
+; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; SI-NEXT: v_alignbit_b32 v24, v22, v24, 16
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v25
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v19
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v50, v48, 8
+; SI-NEXT: v_alignbit_b32 v26, v24, v23, 24
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v40
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v21, v23, 24
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v54
-; SI-NEXT: v_alignbit_b32 v14, v14, v13, 16
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v39
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v25
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v21, v23, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v55
+; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v17
+; SI-NEXT: v_mul_f32_e32 v17, 1.0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v28
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v24, v23, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v41
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v35
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; SI-NEXT: v_alignbit_b32 v21, v19, v21, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v24, v23, 8
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v26
-; SI-NEXT: v_alignbit_b32 v18, v16, v18, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v17
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v21, v23, 8
+; SI-NEXT: v_alignbit_b32 v26, v21, v20, 24
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v44
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v13
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v18, v17, 24
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
-; SI-NEXT: v_alignbit_b32 v11, v11, v10, 16
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v53
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v18, v17, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v43
+; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v14
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v30
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v21, v20, 16
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v45
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v39
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; SI-NEXT: v_alignbit_b32 v18, v17, v18, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v21, v20, 8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v30
-; SI-NEXT: v_alignbit_b32 v15, v13, v15, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v14
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v18, v17, 8
+; SI-NEXT: v_alignbit_b32 v26, v18, v16, 24
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v46
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v10
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v15, v14, 24
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v45
-; SI-NEXT: v_alignbit_b32 v8, v8, v7, 16
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v41
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v30
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v15, v14, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v46
+; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v11
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v38
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v34
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v18, v16, 16
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v51
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; SI-NEXT: v_alignbit_b32 v15, v14, v15, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v18, v16, 8
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v35
-; SI-NEXT: v_alignbit_b32 v12, v10, v12, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_add_f32_e32 v38, 0x40c00000, v11
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v15, v14, 8
+; SI-NEXT: v_alignbit_b32 v26, v15, v13, 24
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v56
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v7
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v12, v11, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v56
-; SI-NEXT: v_alignbit_b32 v5, v5, v4, 16
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v44
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v35
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v12, v11, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
+; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v50
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v38
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v15, v13, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v55
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; SI-NEXT: v_alignbit_b32 v12, v11, v12, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v15, v13, 8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v52
-; SI-NEXT: v_alignbit_b32 v9, v7, v9, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_add_f32_e32 v50, 0x40c00000, v8
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v12, v11, 8
+; SI-NEXT: v_alignbit_b32 v26, v12, v10, 24
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_add_f32_e32 v52, 0x40c00000, v4
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v54
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v50
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v12, v10, 16
+; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v43
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v9, v8, 24
-; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v52
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v12, v10, 8
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_add_f32_e32 v54, 0x40c00000, v5
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v9, v8, 16
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v40
-; SI-NEXT: v_alignbit_b32 v6, v4, v6, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v9, v7, 24
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v42
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v54
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v26, v9, v7, 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_alignbit_b32 v6, v5, v6, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v9, v8, 8
-; SI-NEXT: v_add_f32_e32 v40, 0x40c00000, v1
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v9, v7, 8
+; SI-NEXT: v_add_f32_e32 v42, 0x40c00000, v2
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v6, v5, 24
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v6, v4, 24
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v42
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v6, v5, 16
-; SI-NEXT: v_alignbit_b32 v3, v1, v3, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v6, v4, 16
+; SI-NEXT: v_alignbit_b32 v3, v2, v3, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v6, v5, 8
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v6, v4, 8
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 24
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v3, v1, 24
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 16
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v3, v1, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v20, v3, v2, 8
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v26, v3, v1, 8
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v18
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v18
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v15
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v15
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v22
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v26
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v34
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v30
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v38
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v35
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v50
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v40
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v42
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v9
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v9
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v6
-; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v50
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v6
+; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v24
; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v24
-; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v25
-; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v52
+; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v28
+; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v30
+; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v54
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v12
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v3
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v3
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: .LBB108_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v48
-; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
+; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
-; SI-NEXT: v_or_b32_e32 v22, v22, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26
+; SI-NEXT: v_or_b32_e32 v23, v23, v26
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_or_b32_e32 v24, v25, v24
-; SI-NEXT: v_or_b32_e32 v22, v22, v24
-; SI-NEXT: buffer_store_dword v22, v0, s[0:3], 0 offen
+; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_or_b32_e32 v23, v23, v26
+; SI-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v50
+; SI-NEXT: v_and_b32_e32 v23, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v63
-; SI-NEXT: v_or_b32_e32 v22, v22, v24
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v37
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v20, v20, v24
-; SI-NEXT: v_or_b32_e32 v20, v22, v20
-; SI-NEXT: v_add_i32_e32 v22, vcc, 4, v0
-; SI-NEXT: buffer_store_dword v20, v22, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v25
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v23, vcc, 4, v0
+; SI-NEXT: buffer_store_dword v22, v23, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
; SI-NEXT: v_or_b32_e32 v20, v20, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
@@ -85035,184 +85712,184 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v20, vcc, 12, v0
; SI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
-; SI-NEXT: v_or_b32_e32 v17, v17, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v19
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_or_b32_e32 v17, v17, v19
+; SI-NEXT: v_or_b32_e32 v16, v16, v19
; SI-NEXT: v_add_i32_e32 v19, vcc, 16, v0
-; SI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v16, v19, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v18
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: v_or_b32_e32 v16, v16, v18
; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v60
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_add_i32_e32 v17, vcc, 20, v0
; SI-NEXT: buffer_store_dword v16, v17, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; SI-NEXT: v_or_b32_e32 v14, v14, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: v_or_b32_e32 v14, v14, v16
+; SI-NEXT: v_or_b32_e32 v13, v13, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 24, v0
-; SI-NEXT: buffer_store_dword v14, v16, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v13, v16, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v15
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_or_b32_e32 v13, v13, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
-; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 28, v0
; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
-; SI-NEXT: v_or_b32_e32 v11, v11, v13
+; SI-NEXT: v_or_b32_e32 v10, v10, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_or_b32_e32 v11, v11, v13
+; SI-NEXT: v_or_b32_e32 v10, v10, v13
; SI-NEXT: v_add_i32_e32 v13, vcc, 32, v0
-; SI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v10, v13, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v12
; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_or_b32_e32 v10, v10, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
-; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_add_i32_e32 v11, vcc, 36, v0
; SI-NEXT: buffer_store_dword v10, v11, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
+; SI-NEXT: v_or_b32_e32 v7, v7, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 40, v0
-; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v7, v10, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v9
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_or_b32_e32 v7, v7, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
-; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 44, v0
; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
-; SI-NEXT: v_or_b32_e32 v5, v5, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_or_b32_e32 v5, v5, v7
+; SI-NEXT: v_or_b32_e32 v4, v4, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 48, v0
-; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v4, v7, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_or_b32_e32 v4, v4, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v58
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 52, v0
; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_or_b32_e32 v1, v1, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0
-; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -90722,325 +91399,306 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:28
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; kill: killed $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
-; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v29
-; SI-NEXT: ; kill: killed $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; kill: killed $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:44
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; kill: killed $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v1
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v8
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v9
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v14
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v17
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v24
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:40
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v28
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v13, v13, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v11, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v21, v14, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v36, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v23, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
+; SI-NEXT: v_or_b32_e32 v14, v14, v18
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v38, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v11, v38
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v50, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v39, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v52, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v53, v36, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v49, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v11, v51
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v41, v48, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v44, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v45, v49, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
+; SI-NEXT: v_or_b32_e32 v14, v14, v18
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v11, v42
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v51, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v57, v54, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v52, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v58, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v25
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v53, v18, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v61, v40, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
+; SI-NEXT: v_or_b32_e32 v14, v14, v18
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v48
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v31, v47, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v32, v13, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v20
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v3, v13
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v33, v0, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v30, v26, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v55, v18, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v63
+; SI-NEXT: v_or_b32_e32 v40, v14, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v46
+; SI-NEXT: v_or_b32_e32 v41, v14, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v15
+; SI-NEXT: v_or_b32_e32 v2, v2, v6
+; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v60
+; SI-NEXT: v_or_b32_e32 v43, v6, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v44, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v45
+; SI-NEXT: v_or_b32_e32 v57, v2, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v7
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v59
+; SI-NEXT: v_or_b32_e32 v31, v2, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; SI-NEXT: v_or_b32_e32 v32, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
+; SI-NEXT: v_or_b32_e32 v14, v1, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v24, v16, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v19
+; SI-NEXT: v_or_b32_e32 v18, v1, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v63
-; SI-NEXT: v_or_b32_e32 v28, v3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v30
+; SI-NEXT: v_or_b32_e32 v23, v1, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v15, v1, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v27
+; SI-NEXT: v_or_b32_e32 v34, v1, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v29
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v8, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v25
+; SI-NEXT: v_or_b32_e32 v21, v1, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
@@ -91080,383 +91738,427 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v18
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v11, v59, v11
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v11
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v2
-; SI-NEXT: v_or_b32_e32 v4, v8, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v63
-; SI-NEXT: v_or_b32_e32 v4, v8, v4
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v56
-; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v29
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v20
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v25
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
+; SI-NEXT: v_or_b32_e32 v9, v9, v12
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v24
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v30
+; SI-NEXT: v_or_b32_e32 v9, v12, v9
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v26
+; SI-NEXT: s_movk_i32 s7, 0x300
+; SI-NEXT: s_mov_b32 s6, 0x3000000
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v9, v9, v12
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v3
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v17
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v19
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v1, v1, v8
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v6, v16, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_or_b32_e32 v3, v8, v3
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v61
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v59
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v7
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v3
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v47
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v5, v26, v5
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v25
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v62
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v60
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v37
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v63
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v56
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v60, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v46
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v6
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v2
+; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v5
+; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v1
+; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
+; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v8
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v21
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v48
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v47, v7
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v6
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v2
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v11, v48, v11
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v40, v8
-; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v7
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; SI-NEXT: v_or_b32_e32 v3, v7, v3
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v9
+; SI-NEXT: v_or_b32_e32 v3, v7, v3
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v7
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v7
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v42, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v8
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v49, v10
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v51, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v11
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v11
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v12
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v14
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_or_b32_e32 v12, v36, v12
-; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v12
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v13
+; SI-NEXT: v_or_b32_e32 v3, v9, v3
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
+; SI-NEXT: v_or_b32_e32 v3, v13, v3
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v13, v13, v15
+; SI-NEXT: v_or_b32_e32 v3, v13, v3
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v23
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v55
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v44
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v46
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v58
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v62
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v35
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v12
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v37
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v40
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v42
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v44
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v58
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v23
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v36
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v38
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v49
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v51
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v53
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v57
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v55
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v61
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v41
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v43
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v57
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -91473,30 +92175,23 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v11
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v32
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v31
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v30
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v14
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v33
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v32
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v18
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v33
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v28
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v21
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -91982,17 +92677,17 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
-; GFX9-NEXT: v_mov_b32_e32 v19, v12
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:4
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
@@ -92007,55 +92702,32 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:44
+; GFX9-NEXT: v_mov_b32_e32 v19, v12
; GFX9-NEXT: s_waitcnt vmcnt(23)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
-; GFX9-NEXT: s_waitcnt vmcnt(21)
-; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
-; GFX9-NEXT: s_waitcnt vmcnt(20)
-; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
-; GFX9-NEXT: s_waitcnt vmcnt(14)
-; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(13)
-; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
-; GFX9-NEXT: s_waitcnt vmcnt(12)
-; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -92067,35 +92739,41 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
-; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
-; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
+; GFX9-NEXT: s_waitcnt vmcnt(24)
+; GFX9-NEXT: v_perm_b32 v8, v30, v55, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v10, v57, v56, s6
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v41
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
-; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
-; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v11, v40, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v12, v61, v60, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v13, v62, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_perm_b32 v14, v35, v37, s6
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v15, v51, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; implicit-def: $vgpr23
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr30
-; GFX9-NEXT: ; implicit-def: $vgpr36
-; GFX9-NEXT: ; implicit-def: $vgpr47
-; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr42
-; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr43
-; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
-; GFX9-NEXT: ; implicit-def: $vgpr34
-; GFX9-NEXT: ; implicit-def: $vgpr45
-; GFX9-NEXT: ; implicit-def: $vgpr33
+; GFX9-NEXT: ; implicit-def: $vgpr56
+; GFX9-NEXT: ; implicit-def: $vgpr40
+; GFX9-NEXT: ; implicit-def: $vgpr41
+; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr60
+; GFX9-NEXT: ; implicit-def: $vgpr62
+; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr35
-; GFX9-NEXT: ; implicit-def: $vgpr39
+; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr51
+; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -92131,11 +92809,11 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
-; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
+; GFX9-NEXT: v_perm_b32 v16, v32, v52, s6
; GFX9-NEXT: ; implicit-def: $vgpr19
; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr52
-; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
@@ -92145,21 +92823,29 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
-; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v8, v46, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
-; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v9, v44, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v10, v36, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
-; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v11, v58, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v12, v33, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
-; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v14, v53, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
-; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v15, v39, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
; GFX9-NEXT: ; implicit-def: $vgpr16
; GFX9-NEXT: ; kill: killed $vgpr16
@@ -92201,86 +92887,93 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr29
-; GFX9-NEXT: ; implicit-def: $vgpr59
-; GFX9-NEXT: ; implicit-def: $vgpr60
-; GFX9-NEXT: ; implicit-def: $vgpr48
-; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr46
+; GFX9-NEXT: ; implicit-def: $vgpr47
+; GFX9-NEXT: ; implicit-def: $vgpr44
+; GFX9-NEXT: ; implicit-def: $vgpr45
+; GFX9-NEXT: ; implicit-def: $vgpr36
+; GFX9-NEXT: ; implicit-def: $vgpr34
+; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr31
-; GFX9-NEXT: ; implicit-def: $vgpr53
-; GFX9-NEXT: ; implicit-def: $vgpr56
-; GFX9-NEXT: ; implicit-def: $vgpr61
+; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr38
-; GFX9-NEXT: ; implicit-def: $vgpr37
-; GFX9-NEXT: ; implicit-def: $vgpr51
-; GFX9-NEXT: ; implicit-def: $vgpr50
+; GFX9-NEXT: ; implicit-def: $vgpr53
+; GFX9-NEXT: ; implicit-def: $vgpr54
+; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr49
-; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: .LBB110_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB110_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
+; GFX9-NEXT: s_waitcnt vmcnt(18)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v32
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
-; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
+; GFX9-NEXT: v_add_u16_e32 v1, 3, v39
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v49
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
-; GFX9-NEXT: s_waitcnt vmcnt(6)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v1
+; GFX9-NEXT: s_waitcnt vmcnt(10)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v35
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
-; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
-; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
-; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
-; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v38
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v33
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v31
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v62
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v63
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v61
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v60
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
-; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
-; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v59
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v34
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
-; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v57
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v56
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
-; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
-; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v45
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v36, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v47
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
-; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
+; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v43
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
@@ -92303,23 +92996,28 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v2, 3, v53
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v54
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v3, 3, v51
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v50
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v3
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
-; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
-; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
-; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
-; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
-; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
-; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
-; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
-; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
+; GFX9-NEXT: v_perm_b32 v8, v37, v8, s6
+; GFX9-NEXT: v_perm_b32 v9, v36, v9, s6
+; GFX9-NEXT: v_perm_b32 v10, v34, v10, s6
+; GFX9-NEXT: v_perm_b32 v11, v33, v11, s6
+; GFX9-NEXT: v_perm_b32 v12, v31, v12, s6
+; GFX9-NEXT: v_perm_b32 v13, v35, v13, s6
+; GFX9-NEXT: v_perm_b32 v14, v39, v14, s6
+; GFX9-NEXT: v_perm_b32 v15, v32, v15, s6
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -92416,89 +93114,75 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_3
@@ -92510,281 +93194,301 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v24, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v66, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v70, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v87, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v16, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v96, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v31.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v30, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v29, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v68, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v65, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v81, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v97, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
-; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v85, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v31.h
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v32.l
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v52, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.h, v12.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v37.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v55, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v13.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.h, 8, v49.l
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v36.l
+; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v15.l, v15.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v83, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v16.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-TRUE16-NEXT: .LBB110_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v49.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v39.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v37.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v36.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v53.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v33.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v31.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v51.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v31.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v50.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v82.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v87.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v67.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v70.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v29.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
-; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v16.l, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v17.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
@@ -92794,76 +93498,52 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32bf16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
-; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
-; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:128
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:124
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:100
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:96
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:92
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v15 :: v_dual_mov_b32 v32, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v14 :: v_dual_mov_b32 v52, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v13 :: v_dual_mov_b32 v50, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v11 :: v_dual_mov_b32 v34, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v54, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v3 :: v_dual_mov_b32 v48, v1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -92877,83 +93557,96 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v54, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v53, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v31, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v50, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v18, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v22, v23, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v24, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v26, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v66
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v71
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v65
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v67, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v82
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v69
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v83
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v112
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v102
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v99
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v87
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v103
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v113
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v116
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v85, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v100, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v117, v114, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v16, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v20, 0x5040100
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
@@ -92970,119 +93663,127 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v114
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v116
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v115
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v99, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v113, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v100, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v100, 0x300, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v101
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v112, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v97, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v87
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v85, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v83
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v81
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v69
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v71, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v84, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v65
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v70
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v66, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v30, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
@@ -93103,35 +93804,36 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v32, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v53, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v52
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v51
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v50, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v54, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
@@ -93140,9 +93842,9 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
@@ -93170,10 +93872,10 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v68, v12, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v85, v13, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v14, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v15, 0x5040100
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
index 39a3c96b9839a..99e22c6704e26 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
@@ -3687,6 +3687,7 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v36i16_to_v18i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -3703,9 +3704,13 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: v_mov_b32_e32 v33, v16
+; SI-NEXT: v_mov_b32_e32 v41, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v14
; SI-NEXT: v_mov_b32_e32 v36, v13
; SI-NEXT: v_mov_b32_e32 v37, v12
@@ -3720,49 +3725,28 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v54, v3
; SI-NEXT: v_mov_b32_e32 v55, v2
; SI-NEXT: v_mov_b32_e32 v40, v1
-; SI-NEXT: v_mov_b32_e32 v41, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v41
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3772,36 +3756,50 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v36
-; SI-NEXT: v_or_b32_e32 v0, v0, v45
-; SI-NEXT: v_or_b32_e32 v1, v1, v44
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
-; SI-NEXT: v_or_b32_e32 v5, v5, v62
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v59
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v10, v10, v57
-; SI-NEXT: v_or_b32_e32 v11, v11, v56
-; SI-NEXT: v_or_b32_e32 v12, v12, v47
-; SI-NEXT: v_or_b32_e32 v13, v13, v46
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -3832,15 +3830,19 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -3861,74 +3863,92 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_or_b32_e32 v4, v63, v4
-; SI-NEXT: v_or_b32_e32 v5, v62, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v60, v7
-; SI-NEXT: v_or_b32_e32 v8, v59, v8
-; SI-NEXT: v_or_b32_e32 v9, v58, v9
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v11, v56, v11
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
@@ -4343,49 +4363,121 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36i16_to_v18i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4404,7 +4496,6 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6985,49 +7076,121 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36f16_to_v18i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7046,7 +7209,6 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11214,6 +11376,7 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v36i16_to_v18f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -11230,9 +11393,13 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: v_mov_b32_e32 v33, v16
+; SI-NEXT: v_mov_b32_e32 v41, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v14
; SI-NEXT: v_mov_b32_e32 v36, v13
; SI-NEXT: v_mov_b32_e32 v37, v12
@@ -11247,49 +11414,28 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v54, v3
; SI-NEXT: v_mov_b32_e32 v55, v2
; SI-NEXT: v_mov_b32_e32 v40, v1
-; SI-NEXT: v_mov_b32_e32 v41, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v41
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -11299,36 +11445,50 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v36
-; SI-NEXT: v_or_b32_e32 v0, v0, v45
-; SI-NEXT: v_or_b32_e32 v1, v1, v44
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
-; SI-NEXT: v_or_b32_e32 v5, v5, v62
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v59
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v10, v10, v57
-; SI-NEXT: v_or_b32_e32 v11, v11, v56
-; SI-NEXT: v_or_b32_e32 v12, v12, v47
-; SI-NEXT: v_or_b32_e32 v13, v13, v46
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -11359,15 +11519,19 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -11388,74 +11552,92 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_or_b32_e32 v4, v63, v4
-; SI-NEXT: v_or_b32_e32 v5, v62, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v60, v7
-; SI-NEXT: v_or_b32_e32 v8, v59, v8
-; SI-NEXT: v_or_b32_e32 v9, v58, v9
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v11, v56, v11
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
@@ -11870,49 +12052,121 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36i16_to_v18f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -11931,7 +12185,6 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14709,49 +14962,121 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36f16_to_v18f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -14770,7 +15095,6 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17588,6 +17912,7 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v36i16_to_v9i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -17604,9 +17929,13 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: v_mov_b32_e32 v33, v16
+; SI-NEXT: v_mov_b32_e32 v41, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v14
; SI-NEXT: v_mov_b32_e32 v36, v13
; SI-NEXT: v_mov_b32_e32 v37, v12
@@ -17621,49 +17950,28 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v54, v3
; SI-NEXT: v_mov_b32_e32 v55, v2
; SI-NEXT: v_mov_b32_e32 v40, v1
-; SI-NEXT: v_mov_b32_e32 v41, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v41
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -17673,36 +17981,50 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v36
-; SI-NEXT: v_or_b32_e32 v0, v0, v45
-; SI-NEXT: v_or_b32_e32 v1, v1, v44
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
-; SI-NEXT: v_or_b32_e32 v5, v5, v62
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v59
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v10, v10, v57
-; SI-NEXT: v_or_b32_e32 v11, v11, v56
-; SI-NEXT: v_or_b32_e32 v12, v12, v47
-; SI-NEXT: v_or_b32_e32 v13, v13, v46
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -17733,15 +18055,19 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -17762,77 +18088,95 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_or_b32_e32 v4, v63, v4
-; SI-NEXT: v_or_b32_e32 v5, v62, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v60, v7
-; SI-NEXT: v_or_b32_e32 v8, v59, v8
-; SI-NEXT: v_or_b32_e32 v9, v58, v9
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v11, v56, v11
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -18244,49 +18588,121 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36i16_to_v9i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -18305,7 +18721,6 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20896,49 +21311,121 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36f16_to_v9i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20957,7 +21444,6 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23003,6 +23489,7 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v36i16_to_v9f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -23019,9 +23506,13 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v17
; SI-NEXT: v_mov_b32_e32 v33, v16
+; SI-NEXT: v_mov_b32_e32 v41, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v14
; SI-NEXT: v_mov_b32_e32 v36, v13
; SI-NEXT: v_mov_b32_e32 v37, v12
@@ -23036,49 +23527,28 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v54, v3
; SI-NEXT: v_mov_b32_e32 v55, v2
; SI-NEXT: v_mov_b32_e32 v40, v1
-; SI-NEXT: v_mov_b32_e32 v41, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v41
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -23088,36 +23558,50 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v37
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v36
-; SI-NEXT: v_or_b32_e32 v0, v0, v45
-; SI-NEXT: v_or_b32_e32 v1, v1, v44
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
-; SI-NEXT: v_or_b32_e32 v3, v3, v42
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
-; SI-NEXT: v_or_b32_e32 v5, v5, v62
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v60
-; SI-NEXT: v_or_b32_e32 v8, v8, v59
-; SI-NEXT: v_or_b32_e32 v9, v9, v58
-; SI-NEXT: v_or_b32_e32 v10, v10, v57
-; SI-NEXT: v_or_b32_e32 v11, v11, v56
-; SI-NEXT: v_or_b32_e32 v12, v12, v47
-; SI-NEXT: v_or_b32_e32 v13, v13, v46
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v35
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -23148,15 +23632,19 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -23177,74 +23665,92 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v45
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v42
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v61
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v59
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v57
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v56
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v47
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v46
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
-; SI-NEXT: v_or_b32_e32 v3, v42, v3
-; SI-NEXT: v_or_b32_e32 v4, v63, v4
-; SI-NEXT: v_or_b32_e32 v5, v62, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v60, v7
-; SI-NEXT: v_or_b32_e32 v8, v59, v8
-; SI-NEXT: v_or_b32_e32 v9, v58, v9
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v11, v56, v11
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
@@ -23659,49 +24165,121 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36i16_to_v9f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23720,7 +24298,6 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -26426,49 +27003,121 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v36f16_to_v9f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v33, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v34, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v35, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v31, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v30, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v29, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v27, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v26, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v25, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v23, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v22, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v20, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v19, v17, 0x5040100
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
-; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v17 :: v_dual_mov_b32 v33, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v15 :: v_dual_mov_b32 v35, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v13 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v39, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v9 :: v_dual_mov_b32 v49, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v7 :: v_dual_mov_b32 v51, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v5 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v3 :: v_dual_mov_b32 v55, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v1 :: v_dual_mov_b32 v65, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v65
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v99, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v98, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v97, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v96, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v87, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v86, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v85, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v84, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v83, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v81, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v70, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v69, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v68, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v67, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v66, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -26487,7 +27136,6 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -27295,97 +27943,66 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v36i16_to_v36f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v0
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v36
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v34
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v32
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v22
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v0
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; kill: killed $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -27393,66 +28010,68 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v48, v1, v57
-; SI-NEXT: v_alignbit_b32 v1, v48, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v39, v1, v58
-; SI-NEXT: v_alignbit_b32 v1, v39, v47, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v37, v1, v60
-; SI-NEXT: v_alignbit_b32 v1, v37, v56, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v34, v1, v62
-; SI-NEXT: v_alignbit_b32 v1, v34, v59, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v31, v1, v50
-; SI-NEXT: v_alignbit_b32 v1, v31, v61, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v28, v1, v52
-; SI-NEXT: v_alignbit_b32 v1, v28, v63, 16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; SI-NEXT: v_or_b32_e32 v39, v1, v18
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v46
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v45, v0, v46
+; SI-NEXT: v_or_b32_e32 v38, v3, v18
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
+; SI-NEXT: v_or_b32_e32 v45, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v25, v1, v55
-; SI-NEXT: v_or_b32_e32 v42, v0, v47
+; SI-NEXT: v_or_b32_e32 v36, v5, v18
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v56
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
+; SI-NEXT: v_or_b32_e32 v42, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_alignbit_b32 v1, v25, v51, 16
-; SI-NEXT: v_or_b32_e32 v53, v0, v56
+; SI-NEXT: v_or_b32_e32 v34, v7, v18
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v23
+; SI-NEXT: v_or_b32_e32 v54, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v49, v0, v59
+; SI-NEXT: v_or_b32_e32 v33, v9, v18
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v58
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
+; SI-NEXT: v_or_b32_e32 v51, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v23, v1, v41
-; SI-NEXT: v_or_b32_e32 v38, v0, v61
+; SI-NEXT: v_or_b32_e32 v31, v11, v18
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v59
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
+; SI-NEXT: v_or_b32_e32 v48, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_alignbit_b32 v1, v23, v54, 16
-; SI-NEXT: v_or_b32_e32 v36, v0, v63
+; SI-NEXT: v_or_b32_e32 v29, v13, v18
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v60
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v26
+; SI-NEXT: v_or_b32_e32 v37, v0, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v32, v0, v51
+; SI-NEXT: v_or_b32_e32 v28, v15, v18
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v61
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
+; SI-NEXT: v_or_b32_e32 v35, v0, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v18, v1, v43
-; SI-NEXT: v_or_b32_e32 v29, v0, v54
+; SI-NEXT: v_or_b32_e32 v18, v17, v18
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v62
+; SI-NEXT: v_or_b32_e32 v32, v0, v15
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_alignbit_b32 v44, v18, v40, 16
-; SI-NEXT: v_or_b32_e32 v26, v0, v40
+; SI-NEXT: v_alignbit_b32 v49, v39, v1, 16
+; SI-NEXT: v_alignbit_b32 v50, v38, v3, 16
+; SI-NEXT: v_alignbit_b32 v52, v36, v5, 16
+; SI-NEXT: v_alignbit_b32 v53, v34, v7, 16
+; SI-NEXT: v_alignbit_b32 v55, v33, v9, 16
+; SI-NEXT: v_alignbit_b32 v40, v31, v11, 16
+; SI-NEXT: v_alignbit_b32 v41, v29, v13, 16
+; SI-NEXT: v_alignbit_b32 v43, v28, v15, 16
+; SI-NEXT: v_alignbit_b32 v44, v18, v17, 16
+; SI-NEXT: v_or_b32_e32 v30, v0, v17
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -27471,216 +28090,198 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v46, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v2, v47, v2
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v4, v56, v4
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v8, v61, v8
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v2, v58, v2
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v4, v60, v4
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v2
-; SI-NEXT: v_alignbit_b32 v0, v48, v45, 16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v62
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v27
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v12, v51, v12
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v6, v62, v6
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v39, v42, 16
-; SI-NEXT: v_or_b32_e32 v16, v40, v16
-; SI-NEXT: v_or_b32_e32 v14, v54, v14
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v61
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v26
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v14
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v60
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v25
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v59
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v8, v50, v8
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v24
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v58
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v23
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v22
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v37, v53, 16
-; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v10, v52, v10
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v34, v49, 16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v12, v55, v12
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v31, v38, 16
-; SI-NEXT: v_or_b32_e32 v16, v43, v16
-; SI-NEXT: v_or_b32_e32 v14, v41, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v28, v36, 16
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v25, v32, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v23, v29, 16
-; SI-NEXT: v_alignbit_b32 v44, v18, v26, 16
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v34
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v56
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v47
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v20
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v49, v39, v45, 16
+; SI-NEXT: v_alignbit_b32 v50, v38, v42, 16
+; SI-NEXT: v_alignbit_b32 v52, v36, v54, 16
+; SI-NEXT: v_alignbit_b32 v53, v34, v51, 16
+; SI-NEXT: v_alignbit_b32 v55, v33, v48, 16
+; SI-NEXT: v_alignbit_b32 v40, v31, v37, 16
+; SI-NEXT: v_alignbit_b32 v41, v29, v35, 16
+; SI-NEXT: v_alignbit_b32 v43, v28, v32, 16
+; SI-NEXT: v_alignbit_b32 v44, v18, v30, 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v33
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v44
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v48
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v42
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v41
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v44
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v39
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v38
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v20
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v37
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v36
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v49
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v34
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v38
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v55
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v31
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v33
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v23
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v36
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v28
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v31
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v24
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v32
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v35
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v25
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v25
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v29
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v32
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v23
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v26
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
index 666b5353465eb..3bf13afd35b07 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
@@ -3993,6 +3993,7 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v40i16_to_v20i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -4009,13 +4010,29 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: v_mov_b32_e32 v33, v18
+; SI-NEXT: v_mov_b32_e32 v43, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v12
; SI-NEXT: v_mov_b32_e32 v48, v11
; SI-NEXT: v_mov_b32_e32 v49, v10
@@ -4028,58 +4045,26 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v40, v3
; SI-NEXT: v_mov_b32_e32 v41, v2
; SI-NEXT: v_mov_b32_e32 v42, v1
-; SI-NEXT: v_mov_b32_e32 v43, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -4093,32 +4078,44 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v58
-; SI-NEXT: v_or_b32_e32 v2, v2, v57
-; SI-NEXT: v_or_b32_e32 v3, v3, v56
-; SI-NEXT: v_or_b32_e32 v4, v4, v47
-; SI-NEXT: v_or_b32_e32 v5, v5, v46
-; SI-NEXT: v_or_b32_e32 v6, v6, v45
-; SI-NEXT: v_or_b32_e32 v7, v7, v44
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
@@ -4145,27 +4142,35 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -4202,86 +4207,106 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v59, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_or_b32_e32 v2, v57, v2
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v4, v47, v4
-; SI-NEXT: v_or_b32_e32 v5, v46, v5
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_or_b32_e32 v7, v44, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -4750,53 +4775,132 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v20i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4817,7 +4921,6 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7693,53 +7796,132 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v20i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7760,7 +7942,6 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -12273,6 +12454,7 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v40i16_to_v20f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -12289,13 +12471,29 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: v_mov_b32_e32 v33, v18
+; SI-NEXT: v_mov_b32_e32 v43, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v12
; SI-NEXT: v_mov_b32_e32 v48, v11
; SI-NEXT: v_mov_b32_e32 v49, v10
@@ -12308,58 +12506,26 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v40, v3
; SI-NEXT: v_mov_b32_e32 v41, v2
; SI-NEXT: v_mov_b32_e32 v42, v1
-; SI-NEXT: v_mov_b32_e32 v43, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -12373,32 +12539,44 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v51
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v58
-; SI-NEXT: v_or_b32_e32 v2, v2, v57
-; SI-NEXT: v_or_b32_e32 v3, v3, v56
-; SI-NEXT: v_or_b32_e32 v4, v4, v47
-; SI-NEXT: v_or_b32_e32 v5, v5, v46
-; SI-NEXT: v_or_b32_e32 v6, v6, v45
-; SI-NEXT: v_or_b32_e32 v7, v7, v44
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
@@ -12425,27 +12603,35 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -12482,86 +12668,106 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v59, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_or_b32_e32 v2, v57, v2
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v4, v47, v4
-; SI-NEXT: v_or_b32_e32 v5, v46, v5
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_or_b32_e32 v7, v44, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -13030,53 +13236,132 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v20f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -13097,7 +13382,6 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16191,53 +16475,132 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v20f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -16258,7 +16621,6 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -19322,6 +19684,7 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v40i16_to_v10i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -19338,13 +19701,29 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: v_mov_b32_e32 v33, v18
+; SI-NEXT: v_mov_b32_e32 v43, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v12
; SI-NEXT: v_mov_b32_e32 v48, v11
; SI-NEXT: v_mov_b32_e32 v49, v10
@@ -19357,58 +19736,26 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v40, v3
; SI-NEXT: v_mov_b32_e32 v41, v2
; SI-NEXT: v_mov_b32_e32 v42, v1
-; SI-NEXT: v_mov_b32_e32 v43, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -19422,32 +19769,44 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v58
-; SI-NEXT: v_or_b32_e32 v2, v2, v57
-; SI-NEXT: v_or_b32_e32 v3, v3, v56
-; SI-NEXT: v_or_b32_e32 v4, v4, v47
-; SI-NEXT: v_or_b32_e32 v5, v5, v46
-; SI-NEXT: v_or_b32_e32 v6, v6, v45
-; SI-NEXT: v_or_b32_e32 v7, v7, v44
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
@@ -19474,27 +19833,35 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -19531,86 +19898,106 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v59, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_or_b32_e32 v2, v57, v2
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v4, v47, v4
-; SI-NEXT: v_or_b32_e32 v5, v46, v5
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_or_b32_e32 v7, v44, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -20079,53 +20466,132 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v10i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -20146,7 +20612,6 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23032,53 +23497,132 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v10i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -23099,7 +23643,6 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25341,6 +25884,7 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v40i16_to_v10f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -25357,13 +25901,29 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v32, v19
; SI-NEXT: v_mov_b32_e32 v33, v18
+; SI-NEXT: v_mov_b32_e32 v43, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; SI-NEXT: v_mov_b32_e32 v34, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v12
; SI-NEXT: v_mov_b32_e32 v48, v11
; SI-NEXT: v_mov_b32_e32 v49, v10
@@ -25376,58 +25936,26 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v40, v3
; SI-NEXT: v_mov_b32_e32 v41, v2
; SI-NEXT: v_mov_b32_e32 v42, v1
-; SI-NEXT: v_mov_b32_e32 v43, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -25441,32 +25969,44 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v50
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v49
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v58
-; SI-NEXT: v_or_b32_e32 v2, v2, v57
-; SI-NEXT: v_or_b32_e32 v3, v3, v56
-; SI-NEXT: v_or_b32_e32 v4, v4, v47
-; SI-NEXT: v_or_b32_e32 v5, v5, v46
-; SI-NEXT: v_or_b32_e32 v6, v6, v45
-; SI-NEXT: v_or_b32_e32 v7, v7, v44
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v39
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
@@ -25493,27 +26033,35 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v33
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -25550,86 +26098,106 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v46
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v45
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v59, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v58, v1
-; SI-NEXT: v_or_b32_e32 v2, v57, v2
-; SI-NEXT: v_or_b32_e32 v3, v56, v3
-; SI-NEXT: v_or_b32_e32 v4, v47, v4
-; SI-NEXT: v_or_b32_e32 v5, v46, v5
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_or_b32_e32 v7, v44, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -26098,53 +26666,132 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v10f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -26165,7 +26812,6 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29179,53 +29825,132 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v10f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v19 :: v_dual_mov_b32 v33, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v17 :: v_dual_mov_b32 v35, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v15 :: v_dual_mov_b32 v37, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v13 :: v_dual_mov_b32 v39, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v11 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v9 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v7 :: v_dual_mov_b32 v53, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v5 :: v_dual_mov_b32 v55, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v3 :: v_dual_mov_b32 v65, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v1 :: v_dual_mov_b32 v67, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v37, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v39, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v36, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v35, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v29, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v28, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v27, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v24, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v23, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v103, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v102, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v101, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v100, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v99, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v98, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v97, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v96, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v87, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v86, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v85, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v83, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v82, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v81, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v80, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v71, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v70, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29246,7 +29971,6 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -30136,46 +30860,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; SI-NEXT: ; kill: killed $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -30192,128 +30876,140 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v0
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; kill: killed $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; kill: killed $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v53, v1, v63
-; SI-NEXT: v_alignbit_b32 v1, v53, v60, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; SI-NEXT: v_or_b32_e32 v52, v1, v20
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v60
+; SI-NEXT: v_alignbit_b32 v20, v52, v1, 16
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v51, v1, v40
-; SI-NEXT: v_alignbit_b32 v1, v51, v61, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; SI-NEXT: v_or_b32_e32 v50, v3, v20
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v61
+; SI-NEXT: v_alignbit_b32 v20, v50, v3, 16
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v49, v1, v42
-; SI-NEXT: v_alignbit_b32 v1, v49, v62, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v23
+; SI-NEXT: v_or_b32_e32 v49, v5, v20
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v62
+; SI-NEXT: v_alignbit_b32 v20, v49, v5, 16
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v38, v1, v45
-; SI-NEXT: v_alignbit_b32 v1, v38, v54, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v24
+; SI-NEXT: v_or_b32_e32 v39, v7, v20
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v63
+; SI-NEXT: v_alignbit_b32 v20, v39, v7, 16
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v36, v1, v46
-; SI-NEXT: v_alignbit_b32 v1, v36, v41, 16
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v25
+; SI-NEXT: v_or_b32_e32 v37, v9, v20
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v53
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v59, v0, v60
+; SI-NEXT: v_alignbit_b32 v20, v37, v9, 16
+; SI-NEXT: v_or_b32_e32 v59, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v33, v1, v57
-; SI-NEXT: v_or_b32_e32 v56, v0, v61
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v26
+; SI-NEXT: v_or_b32_e32 v56, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_alignbit_b32 v1, v33, v44, 16
-; SI-NEXT: v_or_b32_e32 v43, v0, v62
+; SI-NEXT: v_or_b32_e32 v35, v11, v20
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v55
+; SI-NEXT: v_or_b32_e32 v45, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v55, v0, v54
+; SI-NEXT: v_alignbit_b32 v20, v35, v11, 16
+; SI-NEXT: v_or_b32_e32 v41, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v30, v1, v29
-; SI-NEXT: v_or_b32_e32 v0, v0, v41
-; SI-NEXT: v_alignbit_b32 v1, v30, v47, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
+; SI-NEXT: v_or_b32_e32 v54, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
-; SI-NEXT: v_or_b32_e32 v27, v1, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v34, v13, v20
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v40
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
+; SI-NEXT: v_or_b32_e32 v51, v0, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_alignbit_b32 v1, v27, v58, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v47
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v32, v15, v20
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v42
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; SI-NEXT: v_or_b32_e32 v48, v0, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v25, v1, v50
-; SI-NEXT: v_or_b32_e32 v0, v0, v58
-; SI-NEXT: v_alignbit_b32 v1, v25, v32, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v31, v17, v20
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v43
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v30
+; SI-NEXT: v_or_b32_e32 v38, v0, v15
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: v_or_b32_e32 v20, v1, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v20, v19, v20
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v44
+; SI-NEXT: v_or_b32_e32 v36, v0, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: v_alignbit_b32 v1, v20, v39, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v46, v34, v13, 16
+; SI-NEXT: v_alignbit_b32 v47, v32, v15, 16
+; SI-NEXT: v_alignbit_b32 v57, v31, v17, 16
+; SI-NEXT: v_alignbit_b32 v58, v20, v19, 16
+; SI-NEXT: v_or_b32_e32 v33, v0, v19
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -30334,214 +31030,193 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v39, v18
-; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v44
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v30
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v18, v52, v18
-; SI-NEXT: v_or_b32_e32 v16, v32, v16
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v43
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v29
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v50, v16
-; SI-NEXT: v_or_b32_e32 v14, v58, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v42
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v28
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v14, v35, v14
-; SI-NEXT: v_or_b32_e32 v12, v47, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v40
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v27
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: v_or_b32_e32 v12, v29, v12
-; SI-NEXT: v_or_b32_e32 v10, v44, v10
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v2, v61, v2
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v55
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v26
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v6, v54, v6
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v63, v0
-; SI-NEXT: v_or_b32_e32 v10, v57, v10
-; SI-NEXT: v_or_b32_e32 v8, v41, v8
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v53
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v4, v42, v4
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v2
-; SI-NEXT: v_alignbit_b32 v0, v53, v59, 16
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v6, v45, v6
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v25
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v63
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v24
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v61
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v60
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v52, v59, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v51, v56, 16
-; SI-NEXT: v_or_b32_e32 v8, v46, v8
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v50, v56, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v49, v43, 16
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v49, v45, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v38, v55, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v36, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v33, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v30, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v27, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v25, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v20, v21, 16
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v25
+; SI-NEXT: v_alignbit_b32 v0, v39, v41, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v37, v54, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v35, v51, 16
+; SI-NEXT: v_alignbit_b32 v46, v34, v48, 16
+; SI-NEXT: v_alignbit_b32 v47, v32, v38, 16
+; SI-NEXT: v_alignbit_b32 v57, v31, v36, 16
+; SI-NEXT: v_alignbit_b32 v58, v20, v33, 16
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v46
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v47
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v57
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v58
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v25
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v22
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v53
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v56
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v51
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v50
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v55
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v38
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -30559,43 +31234,38 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v39
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v36
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v33
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v35
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v48
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v30
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v34
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v38
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v27
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v36
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v25
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v33
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v30
; SI-NEXT: v_or_b32_e32 v19, v19, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v40i16_to_v40f16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 68bf611ec019e..e9a6997390b1b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -1167,11 +1167,9 @@ define i64 @bitcast_v4i16_to_i64(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1184,21 +1182,25 @@ define i64 @bitcast_v4i16_to_i64(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB14_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: .LBB14_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -2019,14 +2021,10 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2038,25 +2036,33 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB22_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: .LBB22_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -2958,12 +2964,9 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v8i8_to_i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -2976,49 +2979,57 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
@@ -4341,11 +4352,9 @@ define double @bitcast_v4i16_to_f64(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -4358,21 +4367,25 @@ define double @bitcast_v4i16_to_f64(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB38_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: .LBB38_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -5190,14 +5203,10 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5209,25 +5218,33 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB46_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_2
; SI-NEXT: .LBB46_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -6136,12 +6153,9 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v8i8_to_f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6154,49 +6168,57 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB50_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: .LBB50_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
@@ -7206,11 +7228,9 @@ define <2 x i32> @bitcast_v4i16_to_v2i32(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -7223,21 +7243,25 @@ define <2 x i32> @bitcast_v4i16_to_v2i32(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB58_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: .LBB58_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -8056,14 +8080,10 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -8075,25 +8095,33 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB66_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB66_2
; SI-NEXT: .LBB66_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -8993,12 +9021,9 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v8i8_to_v2i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -9011,49 +9036,57 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB70_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB70_2
; SI-NEXT: .LBB70_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
@@ -9744,11 +9777,9 @@ define <2 x float> @bitcast_v4i16_to_v2f32(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -9761,21 +9792,25 @@ define <2 x float> @bitcast_v4i16_to_v2f32(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB74_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_2
; SI-NEXT: .LBB74_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -10606,14 +10641,10 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -10625,25 +10656,33 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB82_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_alignbit_b32 v0, v0, v5, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v3, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB82_2
; SI-NEXT: .LBB82_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11559,12 +11598,9 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v8i8_to_v2f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v10, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -11577,49 +11613,57 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB86_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB86_2
; SI-NEXT: .LBB86_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
@@ -12117,10 +12161,8 @@ define <4 x half> @bitcast_v4i16_to_v4f16(<4 x i16> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
@@ -12128,25 +12170,28 @@ define <4 x half> @bitcast_v4i16_to_v4f16(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v1, v7
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v4, v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v5, v4, v6, 16
-; SI-NEXT: v_or_b32_e32 v2, v0, v6
+; SI-NEXT: v_alignbit_b32 v5, v4, v1, 16
+; SI-NEXT: v_or_b32_e32 v2, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v5, v4, v2, 16
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4
@@ -12582,45 +12627,51 @@ define <4 x bfloat> @bitcast_v4i16_to_v4bf16(<4 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v4i16_to_v4bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v2
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v2
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -12817,54 +12868,58 @@ define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v3
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB94_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v5
-; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; SI-NEXT: v_alignbit_b32 v3, v1, v3, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; SI-NEXT: v_alignbit_b32 v1, v4, v1, 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
; SI-NEXT: .LBB94_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -13365,10 +13420,8 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v9, v0
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v6
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -13387,27 +13440,30 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB96_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_or_b32_e32 v4, v1, v10
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v4, v1, v2
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: v_bfe_u32 v7, v6, 8, 8
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: .LBB96_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_or_b32_e32 v1, v10, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
@@ -13423,20 +13479,22 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr4
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v0
; VI-NEXT: v_mov_b32_e32 v9, v0
; VI-NEXT: v_mov_b32_e32 v8, v1
@@ -13814,77 +13872,81 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v7, v3
-; SI-NEXT: v_or_b32_e32 v3, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v9, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v5, v3, v1, 16
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; SI-NEXT: v_alignbit_b32 v10, v9, v2, 16
+; SI-NEXT: v_or_b32_e32 v8, v0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: .LBB98_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v5, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v10, v9, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -14645,45 +14707,50 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v4bf16_to_v4f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB102_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; SI-NEXT: v_alignbit_b32 v2, v1, v5, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; SI-NEXT: v_alignbit_b32 v3, v2, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; SI-NEXT: v_alignbit_b32 v0, v0, v7, 16
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v4
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_alignbit_b32 v2, v1, v0, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6
+; SI-NEXT: v_alignbit_b32 v3, v2, v3, 16
+; SI-NEXT: v_alignbit_b32 v0, v0, v4, 16
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: .LBB102_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB102_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v7
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v2, v1, v2, 16
@@ -15286,18 +15353,20 @@ define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) {
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v9
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; VI-NEXT: ; %bb.2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
@@ -15683,77 +15752,81 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v7, v3
-; SI-NEXT: v_or_b32_e32 v3, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v10
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v9, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v5, v3, v1, 16
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; SI-NEXT: v_alignbit_b32 v10, v9, v2, 16
+; SI-NEXT: v_or_b32_e32 v8, v0, v2
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: .LBB106_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v5, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v10, v9, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v9
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -16260,15 +16333,11 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v4bf16_to_v8i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v3
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v1
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -16287,14 +16356,18 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB108_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v4, v6, v9, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v8
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_alignbit_b32 v4, v6, v1, 16
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v8
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
@@ -16303,14 +16376,18 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB108_2
; SI-NEXT: .LBB108_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
@@ -17043,13 +17120,10 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v7
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
@@ -17057,64 +17131,70 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; SI-NEXT: v_or_b32_e32 v3, v1, v0
+; SI-NEXT: v_or_b32_e32 v8, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v5, v8, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_or_b32_e32 v9, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v10, v9, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_or_b32_e32 v11, v1, v0
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v3, v11, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x300, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v9, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v8, v1
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
index d2f29b856a013..2e1073ab137d7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
@@ -4284,14 +4284,41 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v33, v20
+; SI-NEXT: v_mov_b32_e32 v45, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v34, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v11
; SI-NEXT: v_mov_b32_e32 v51, v10
; SI-NEXT: v_mov_b32_e32 v52, v9
@@ -4303,104 +4330,77 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v42, v3
; SI-NEXT: v_mov_b32_e32 v43, v2
; SI-NEXT: v_mov_b32_e32 v44, v1
-; SI-NEXT: v_mov_b32_e32 v45, v0
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v45
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v50
-; SI-NEXT: v_or_b32_e32 v0, v0, v33
-; SI-NEXT: v_or_b32_e32 v1, v1, v63
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v62
-; SI-NEXT: v_or_b32_e32 v4, v4, v61
-; SI-NEXT: v_or_b32_e32 v5, v5, v60
-; SI-NEXT: v_or_b32_e32 v6, v6, v59
-; SI-NEXT: v_or_b32_e32 v7, v7, v58
-; SI-NEXT: v_or_b32_e32 v8, v8, v57
-; SI-NEXT: v_or_b32_e32 v9, v9, v56
-; SI-NEXT: v_or_b32_e32 v10, v10, v47
-; SI-NEXT: v_or_b32_e32 v11, v11, v46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -4413,10 +4413,9 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -4425,33 +4424,48 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
@@ -4459,10 +4473,9 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -4494,96 +4507,125 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: v_or_b32_e32 v4, v61, v4
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v7, v58, v7
-; SI-NEXT: v_or_b32_e32 v8, v57, v8
-; SI-NEXT: v_or_b32_e32 v9, v56, v9
-; SI-NEXT: v_or_b32_e32 v10, v47, v10
-; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -4594,17 +4636,12 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: .LBB14_4: ; %end
@@ -5119,57 +5156,143 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44i16_to_v22i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5192,7 +5315,6 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8363,57 +8485,143 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44f16_to_v22i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -8436,7 +8644,6 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -13267,14 +13474,41 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v33, v20
+; SI-NEXT: v_mov_b32_e32 v45, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v34, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v11
; SI-NEXT: v_mov_b32_e32 v51, v10
; SI-NEXT: v_mov_b32_e32 v52, v9
@@ -13286,104 +13520,77 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v42, v3
; SI-NEXT: v_mov_b32_e32 v43, v2
; SI-NEXT: v_mov_b32_e32 v44, v1
-; SI-NEXT: v_mov_b32_e32 v45, v0
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v45
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v50
-; SI-NEXT: v_or_b32_e32 v0, v0, v33
-; SI-NEXT: v_or_b32_e32 v1, v1, v63
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v62
-; SI-NEXT: v_or_b32_e32 v4, v4, v61
-; SI-NEXT: v_or_b32_e32 v5, v5, v60
-; SI-NEXT: v_or_b32_e32 v6, v6, v59
-; SI-NEXT: v_or_b32_e32 v7, v7, v58
-; SI-NEXT: v_or_b32_e32 v8, v8, v57
-; SI-NEXT: v_or_b32_e32 v9, v9, v56
-; SI-NEXT: v_or_b32_e32 v10, v10, v47
-; SI-NEXT: v_or_b32_e32 v11, v11, v46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -13396,10 +13603,9 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -13408,33 +13614,48 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
@@ -13442,10 +13663,9 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -13477,96 +13697,125 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: v_or_b32_e32 v4, v61, v4
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v7, v58, v7
-; SI-NEXT: v_or_b32_e32 v8, v57, v8
-; SI-NEXT: v_or_b32_e32 v9, v56, v9
-; SI-NEXT: v_or_b32_e32 v10, v47, v10
-; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -13577,17 +13826,12 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: .LBB30_4: ; %end
@@ -14102,57 +14346,143 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44i16_to_v22f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -14175,7 +14505,6 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17585,57 +17914,143 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44f16_to_v22f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -17658,7 +18073,6 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20975,14 +21389,41 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v33, v20
+; SI-NEXT: v_mov_b32_e32 v45, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v34, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v11
; SI-NEXT: v_mov_b32_e32 v51, v10
; SI-NEXT: v_mov_b32_e32 v52, v9
@@ -20994,104 +21435,77 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v42, v3
; SI-NEXT: v_mov_b32_e32 v43, v2
; SI-NEXT: v_mov_b32_e32 v44, v1
-; SI-NEXT: v_mov_b32_e32 v45, v0
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v45
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v50
-; SI-NEXT: v_or_b32_e32 v0, v0, v33
-; SI-NEXT: v_or_b32_e32 v1, v1, v63
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v62
-; SI-NEXT: v_or_b32_e32 v4, v4, v61
-; SI-NEXT: v_or_b32_e32 v5, v5, v60
-; SI-NEXT: v_or_b32_e32 v6, v6, v59
-; SI-NEXT: v_or_b32_e32 v7, v7, v58
-; SI-NEXT: v_or_b32_e32 v8, v8, v57
-; SI-NEXT: v_or_b32_e32 v9, v9, v56
-; SI-NEXT: v_or_b32_e32 v10, v10, v47
-; SI-NEXT: v_or_b32_e32 v11, v11, v46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -21104,10 +21518,9 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -21116,33 +21529,48 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
@@ -21150,10 +21578,9 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -21185,117 +21612,141 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: v_or_b32_e32 v4, v61, v4
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v7, v58, v7
-; SI-NEXT: v_or_b32_e32 v8, v57, v8
-; SI-NEXT: v_or_b32_e32 v9, v56, v9
-; SI-NEXT: v_or_b32_e32 v10, v47, v10
-; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: .LBB42_4: ; %end
@@ -21810,57 +22261,143 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44i16_to_v11i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -21883,7 +22420,6 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25066,57 +25602,143 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44f16_to_v11i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -25139,7 +25761,6 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -27597,14 +28218,41 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v33, v20
+; SI-NEXT: v_mov_b32_e32 v45, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v34, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; SI-NEXT: v_mov_b32_e32 v35, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; SI-NEXT: v_mov_b32_e32 v36, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v11
; SI-NEXT: v_mov_b32_e32 v51, v10
; SI-NEXT: v_mov_b32_e32 v52, v9
@@ -27616,104 +28264,77 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v42, v3
; SI-NEXT: v_mov_b32_e32 v43, v2
; SI-NEXT: v_mov_b32_e32 v44, v1
-; SI-NEXT: v_mov_b32_e32 v45, v0
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v45
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v52
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v50
-; SI-NEXT: v_or_b32_e32 v0, v0, v33
-; SI-NEXT: v_or_b32_e32 v1, v1, v63
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v62
-; SI-NEXT: v_or_b32_e32 v4, v4, v61
-; SI-NEXT: v_or_b32_e32 v5, v5, v60
-; SI-NEXT: v_or_b32_e32 v6, v6, v59
-; SI-NEXT: v_or_b32_e32 v7, v7, v58
-; SI-NEXT: v_or_b32_e32 v8, v8, v57
-; SI-NEXT: v_or_b32_e32 v9, v9, v56
-; SI-NEXT: v_or_b32_e32 v10, v10, v47
-; SI-NEXT: v_or_b32_e32 v11, v11, v46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
@@ -27726,10 +28347,9 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
@@ -27738,33 +28358,48 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v35
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v34
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
@@ -27772,10 +28407,9 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -27807,96 +28441,125 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v46
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v62
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v47
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: v_or_b32_e32 v4, v61, v4
-; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v7, v58, v7
-; SI-NEXT: v_or_b32_e32 v8, v57, v8
-; SI-NEXT: v_or_b32_e32 v9, v56, v9
-; SI-NEXT: v_or_b32_e32 v10, v47, v10
-; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v49
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v33
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -27907,17 +28570,12 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: .LBB50_4: ; %end
@@ -28432,57 +29090,143 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44i16_to_v11f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -28505,7 +29249,6 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -31827,57 +32570,143 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v44f16_to_v11f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v21 :: v_dual_mov_b32 v33, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v19 :: v_dual_mov_b32 v35, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v17 :: v_dual_mov_b32 v37, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v15 :: v_dual_mov_b32 v39, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v13 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v11 :: v_dual_mov_b32 v51, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v9 :: v_dual_mov_b32 v53, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v7 :: v_dual_mov_b32 v55, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v5 :: v_dual_mov_b32 v65, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v3 :: v_dual_mov_b32 v67, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v1 :: v_dual_mov_b32 v69, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v69
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v49, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v48, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v39, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v38, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v37, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v36, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v35, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v34, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v32, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v31, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v30, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v28, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v27, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v26, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v25, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v115, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v114, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v113, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v112, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v103, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v102, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v101, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v100, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v99, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v98, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v97, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v96, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v87, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v83, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v82, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v81, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v80, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v71, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v70, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -31900,7 +32729,6 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32856,32 +33684,7 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v44i16_to_v44f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v51
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v48
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
@@ -32903,26 +33706,6 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -32941,40 +33724,50 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v50
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v0
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -32982,106 +33775,105 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v51
-; SI-NEXT: v_or_b32_e32 v42, v1, v22
-; SI-NEXT: v_alignbit_b32 v1, v42, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; SI-NEXT: v_or_b32_e32 v55, v1, v22
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v44
+; SI-NEXT: v_alignbit_b32 v22, v55, v1, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
-; SI-NEXT: v_or_b32_e32 v40, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v40, v47, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; SI-NEXT: v_or_b32_e32 v54, v3, v22
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v45
+; SI-NEXT: v_alignbit_b32 v22, v54, v3, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v54, v1, v62
-; SI-NEXT: v_alignbit_b32 v1, v54, v56, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v25
+; SI-NEXT: v_or_b32_e32 v52, v5, v22
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v47
+; SI-NEXT: v_alignbit_b32 v22, v52, v5, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_or_b32_e32 v52, v1, v32
-; SI-NEXT: v_alignbit_b32 v1, v52, v59, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v26
+; SI-NEXT: v_or_b32_e32 v50, v7, v22
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v56
+; SI-NEXT: v_alignbit_b32 v22, v50, v7, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_or_b32_e32 v0, v0, v46
-; SI-NEXT: v_or_b32_e32 v49, v1, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v27
+; SI-NEXT: v_or_b32_e32 v49, v9, v22
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v57
+; SI-NEXT: v_alignbit_b32 v22, v49, v9, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_alignbit_b32 v1, v49, v61, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v47
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v28
+; SI-NEXT: v_or_b32_e32 v39, v11, v22
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v59
+; SI-NEXT: v_alignbit_b32 v22, v39, v11, 16
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
+; SI-NEXT: v_or_b32_e32 v37, v13, v22
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v60
+; SI-NEXT: v_alignbit_b32 v22, v37, v13, 16
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v30
+; SI-NEXT: v_or_b32_e32 v42, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v36, v15, v22
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v62
+; SI-NEXT: v_or_b32_e32 v41, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v38, v1, v53
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: v_alignbit_b32 v1, v38, v43, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v22, v36, v15, 16
+; SI-NEXT: v_or_b32_e32 v61, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_or_b32_e32 v35, v1, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v31
+; SI-NEXT: v_or_b32_e32 v58, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_alignbit_b32 v1, v35, v36, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v61
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v35, v17, v22
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v63
+; SI-NEXT: v_or_b32_e32 v46, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v33, v1, v45
-; SI-NEXT: v_or_b32_e32 v0, v0, v43
-; SI-NEXT: v_alignbit_b32 v1, v33, v50, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v22, v35, v17, 16
+; SI-NEXT: v_or_b32_e32 v43, v0, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v0, v0, v36
-; SI-NEXT: v_or_b32_e32 v30, v1, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v32
+; SI-NEXT: v_or_b32_e32 v40, v0, v13
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_alignbit_b32 v1, v30, v55, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v50
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v34, v19, v22
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
+; SI-NEXT: v_or_b32_e32 v53, v0, v15
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v28, v1, v57
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
-; SI-NEXT: v_alignbit_b32 v1, v28, v58, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v22, v34, v19, 16
+; SI-NEXT: v_or_b32_e32 v51, v0, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v0, v0, v58
-; SI-NEXT: v_or_b32_e32 v22, v1, v60
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v19
+; SI-NEXT: v_or_b32_e32 v22, v21, v22
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v48
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: v_alignbit_b32 v1, v22, v44, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
-; SI-NEXT: ; kill: killed $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v38, v22, v21, 16
+; SI-NEXT: v_or_b32_e32 v0, v0, v21
+; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
@@ -33105,239 +33897,257 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; kill: killed $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v44, v20
-; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v48
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
+; SI-NEXT: v_add_i32_e32 v48, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v33
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v20, v60, v20
-; SI-NEXT: v_or_b32_e32 v18, v58, v18
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v38
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v32
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v57, v18
-; SI-NEXT: v_or_b32_e32 v16, v55, v16
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v63
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v31
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v63, v16
-; SI-NEXT: v_or_b32_e32 v14, v50, v14
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v62
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v30
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v14, v45, v14
-; SI-NEXT: v_or_b32_e32 v12, v36, v12
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v60
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v29
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v12, v41, v12
-; SI-NEXT: v_or_b32_e32 v10, v43, v10
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v59
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v28
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v10, v53, v10
-; SI-NEXT: v_or_b32_e32 v8, v61, v8
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v57
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
+; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v26
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v6, v32, v6
-; SI-NEXT: v_or_b32_e32 v4, v56, v4
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v47
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v25
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v62, v4
-; SI-NEXT: v_or_b32_e32 v2, v47, v2
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v45
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v46, v0
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v33
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v30
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v44
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v40
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v42, v2, 16
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v55, v42, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v54, v41, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v52, v61, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v50, v58, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v49, v46, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v39, v43, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v40, v4, 16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v37, v40, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v54, v6, 16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v36, v53, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v35, v51, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v52, v8, 16
+; SI-NEXT: v_alignbit_b32 v0, v34, v20, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v49, v10, 16
+; SI-NEXT: v_alignbit_b32 v0, v22, v48, 16
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v36
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v35
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v34
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v38, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v35, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v33, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v30, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v28, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v22, v23, 16
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v42
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v51
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v24
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v32
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v41
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v58
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v50
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v46
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v49
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v43
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v39
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v40
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v37
+; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v15, v15, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v35
+; SI-NEXT: v_or_b32_e32 v17, v17, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -33355,58 +34165,18 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v54
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v52
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v49
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v38
-; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v30
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v28
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v34
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v33
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index ba58d8a9fba52..fbf8495923781 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -4574,14 +4574,49 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v47, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v35, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
@@ -4593,112 +4628,76 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
-; SI-NEXT: v_mov_b32_e32 v47, v0
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v59
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v58
-; SI-NEXT: v_or_b32_e32 v4, v4, v33
-; SI-NEXT: v_or_b32_e32 v5, v5, v57
-; SI-NEXT: v_or_b32_e32 v6, v6, v32
-; SI-NEXT: v_or_b32_e32 v7, v7, v56
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
@@ -4711,47 +4710,61 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
@@ -4759,10 +4772,13 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -4810,96 +4826,124 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v58, v3
-; SI-NEXT: v_or_b32_e32 v4, v33, v4
-; SI-NEXT: v_or_b32_e32 v5, v57, v5
-; SI-NEXT: v_or_b32_e32 v6, v32, v6
-; SI-NEXT: v_or_b32_e32 v7, v56, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -4910,22 +4954,21 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -5502,61 +5545,154 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v24i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5581,7 +5717,6 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9061,61 +9196,154 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v24i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9140,7 +9368,6 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14288,14 +14515,49 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v47, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v35, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
@@ -14307,112 +14569,76 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
-; SI-NEXT: v_mov_b32_e32 v47, v0
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v59
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v58
-; SI-NEXT: v_or_b32_e32 v4, v4, v33
-; SI-NEXT: v_or_b32_e32 v5, v5, v57
-; SI-NEXT: v_or_b32_e32 v6, v6, v32
-; SI-NEXT: v_or_b32_e32 v7, v7, v56
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
@@ -14425,47 +14651,61 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
@@ -14473,10 +14713,13 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -14524,96 +14767,124 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v58, v3
-; SI-NEXT: v_or_b32_e32 v4, v33, v4
-; SI-NEXT: v_or_b32_e32 v5, v57, v5
-; SI-NEXT: v_or_b32_e32 v6, v32, v6
-; SI-NEXT: v_or_b32_e32 v7, v56, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -14624,22 +14895,21 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -15216,61 +15486,154 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v24f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -15295,7 +15658,6 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -19035,61 +19397,154 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v24f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -19114,7 +19569,6 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -22681,14 +23135,49 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v47, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v35, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
@@ -22700,112 +23189,76 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
-; SI-NEXT: v_mov_b32_e32 v47, v0
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v59
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v58
-; SI-NEXT: v_or_b32_e32 v4, v4, v33
-; SI-NEXT: v_or_b32_e32 v5, v5, v57
-; SI-NEXT: v_or_b32_e32 v6, v6, v32
-; SI-NEXT: v_or_b32_e32 v7, v7, v56
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
@@ -22818,47 +23271,61 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
@@ -22866,10 +23333,13 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -22917,96 +23387,124 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v58, v3
-; SI-NEXT: v_or_b32_e32 v4, v33, v4
-; SI-NEXT: v_or_b32_e32 v5, v57, v5
-; SI-NEXT: v_or_b32_e32 v6, v32, v6
-; SI-NEXT: v_or_b32_e32 v7, v56, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -23017,22 +23515,21 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -23609,61 +24106,154 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v12i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23688,7 +24278,6 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -27180,61 +27769,154 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v12i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -27259,7 +27941,6 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29933,14 +30614,49 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v47, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v35, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; SI-NEXT: v_mov_b32_e32 v37, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
@@ -29952,112 +30668,76 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
-; SI-NEXT: v_mov_b32_e32 v47, v0
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v59
-; SI-NEXT: v_or_b32_e32 v2, v2, v34
-; SI-NEXT: v_or_b32_e32 v3, v3, v58
-; SI-NEXT: v_or_b32_e32 v4, v4, v33
-; SI-NEXT: v_or_b32_e32 v5, v5, v57
-; SI-NEXT: v_or_b32_e32 v6, v6, v32
-; SI-NEXT: v_or_b32_e32 v7, v7, v56
-; SI-NEXT: v_or_b32_e32 v8, v8, v63
-; SI-NEXT: v_or_b32_e32 v9, v9, v62
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
@@ -30070,47 +30750,61 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
@@ -30118,10 +30812,13 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -30169,96 +30866,124 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v33
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v58
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v57
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v2, v34, v2
-; SI-NEXT: v_or_b32_e32 v3, v58, v3
-; SI-NEXT: v_or_b32_e32 v4, v33, v4
-; SI-NEXT: v_or_b32_e32 v5, v57, v5
-; SI-NEXT: v_or_b32_e32 v6, v32, v6
-; SI-NEXT: v_or_b32_e32 v7, v56, v7
-; SI-NEXT: v_or_b32_e32 v8, v63, v8
-; SI-NEXT: v_or_b32_e32 v9, v62, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
-; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v35
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -30269,22 +30994,21 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -30861,61 +31585,154 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v12f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -30940,7 +31757,6 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -34584,61 +35400,154 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v12f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v23 :: v_dual_mov_b32 v33, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v21 :: v_dual_mov_b32 v35, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v19 :: v_dual_mov_b32 v37, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v17 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v49, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v13 :: v_dual_mov_b32 v51, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v11 :: v_dual_mov_b32 v53, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v9 :: v_dual_mov_b32 v55, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v7 :: v_dual_mov_b32 v65, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v5 :: v_dual_mov_b32 v67, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v3 :: v_dual_mov_b32 v69, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v1 :: v_dual_mov_b32 v71, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v71
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v119, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v118, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v116, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v115, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v114, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v113, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v112, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v103, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v101, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v100, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v99, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v98, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v96, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v86, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v85, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v84, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v83, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v81, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v80, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34663,7 +35572,6 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -35695,36 +36603,7 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v48i16_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; kill: killed $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; kill: killed $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
@@ -35778,64 +36657,48 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
-; SI-NEXT: ; kill: killed $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v54
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v52
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v51
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v48
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v0
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -35843,128 +36706,127 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v53
-; SI-NEXT: v_or_b32_e32 v46, v1, v24
-; SI-NEXT: v_alignbit_b32 v1, v46, v58, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_or_b32_e32 v44, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v44, v60, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v25
+; SI-NEXT: v_or_b32_e32 v42, v1, v24
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v43
+; SI-NEXT: v_alignbit_b32 v24, v42, v1, 16
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
-; SI-NEXT: v_or_b32_e32 v43, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v43, v61, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
+; SI-NEXT: v_or_b32_e32 v40, v3, v24
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; SI-NEXT: v_alignbit_b32 v24, v40, v3, 16
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
-; SI-NEXT: v_or_b32_e32 v41, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v27
+; SI-NEXT: v_or_b32_e32 v55, v5, v24
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v56
+; SI-NEXT: v_alignbit_b32 v24, v55, v5, 16
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
-; SI-NEXT: v_or_b32_e32 v55, v1, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v1, v55, v51, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v58
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v28
+; SI-NEXT: v_or_b32_e32 v53, v7, v24
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; SI-NEXT: v_alignbit_b32 v24, v53, v7, 16
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v29
+; SI-NEXT: v_or_b32_e32 v51, v9, v24
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v52
+; SI-NEXT: v_alignbit_b32 v24, v51, v9, 16
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
+; SI-NEXT: v_or_b32_e32 v50, v11, v24
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v54
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_alignbit_b32 v24, v50, v11, 16
+; SI-NEXT: v_or_b32_e32 v62, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v52, v1, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_alignbit_b32 v1, v52, v40, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v31
+; SI-NEXT: v_or_b32_e32 v60, v0, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v0, v0, v61
-; SI-NEXT: v_or_b32_e32 v49, v1, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_or_b32_e32 v49, v13, v24
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v41
+; SI-NEXT: v_or_b32_e32 v57, v0, v5
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_alignbit_b32 v1, v49, v45, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v36
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v24, v49, v13, 16
+; SI-NEXT: v_or_b32_e32 v45, v0, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v38, v1, v57
-; SI-NEXT: v_or_b32_e32 v0, v0, v51
-; SI-NEXT: v_alignbit_b32 v1, v38, v59, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
+; SI-NEXT: v_or_b32_e32 v0, v0, v9
+; SI-NEXT: v_or_b32_e32 v48, v15, v24
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v24, v48, v15, 16
+; SI-NEXT: v_or_b32_e32 v0, v0, v11
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v0, v0, v40
-; SI-NEXT: v_or_b32_e32 v35, v1, v54
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_alignbit_b32 v1, v35, v63, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v45
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v39, v17, v24
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v47
+; SI-NEXT: v_or_b32_e32 v0, v0, v13
+; SI-NEXT: v_alignbit_b32 v24, v39, v17, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v33, v1, v47
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_alignbit_b32 v1, v33, v48, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
+; SI-NEXT: v_or_b32_e32 v0, v0, v15
+; SI-NEXT: v_or_b32_e32 v38, v19, v24
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v58
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v24, v38, v19, 16
+; SI-NEXT: v_or_b32_e32 v0, v0, v17
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v0, v0, v63
-; SI-NEXT: v_or_b32_e32 v31, v1, v25
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v35
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: v_or_b32_e32 v0, v0, v48
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: v_alignbit_b32 v1, v31, v42, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v37, v21, v24
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v19
+; SI-NEXT: v_alignbit_b32 v24, v37, v21, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: v_or_b32_e32 v0, v0, v42
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: v_or_b32_e32 v24, v1, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v0, v21
+; SI-NEXT: v_or_b32_e32 v24, v23, v24
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v63
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: v_alignbit_b32 v1, v24, v56, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v52, v24, v23, 16
+; SI-NEXT: v_or_b32_e32 v0, v0, v23
+; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -35989,279 +36851,262 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; kill: killed $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v22, v56, v22
-; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v22
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v63
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
+; SI-NEXT: v_add_i32_e32 v63, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v36
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v22, v26, v22
-; SI-NEXT: v_or_b32_e32 v20, v42, v20
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v61
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v35
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v25, v20
-; SI-NEXT: v_or_b32_e32 v18, v48, v18
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v58
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v34
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v47, v18
-; SI-NEXT: v_or_b32_e32 v16, v63, v16
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v47
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v33
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v54, v16
-; SI-NEXT: v_or_b32_e32 v14, v59, v14
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v44
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v32
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v14, v57, v14
-; SI-NEXT: v_or_b32_e32 v12, v45, v12
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v41
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v12, v62, v12
-; SI-NEXT: v_or_b32_e32 v10, v40, v10
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v54
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v51, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v36, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v61, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v60, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v58, v0
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v35
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v30
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v52
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v52
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v29
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v59
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v28
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v56
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v41
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v27
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v46
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v43
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v26
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v43
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v44
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v25
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v46, v2, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v42, v62, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v40, v60, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v55, v57, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v53, v45, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v51, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v44, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v50, v12, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v43, v6, 16
+; SI-NEXT: v_alignbit_b32 v0, v49, v14, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v41, v8, 16
+; SI-NEXT: v_alignbit_b32 v0, v48, v16, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v55, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v52, v12, 16
+; SI-NEXT: v_alignbit_b32 v0, v39, v18, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v49, v14, 16
+; SI-NEXT: v_alignbit_b32 v0, v38, v20, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v38, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v35, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v33, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v31, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v37, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v24, v27, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v31
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v24, v63, 16
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v39
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v38
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v37
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v62
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v27
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v35
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v42
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v40
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v57
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v55
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v45
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v53
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v41
-; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -36279,54 +37124,54 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v55
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v50
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v35
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v33
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v31
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v37
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index b52e8a54540dc..e3adc5f2e6b8e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -4895,15 +4895,58 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v57, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v38, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v11
; SI-NEXT: v_mov_b32_e32 v55, v10
; SI-NEXT: v_mov_b32_e32 v40, v9
@@ -4915,82 +4958,26 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v3
; SI-NEXT: v_mov_b32_e32 v47, v2
; SI-NEXT: v_mov_b32_e32 v56, v1
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_mov_b32_e32 v57, v0
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v57
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5006,30 +4993,41 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v57
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v59
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_or_b32_e32 v4, v4, v58
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v33
-; SI-NEXT: v_or_b32_e32 v8, v8, v62
-; SI-NEXT: v_or_b32_e32 v9, v9, v32
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
@@ -5042,16 +5040,16 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -5059,33 +5057,43 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr53
@@ -5097,6 +5105,16 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -5170,94 +5188,115 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v36, v1
-; SI-NEXT: v_or_b32_e32 v2, v59, v2
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
-; SI-NEXT: v_or_b32_e32 v4, v58, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v33, v7
-; SI-NEXT: v_or_b32_e32 v8, v62, v8
-; SI-NEXT: v_or_b32_e32 v9, v32, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -5276,9 +5315,18 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -5919,65 +5967,165 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v26i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6004,7 +6152,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9822,65 +9969,165 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v26i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9907,7 +10154,6 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -15437,15 +15683,58 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v57, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v38, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v11
; SI-NEXT: v_mov_b32_e32 v55, v10
; SI-NEXT: v_mov_b32_e32 v40, v9
@@ -15457,82 +15746,26 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v3
; SI-NEXT: v_mov_b32_e32 v47, v2
; SI-NEXT: v_mov_b32_e32 v56, v1
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_mov_b32_e32 v57, v0
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v57
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -15548,30 +15781,41 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v57
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v59
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_or_b32_e32 v4, v4, v58
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v33
-; SI-NEXT: v_or_b32_e32 v8, v8, v62
-; SI-NEXT: v_or_b32_e32 v9, v9, v32
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
@@ -15584,16 +15828,16 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -15601,33 +15845,43 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr53
@@ -15639,6 +15893,16 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -15712,94 +15976,115 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v36, v1
-; SI-NEXT: v_or_b32_e32 v2, v59, v2
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
-; SI-NEXT: v_or_b32_e32 v4, v58, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v33, v7
-; SI-NEXT: v_or_b32_e32 v8, v62, v8
-; SI-NEXT: v_or_b32_e32 v9, v32, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -15818,9 +16103,18 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -16461,65 +16755,165 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v26f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -16546,7 +16940,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20679,65 +21072,165 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v26f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20764,7 +21257,6 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -24614,15 +25106,58 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v57, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v38, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v11
; SI-NEXT: v_mov_b32_e32 v55, v10
; SI-NEXT: v_mov_b32_e32 v40, v9
@@ -24634,82 +25169,26 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v3
; SI-NEXT: v_mov_b32_e32 v47, v2
; SI-NEXT: v_mov_b32_e32 v56, v1
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_mov_b32_e32 v57, v0
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v57
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -24725,30 +25204,41 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v57
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v59
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_or_b32_e32 v4, v4, v58
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v33
-; SI-NEXT: v_or_b32_e32 v8, v8, v62
-; SI-NEXT: v_or_b32_e32 v9, v9, v32
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
@@ -24761,16 +25251,16 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -24778,33 +25268,43 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr53
@@ -24816,6 +25316,16 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -24889,94 +25399,115 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v36, v1
-; SI-NEXT: v_or_b32_e32 v2, v59, v2
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
-; SI-NEXT: v_or_b32_e32 v4, v58, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v33, v7
-; SI-NEXT: v_or_b32_e32 v8, v62, v8
-; SI-NEXT: v_or_b32_e32 v9, v32, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -24995,9 +25526,18 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -25638,65 +26178,165 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v13i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -25723,7 +26363,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29555,65 +30194,165 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v13i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29640,7 +30379,6 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32598,15 +33336,58 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v57, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v37, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v38, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v11
; SI-NEXT: v_mov_b32_e32 v55, v10
; SI-NEXT: v_mov_b32_e32 v40, v9
@@ -32618,82 +33399,26 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v3
; SI-NEXT: v_mov_b32_e32 v47, v2
; SI-NEXT: v_mov_b32_e32 v56, v1
-; SI-NEXT: s_waitcnt expcnt(6)
-; SI-NEXT: v_mov_b32_e32 v57, v0
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v57
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -32709,30 +33434,41 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v57
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: v_or_b32_e32 v2, v2, v59
-; SI-NEXT: v_or_b32_e32 v3, v3, v35
-; SI-NEXT: v_or_b32_e32 v4, v4, v58
-; SI-NEXT: v_or_b32_e32 v5, v5, v34
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v33
-; SI-NEXT: v_or_b32_e32 v8, v8, v62
-; SI-NEXT: v_or_b32_e32 v9, v9, v32
-; SI-NEXT: v_or_b32_e32 v10, v10, v61
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr47
@@ -32745,16 +33481,16 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -32762,33 +33498,43 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr53
@@ -32800,6 +33546,16 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
@@ -32873,94 +33629,115 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v34
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v54
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v36, v1
-; SI-NEXT: v_or_b32_e32 v2, v59, v2
-; SI-NEXT: v_or_b32_e32 v3, v35, v3
-; SI-NEXT: v_or_b32_e32 v4, v58, v4
-; SI-NEXT: v_or_b32_e32 v5, v34, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v33, v7
-; SI-NEXT: v_or_b32_e32 v8, v62, v8
-; SI-NEXT: v_or_b32_e32 v9, v32, v9
-; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -32979,9 +33756,18 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -33622,65 +34408,165 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v13f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -33707,7 +34593,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -37740,65 +38625,165 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v13f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v25 :: v_dual_mov_b32 v33, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v23 :: v_dual_mov_b32 v35, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v21 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v19 :: v_dual_mov_b32 v39, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v17 :: v_dual_mov_b32 v49, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v53, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v11 :: v_dual_mov_b32 v55, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v9 :: v_dual_mov_b32 v65, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v7 :: v_dual_mov_b32 v67, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v5 :: v_dual_mov_b32 v69, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v3 :: v_dual_mov_b32 v71, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v1 :: v_dual_mov_b32 v81, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v81
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v65, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v66, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v67, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v68, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v64, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v55, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v53, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v52, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v51, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v50, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v49, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v48, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v39, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v38, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v37, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v36, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v35, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v31, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v30, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v29, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v131, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v130, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v129, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v128, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v119, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v118, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v117, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v116, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v115, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v114, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v113, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v103, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v101, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v100, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v99, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v98, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v96, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v85, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v84, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v82, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -37825,7 +38810,6 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -38933,58 +39917,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v52i16_to_v52f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v9
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v39
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v11
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v37
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v13
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v33
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v32
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
@@ -39032,169 +39965,222 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v51
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v48
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v47
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v45
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v55
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v25
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v16
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v9
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v0
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v40
-; SI-NEXT: v_or_b32_e32 v59, v1, v26
-; SI-NEXT: v_mov_b32_e32 v26, v32
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v59, v32, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_or_b32_e32 v43, v1, v26
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v47
+; SI-NEXT: v_alignbit_b32 v26, v43, v1, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v53
-; SI-NEXT: v_or_b32_e32 v57, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v57, v54, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; SI-NEXT: v_or_b32_e32 v42, v3, v26
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57
+; SI-NEXT: v_alignbit_b32 v26, v42, v3, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
-; SI-NEXT: v_or_b32_e32 v47, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v47, v41, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v29
+; SI-NEXT: v_or_b32_e32 v41, v5, v26
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v45
+; SI-NEXT: v_alignbit_b32 v26, v41, v5, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
-; SI-NEXT: v_or_b32_e32 v45, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v30
+; SI-NEXT: v_or_b32_e32 v40, v7, v26
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v58
+; SI-NEXT: v_alignbit_b32 v26, v40, v7, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
-; SI-NEXT: v_or_b32_e32 v43, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v43, v58, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v31
+; SI-NEXT: v_or_b32_e32 v55, v9, v26
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
+; SI-NEXT: v_alignbit_b32 v26, v55, v9, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
-; SI-NEXT: v_or_b32_e32 v42, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v42, v63, 16
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v32
+; SI-NEXT: v_or_b32_e32 v54, v11, v26
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
+; SI-NEXT: v_alignbit_b32 v26, v54, v11, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v33
+; SI-NEXT: v_or_b32_e32 v53, v13, v26
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v44
+; SI-NEXT: v_alignbit_b32 v26, v53, v13, 16
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v34
+; SI-NEXT: v_or_b32_e32 v52, v15, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
+; SI-NEXT: v_or_b32_e32 v51, v17, v26
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v36
+; SI-NEXT: v_or_b32_e32 v50, v17, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v37
+; SI-NEXT: v_or_b32_e32 v49, v17, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v27
+; SI-NEXT: v_or_b32_e32 v48, v17, v19
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v39
+; SI-NEXT: v_or_b32_e32 v26, v17, v19
+; SI-NEXT: v_alignbit_b32 v17, v52, v15, 16
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v59
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v51, v17, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v62
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
-; SI-NEXT: v_or_b32_e32 v55, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v50, v0, 16
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v46
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v2, v49, v1, 16
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v56
+; SI-NEXT: v_or_b32_e32 v3, v3, v7
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_alignbit_b32 v1, v55, v60, 16
-; SI-NEXT: v_or_b32_e32 v0, v0, v58
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v3, v48, v2, 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v4, v26, v3, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v4, v4, v11
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v4, v4, v13
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v61
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v4, v4, v15
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v4, v4, v17
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v27
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
-; SI-NEXT: v_mov_b32_e32 v32, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
@@ -39208,343 +40194,285 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_or_b32_e32 v52, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v52, v56, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v49, v1, v29
-; SI-NEXT: v_alignbit_b32 v1, v49, v61, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v38, v1, v30
-; SI-NEXT: v_alignbit_b32 v1, v38, v62, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v36, v1, v51
-; SI-NEXT: v_alignbit_b32 v1, v36, v27, 16
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_or_b32_e32 v34, v1, v48
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_alignbit_b32 v1, v34, v28, 16
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_or_b32_e32 v3, v1, v31
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_alignbit_b32 v1, v3, v44, 16
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v26, v3
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; kill: killed $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v44, v24
-; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v24
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v60
+; SI-NEXT: v_or_b32_e32 v24, v26, v24
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x30000, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v39
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v24, v31, v24
-; SI-NEXT: v_or_b32_e32 v22, v28, v22
-; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v38
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v22, v48, v22
-; SI-NEXT: v_or_b32_e32 v20, v27, v20
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v46
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v37
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v51, v20
-; SI-NEXT: v_or_b32_e32 v18, v62, v18
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v20
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v62
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v36
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v30, v18
-; SI-NEXT: v_or_b32_e32 v16, v61, v16
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v59
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v35
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v29, v16
-; SI-NEXT: v_or_b32_e32 v14, v56, v14
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v27
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v60, v12
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v58, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v46, v6
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v41, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v54, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v14
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v44
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v33
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v12
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v61
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v10
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v63
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v42
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v31
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v8
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v43
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v45
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v45
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v29
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v57
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v47
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v57
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v47
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v26
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v59, v2, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v43, v2, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v57, v4, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v42, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v47, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v41, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v45, v8, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v40, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v43, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v55, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v42, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v54, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v55, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v53, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v52, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v49, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v51, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v38, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v50, v20, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v36, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v49, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v34, v24, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v48, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v26, v32, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v34
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v26, v60, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v35
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v38
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v59
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v43
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: s_waitcnt vmcnt(3)
@@ -39556,33 +40484,21 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v57
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v42
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v47
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v45
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
-; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -39600,48 +40516,58 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v55
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v54
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v55
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v53
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v49
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v38
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v50
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v36
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v34
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v48
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v39
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index a24315e66392c..1b9bc9b6e0f6c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -5224,15 +5224,70 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v59, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v38, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v39, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v10
; SI-NEXT: v_mov_b32_e32 v42, v9
; SI-NEXT: v_mov_b32_e32 v43, v8
@@ -5241,133 +5296,76 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v5
; SI-NEXT: v_mov_b32_e32 v47, v4
; SI-NEXT: v_mov_b32_e32 v56, v3
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v2
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v1
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_mov_b32_e32 v59, v0
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -5379,51 +5377,69 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v39
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -5431,14 +5447,20 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -5514,54 +5536,62 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v37
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -5569,41 +5599,69 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v38
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -5614,32 +5672,31 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -6338,69 +6395,176 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56i16_to_v28i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6429,7 +6593,6 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10676,69 +10839,176 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56f16_to_v28i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -10767,7 +11037,6 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16695,15 +16964,70 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v59, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v38, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v39, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v10
; SI-NEXT: v_mov_b32_e32 v42, v9
; SI-NEXT: v_mov_b32_e32 v43, v8
@@ -16712,133 +17036,76 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v5
; SI-NEXT: v_mov_b32_e32 v47, v4
; SI-NEXT: v_mov_b32_e32 v56, v3
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v2
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v1
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_mov_b32_e32 v59, v0
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -16850,51 +17117,69 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v39
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -16902,14 +17187,20 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -16985,54 +17276,62 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v37
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -17040,41 +17339,69 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v38
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -17085,32 +17412,31 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -17809,69 +18135,176 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56i16_to_v28f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -17900,7 +18333,6 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -22510,69 +22942,176 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56f16_to_v28f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -22601,7 +23140,6 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -26755,15 +27293,70 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v59, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v38, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v39, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v10
; SI-NEXT: v_mov_b32_e32 v42, v9
; SI-NEXT: v_mov_b32_e32 v43, v8
@@ -26772,133 +27365,76 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v5
; SI-NEXT: v_mov_b32_e32 v47, v4
; SI-NEXT: v_mov_b32_e32 v56, v3
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v2
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v1
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_mov_b32_e32 v59, v0
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -26910,51 +27446,69 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v39
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -26962,14 +27516,20 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -27045,54 +27605,62 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v37
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -27100,41 +27668,69 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v38
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -27145,32 +27741,31 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -27869,69 +28464,176 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56i16_to_v14i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -27960,7 +28662,6 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32221,69 +32922,176 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56f16_to_v14i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -32312,7 +33120,6 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -35570,15 +36377,70 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_mov_b32_e32 v59, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v38, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; SI-NEXT: v_mov_b32_e32 v39, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v10
; SI-NEXT: v_mov_b32_e32 v42, v9
; SI-NEXT: v_mov_b32_e32 v43, v8
@@ -35587,133 +36449,76 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v46, v5
; SI-NEXT: v_mov_b32_e32 v47, v4
; SI-NEXT: v_mov_b32_e32 v56, v3
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v2
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v1
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: v_mov_b32_e32 v59, v0
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v21
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v43
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -35725,51 +36530,69 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v39
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -35777,14 +36600,20 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -35860,54 +36689,62 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v37
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v42
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -35915,41 +36752,69 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v11, v12, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v38
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
@@ -35960,32 +36825,31 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -36684,69 +37548,176 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56i16_to_v14f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -36775,7 +37746,6 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -41280,69 +42250,176 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v56f16_to_v14f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v27 :: v_dual_mov_b32 v33, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v25 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v23 :: v_dual_mov_b32 v37, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v21 :: v_dual_mov_b32 v39, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v19 :: v_dual_mov_b32 v49, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v17 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v15 :: v_dual_mov_b32 v53, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v13 :: v_dual_mov_b32 v55, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v11 :: v_dual_mov_b32 v65, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v9 :: v_dual_mov_b32 v67, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v7 :: v_dual_mov_b32 v69, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v5 :: v_dual_mov_b32 v71, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v3 :: v_dual_mov_b32 v81, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v1 :: v_dual_mov_b32 v83, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v83
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v69, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v70, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v71, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v68, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v67, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v66, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v65, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v64, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v54, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v52, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v49, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v38, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v35, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v34, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v33, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v32, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v31, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v135, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v134, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v133, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v132, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v131, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v130, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v129, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v128, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v119, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v117, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v115, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v114, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v112, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v103, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v101, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v100, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v99, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v98, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v97, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v87, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v85, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -41371,7 +42448,6 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -42570,67 +43646,7 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v56i16_to_v56f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v3
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v9
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v11
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v13
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v58
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
@@ -42672,76 +43688,91 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v14
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v12
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v10
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v8
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v47
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v45
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v44
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v27
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v21
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v9
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v2
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v0
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -42749,502 +43780,488 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v54
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_or_b32_e32 v60, v1, v28
-; SI-NEXT: v_mov_b32_e32 v28, v39
-; SI-NEXT: v_mov_b32_e32 v39, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v29
+; SI-NEXT: v_or_b32_e32 v47, v1, v28
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v58
+; SI-NEXT: v_alignbit_b32 v28, v47, v1, 16
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v30
+; SI-NEXT: v_or_b32_e32 v46, v3, v28
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
+; SI-NEXT: v_alignbit_b32 v28, v46, v3, 16
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v31
+; SI-NEXT: v_or_b32_e32 v45, v5, v28
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61
+; SI-NEXT: v_alignbit_b32 v28, v45, v5, 16
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v32
+; SI-NEXT: v_or_b32_e32 v44, v7, v28
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v33
+; SI-NEXT: v_or_b32_e32 v43, v9, v28
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v34
+; SI-NEXT: v_or_b32_e32 v42, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v35
+; SI-NEXT: v_or_b32_e32 v41, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v36
+; SI-NEXT: v_or_b32_e32 v40, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v37
+; SI-NEXT: v_or_b32_e32 v55, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
+; SI-NEXT: v_or_b32_e32 v54, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v39
+; SI-NEXT: v_or_b32_e32 v53, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v48
+; SI-NEXT: v_or_b32_e32 v52, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v62
+; SI-NEXT: v_or_b32_e32 v51, v9, v11
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v50
+; SI-NEXT: v_or_b32_e32 v28, v9, v11
+; SI-NEXT: v_alignbit_b32 v9, v44, v7, 16
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v60, v43, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
-; SI-NEXT: v_or_b32_e32 v58, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v58, v39, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v43, v9, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
-; SI-NEXT: v_or_b32_e32 v57, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v43
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v42, v0, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_mov_b32_e32 v39, v28
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v1, v57, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_or_b32_e32 v47, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v2, v41, v1, 16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v47, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v3, v3, v7
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v45, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v3, v40, v2, 16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v9
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v4, v55, v3, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v18
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v0, v5, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v54, v4, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v63
+; SI-NEXT: v_or_b32_e32 v1, v5, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v29
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v53, v0, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v56
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v2, v52, v1, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v57
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v3, v51, v2, 16
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v59
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v4, v28, v3, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: ; kill: killed $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v63
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: ; kill: killed $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v0, v0, v61
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: ; kill: killed $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_or_b32_e32 v44, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v44, v56, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v42, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v42, v59, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v40, v1, v35
-; SI-NEXT: v_alignbit_b32 v1, v40, v62, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v55, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v55, v29, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v53, v1, v34
-; SI-NEXT: v_alignbit_b32 v1, v53, v30, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v52, v1, v41
-; SI-NEXT: v_alignbit_b32 v1, v52, v31, 16
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v50, v1, v37
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_alignbit_b32 v1, v50, v32, 16
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v48, v1, v33
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_alignbit_b32 v1, v48, v63, 16
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v3, v1, v38
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_alignbit_b32 v1, v3, v61, 16
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v28, v3
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; kill: killed $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v26, v61, v26
-; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v26
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v59
+; SI-NEXT: v_or_b32_e32 v26, v28, v26
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v26
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v50
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v26, v38, v26
-; SI-NEXT: v_or_b32_e32 v24, v63, v24
+; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v26
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v57
+; SI-NEXT: v_or_b32_e32 v24, v26, v24
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v49
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v24
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v24, v33, v24
-; SI-NEXT: v_or_b32_e32 v22, v32, v22
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v24
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v48
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
+; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v22, v37, v22
-; SI-NEXT: v_or_b32_e32 v20, v31, v20
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v22
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v63
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v39
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v41, v20
-; SI-NEXT: v_or_b32_e32 v18, v30, v18
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v34, v18
-; SI-NEXT: v_or_b32_e32 v16, v29, v16
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_or_b32_e32 v14, v62, v14
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v14, v35, v14
-; SI-NEXT: v_or_b32_e32 v12, v59, v12
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v56, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v46, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v51
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v54
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v37
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v55
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v36
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
+; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v35
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v41
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v34
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v42
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v33
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v62
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v61
; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v31
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v60
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v57
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v30
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v58
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v60, v2, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v47, v2, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v58, v4, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v46, v4, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v57, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v45, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v47, v8, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v44, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v45, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v43, v10, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v44, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v42, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v42, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v41, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v40, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v55, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v53, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v54, v20, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v52, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v53, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v50, v24, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v52, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v48, v26, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v51, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v28, v39, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v47
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v28, v59, 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v51
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v49
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v47
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(7)
@@ -43264,45 +44281,45 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v45
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NEXT: v_and_b32_e32 v7, 0xffff, v47
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v44
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v45
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v43
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v44
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v42
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -43324,38 +44341,36 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v53
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v54
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v52
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v53
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v50
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v48
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v50
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index d6cf0367f1b20..4485e7e1a2911 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -5584,161 +5584,156 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mov_b32_e32 v61, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v48, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v49, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
; SI-NEXT: v_mov_b32_e32 v42, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
; SI-NEXT: v_mov_b32_e32 v43, v10
; SI-NEXT: v_mov_b32_e32 v44, v9
; SI-NEXT: v_mov_b32_e32 v45, v8
; SI-NEXT: v_mov_b32_e32 v46, v7
; SI-NEXT: v_mov_b32_e32 v47, v6
; SI-NEXT: v_mov_b32_e32 v56, v5
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v4
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v3
-; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_mov_b32_e32 v59, v2
-; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v60, v1
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mov_b32_e32 v61, v0
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v60
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v61
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v48
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v39
-; SI-NEXT: v_or_b32_e32 v4, v4, v34
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v37
-; SI-NEXT: v_or_b32_e32 v8, v8, v33
-; SI-NEXT: v_or_b32_e32 v9, v9, v36
-; SI-NEXT: v_or_b32_e32 v10, v10, v62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
@@ -5750,53 +5745,68 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -5806,10 +5816,23 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -5901,53 +5924,62 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v4, v34, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: v_or_b32_e32 v8, v33, v8
-; SI-NEXT: v_or_b32_e32 v9, v36, v9
-; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -5955,50 +5987,70 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v48
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -6009,27 +6061,36 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -6792,73 +6853,187 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v30i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6889,7 +7064,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11403,73 +11577,187 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v30i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -11500,7 +11788,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17854,161 +18141,156 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mov_b32_e32 v61, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v48, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v49, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
; SI-NEXT: v_mov_b32_e32 v42, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
; SI-NEXT: v_mov_b32_e32 v43, v10
; SI-NEXT: v_mov_b32_e32 v44, v9
; SI-NEXT: v_mov_b32_e32 v45, v8
; SI-NEXT: v_mov_b32_e32 v46, v7
; SI-NEXT: v_mov_b32_e32 v47, v6
; SI-NEXT: v_mov_b32_e32 v56, v5
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v4
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v3
-; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_mov_b32_e32 v59, v2
-; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v60, v1
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mov_b32_e32 v61, v0
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v60
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v61
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v48
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v39
-; SI-NEXT: v_or_b32_e32 v4, v4, v34
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v37
-; SI-NEXT: v_or_b32_e32 v8, v8, v33
-; SI-NEXT: v_or_b32_e32 v9, v9, v36
-; SI-NEXT: v_or_b32_e32 v10, v10, v62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
@@ -18020,53 +18302,68 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -18076,10 +18373,23 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -18171,53 +18481,62 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v4, v34, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: v_or_b32_e32 v8, v33, v8
-; SI-NEXT: v_or_b32_e32 v9, v36, v9
-; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -18225,50 +18544,70 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v48
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -18279,27 +18618,36 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -19062,73 +19410,187 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v30f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -19159,7 +19621,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -24080,73 +24541,187 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v30f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -24177,7 +24752,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -28637,161 +29211,156 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mov_b32_e32 v61, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v48, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v49, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
; SI-NEXT: v_mov_b32_e32 v42, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
; SI-NEXT: v_mov_b32_e32 v43, v10
; SI-NEXT: v_mov_b32_e32 v44, v9
; SI-NEXT: v_mov_b32_e32 v45, v8
; SI-NEXT: v_mov_b32_e32 v46, v7
; SI-NEXT: v_mov_b32_e32 v47, v6
; SI-NEXT: v_mov_b32_e32 v56, v5
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v4
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v3
-; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_mov_b32_e32 v59, v2
-; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v60, v1
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mov_b32_e32 v61, v0
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v60
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v61
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v48
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v39
-; SI-NEXT: v_or_b32_e32 v4, v4, v34
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v37
-; SI-NEXT: v_or_b32_e32 v8, v8, v33
-; SI-NEXT: v_or_b32_e32 v9, v9, v36
-; SI-NEXT: v_or_b32_e32 v10, v10, v62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
@@ -28803,53 +29372,68 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -28859,10 +29443,23 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -28954,53 +29551,62 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v4, v34, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: v_or_b32_e32 v8, v33, v8
-; SI-NEXT: v_or_b32_e32 v9, v36, v9
-; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -29008,50 +29614,70 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v48
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -29062,27 +29688,36 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -29845,73 +30480,187 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v15i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -29942,7 +30691,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -34472,73 +35220,187 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v15i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34569,7 +35431,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -38103,161 +38964,156 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_mov_b32_e32 v61, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; SI-NEXT: v_mov_b32_e32 v48, v21
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: v_mov_b32_e32 v49, v20
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v18
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: v_mov_b32_e32 v52, v17
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_mov_b32_e32 v53, v16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; SI-NEXT: v_mov_b32_e32 v54, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: v_mov_b32_e32 v55, v14
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; SI-NEXT: v_mov_b32_e32 v40, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
; SI-NEXT: v_mov_b32_e32 v41, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v40
; SI-NEXT: v_mov_b32_e32 v42, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
; SI-NEXT: v_mov_b32_e32 v43, v10
; SI-NEXT: v_mov_b32_e32 v44, v9
; SI-NEXT: v_mov_b32_e32 v45, v8
; SI-NEXT: v_mov_b32_e32 v46, v7
; SI-NEXT: v_mov_b32_e32 v47, v6
; SI-NEXT: v_mov_b32_e32 v56, v5
-; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mov_b32_e32 v57, v4
-; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mov_b32_e32 v58, v3
-; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_mov_b32_e32 v59, v2
-; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v60, v1
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_mov_b32_e32 v61, v0
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v29
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v26
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v25
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v24
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v23
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
-; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
-; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
-; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
-; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v56
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
-; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
-; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v61
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v43
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v44
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v45
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v57
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v58
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v60
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v61
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v60
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v59
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v58
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v57
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v47
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v45
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v44
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: v_or_b32_e32 v1, v1, v48
-; SI-NEXT: v_or_b32_e32 v2, v2, v32
-; SI-NEXT: v_or_b32_e32 v3, v3, v39
-; SI-NEXT: v_or_b32_e32 v4, v4, v34
-; SI-NEXT: v_or_b32_e32 v5, v5, v38
-; SI-NEXT: v_or_b32_e32 v6, v6, v63
-; SI-NEXT: v_or_b32_e32 v7, v7, v37
-; SI-NEXT: v_or_b32_e32 v8, v8, v33
-; SI-NEXT: v_or_b32_e32 v9, v9, v36
-; SI-NEXT: v_or_b32_e32 v10, v10, v62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr59
@@ -38269,53 +39125,68 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v41
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v40
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v55
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v54
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v53
; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v52
; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v51
; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
@@ -38325,10 +39196,23 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -38420,53 +39304,62 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v61
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v63
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v58
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v33
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v57
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v37
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v32
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
+; SI-NEXT: v_or_b32_e32 v7, v8, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v62
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v44
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
+; SI-NEXT: v_or_b32_e32 v9, v10, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_or_b32_e32 v2, v32, v2
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
-; SI-NEXT: v_or_b32_e32 v4, v34, v4
-; SI-NEXT: v_or_b32_e32 v5, v38, v5
-; SI-NEXT: v_or_b32_e32 v6, v63, v6
-; SI-NEXT: v_or_b32_e32 v7, v37, v7
-; SI-NEXT: v_or_b32_e32 v8, v33, v8
-; SI-NEXT: v_or_b32_e32 v9, v36, v9
-; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
@@ -38474,50 +39367,70 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v42
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v21, v20
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v48
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v21, v22, v21
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
@@ -38528,27 +39441,36 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -39311,73 +40233,187 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v15f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -39408,7 +40444,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -44216,73 +45251,187 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v15f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v27 :: v_dual_mov_b32 v35, v26
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v25 :: v_dual_mov_b32 v37, v24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v23 :: v_dual_mov_b32 v39, v22
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v21 :: v_dual_mov_b32 v49, v20
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v19 :: v_dual_mov_b32 v51, v18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v17 :: v_dual_mov_b32 v53, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v15 :: v_dual_mov_b32 v55, v14
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v13 :: v_dual_mov_b32 v65, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v11 :: v_dual_mov_b32 v67, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, v9 :: v_dual_mov_b32 v69, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v7 :: v_dual_mov_b32 v71, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v3 :: v_dual_mov_b32 v83, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, v1 :: v_dual_mov_b32 v85, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v35
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v53
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v54
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v55
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v66
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v68
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v69
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v71
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v85
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v81, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v82, v1, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v84, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v80, v4, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v71, v5, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v70, v6, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v69, v7, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v67, v9, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v66, v10, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v11, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v64, v12, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v55, v13, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v54, v14, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v15, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v52, v16, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v17, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v50, v18, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v49, v19, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v48, v20, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v39, v21, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v37, v23, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v36, v24, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v35, v25, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v34, v26, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v33, v27, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v147, v85, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v146, v84, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v145, v83, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v144, v82, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v135, v81, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v134, v80, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v133, v71, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v132, v70, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v131, v69, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v130, v68, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v129, v67, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v128, v66, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v119, v65, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v118, v64, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v117, v55, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v116, v54, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v115, v53, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v114, v52, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v113, v51, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v112, v50, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v103, v49, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v102, v48, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v101, v39, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v100, v38, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v99, v37, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v98, v36, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v97, v35, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v96, v34, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v87, v33, 0x5040100
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v86, v32, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -44313,7 +45462,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -45588,7 +46736,94 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v60i16_to_v60f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
+; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v0
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v18
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v12
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v10
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v6
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v4
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v2
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -45605,734 +46840,582 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v28
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v23
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
-; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v0
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v52
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v51
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v1
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v3
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v43
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v40
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v7
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v22
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v3
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v53
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v9
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v59
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v58
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v13
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v57
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v56
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v28
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v19
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
-; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v47
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v49
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v46
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v45
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; kill: killed $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; kill: killed $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v54, v53
-; SI-NEXT: v_mov_b32_e32 v53, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v43
-; SI-NEXT: v_or_b32_e32 v45, v1, v48
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v31, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v31
+; SI-NEXT: v_or_b32_e32 v56, v1, v30
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
; SI-NEXT: v_or_b32_e32 v63, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v63, v3, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v61, v1, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v61, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; SI-NEXT: v_or_b32_e32 v61, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
+; SI-NEXT: v_or_b32_e32 v59, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
+; SI-NEXT: v_or_b32_e32 v57, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36
+; SI-NEXT: v_or_b32_e32 v47, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
+; SI-NEXT: v_or_b32_e32 v45, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
+; SI-NEXT: v_or_b32_e32 v44, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
+; SI-NEXT: v_or_b32_e32 v43, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; SI-NEXT: v_or_b32_e32 v42, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
+; SI-NEXT: v_or_b32_e32 v41, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_or_b32_e32 v40, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
+; SI-NEXT: v_or_b32_e32 v55, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v52
+; SI-NEXT: v_or_b32_e32 v54, v1, v3
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v29
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v53
+; SI-NEXT: v_or_b32_e32 v30, v1, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v59, v1, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v59, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v56, v1, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v7
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v63, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v53
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v61, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v33
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v34
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v59, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v0, v0, v35
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v0, v0, v36
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v57, v0, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v0, v0, v37
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v47, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v0, v0, v38
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v45, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v28
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_or_b32_e32 v57, v1, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v57, v53, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_mov_b32_e32 v53, v54
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v56, v1, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v56, v32, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v44, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v46, v1, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v46, v33, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v44, v1, v9
-; SI-NEXT: v_alignbit_b32 v1, v44, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v43, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v42, v1, v47
-; SI-NEXT: v_alignbit_b32 v1, v42, v35, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v41, v1, v49
-; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v42, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v55, v1, v30
-; SI-NEXT: v_alignbit_b32 v1, v55, v60, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_or_b32_e32 v9, v1, v58
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_alignbit_b32 v1, v9, v37, 16
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v41, v0, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_or_b32_e32 v1, v1, v50
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v62
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v40, v0, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v1, v62, 16
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v58
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v55, v0, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_or_b32_e32 v48, v1, v51
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_alignbit_b32 v1, v48, v38, 16
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v60
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v54, v0, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v29
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_or_b32_e32 v1, v1, v52
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v1, v39, 16
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v54, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_alignbit_b32 v0, v30, v0, 16
+; SI-NEXT: ; kill: killed $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; kill: killed $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr46
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
-; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v28, v39, v28
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v26, v38, v26
-; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v28
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v46
+; SI-NEXT: v_or_b32_e32 v28, v30, v28
+; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v28
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v26
+; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v53
+; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v28, v29, v28
+; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
+; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v28
+; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v60
+; SI-NEXT: v_or_b32_e32 v26, v28, v26
+; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v26
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v27
-; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
-; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v52
+; SI-NEXT: v_or_b32_e32 v26, v27, v26
+; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
+; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v26
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v26, v51, v26
-; SI-NEXT: v_or_b32_e32 v24, v62, v24
-; SI-NEXT: v_or_b32_e32 v22, v37, v22
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v26
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v58
+; SI-NEXT: v_or_b32_e32 v24, v26, v24
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v22
+; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v51
+; SI-NEXT: v_or_b32_e32 v24, v25, v24
+; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
+; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v24
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v62
+; SI-NEXT: v_or_b32_e32 v22, v24, v22
+; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v50
+; SI-NEXT: v_or_b32_e32 v22, v23, v22
+; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v22, v58, v22
-; SI-NEXT: v_or_b32_e32 v20, v60, v20
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v22
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v30, v20
-; SI-NEXT: v_or_b32_e32 v18, v36, v18
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v49, v18
-; SI-NEXT: v_or_b32_e32 v16, v35, v16
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v47, v16
-; SI-NEXT: v_or_b32_e32 v14, v34, v14
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v33, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v32, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v31, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v50, v24
-; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
-; SI-NEXT: v_or_b32_e32 v28, v52, v28
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v55
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_or_b32_e32 v20, v22, v20
+; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v49
+; SI-NEXT: v_or_b32_e32 v20, v21, v20
+; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v41
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_or_b32_e32 v18, v20, v18
+; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
+; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v48
+; SI-NEXT: v_or_b32_e32 v18, v19, v18
+; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v42
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v16, v18, v16
+; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v39
+; SI-NEXT: v_or_b32_e32 v16, v17, v16
+; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v43
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v38
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v37
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v45
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_or_b32_e32 v10, v12, v10
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v36
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v47
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v57
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v59
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v33
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v61
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v61
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v63
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v31
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
-; SI-NEXT: v_alignbit_b32 v0, v45, v2, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v0
+; SI-NEXT: v_alignbit_b32 v0, v56, v2, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v63, v4, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v61, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v59, v8, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v57, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v56, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v47, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v46, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v45, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v44, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v42, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v41, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v55, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v43, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v54, v25, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v42, v20, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v24, v26, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v41, v22, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v48, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v40, v24, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v28, v39, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v59
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v57
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v56
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v46
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v44
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v42
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v41
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v55
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v55, v26, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v45
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v54, v28, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v30, v46, 16
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v56
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v35
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v52
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v45
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v56
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(7)
@@ -46347,7 +47430,6 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -46355,55 +47437,67 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) {
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v63
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v61
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v59
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v57
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff, v56
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v47
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v46
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v45
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v44
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v42
+; SI-NEXT: v_and_b32_e32 v17, 0xffff, v43
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
-; SI-NEXT: v_and_b32_e32 v19, 0xffff, v41
+; SI-NEXT: v_and_b32_e32 v19, 0xffff, v42
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: v_and_b32_e32 v21, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v21, v21, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_and_b32_e32 v23, 0xffff, v40
+; SI-NEXT: v_or_b32_e32 v23, v23, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -46421,37 +47515,22 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v20, v20, v21
-; SI-NEXT: v_and_b32_e32 v21, 0xffff, v55
-; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v22, v22, v23
-; SI-NEXT: v_and_b32_e32 v23, 0xffff, v54
-; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
+; SI-NEXT: v_and_b32_e32 v25, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: v_and_b32_e32 v27, 0xffff, v48
+; SI-NEXT: v_and_b32_e32 v27, 0xffff, v54
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; SI-NEXT: v_and_b32_e32 v29, 0xffff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v53
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 23a43ff3b2f87..df9cbc8452a2e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -862,15 +862,10 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v12i8_to_v3i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v14, v2
-; SI-NEXT: v_mov_b32_e32 v13, v0
+; SI-NEXT: v_mov_b32_e32 v15, v2
+; SI-NEXT: v_mov_b32_e32 v13, v1
+; SI-NEXT: v_mov_b32_e32 v14, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -882,69 +877,81 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB6_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v13
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v16
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v15, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v12
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: .LBB6_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v0, v16, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v15, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v12, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v3, v3, v4
@@ -1811,18 +1818,12 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -1834,35 +1835,47 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB10_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v6, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v4, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB10_2
; SI-NEXT: .LBB10_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3248,13 +3261,10 @@ define <3 x i32> @bitcast_v6i16_to_v3i32(<6 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v6, v2
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v5, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -3267,28 +3277,34 @@ define <3 x i32> @bitcast_v6i16_to_v3i32(<6 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB18_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v8
-; SI-NEXT: v_or_b32_e32 v1, v1, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB18_2
; SI-NEXT: .LBB18_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v8, v0
-; SI-NEXT: v_or_b32_e32 v1, v7, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -4025,15 +4041,10 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) {
; SI-LABEL: bitcast_v12i8_to_v3f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v14, v2
-; SI-NEXT: v_mov_b32_e32 v13, v0
+; SI-NEXT: v_mov_b32_e32 v15, v2
+; SI-NEXT: v_mov_b32_e32 v13, v1
+; SI-NEXT: v_mov_b32_e32 v14, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -4045,69 +4056,81 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB22_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v13
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
-; SI-NEXT: v_or_b32_e32 v0, v0, v16
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v15, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v12
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v11
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: .LBB22_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v14
-; SI-NEXT: v_or_b32_e32 v0, v16, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v15, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v1, v12, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v9
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v3, v3, v4
@@ -4985,18 +5008,12 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v4, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -5008,35 +5025,47 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB26_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; SI-NEXT: v_alignbit_b32 v1, v1, v6, 16
-; SI-NEXT: v_alignbit_b32 v2, v2, v4, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: .LBB26_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -6438,13 +6467,10 @@ define <3 x float> @bitcast_v6i16_to_v3f32(<6 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v6, v2
; SI-NEXT: v_mov_b32_e32 v4, v1
; SI-NEXT: v_mov_b32_e32 v5, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -6457,28 +6483,34 @@ define <3 x float> @bitcast_v6i16_to_v3f32(<6 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB34_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v0, v0, v8
-; SI-NEXT: v_or_b32_e32 v1, v1, v7
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_2
; SI-NEXT: .LBB34_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v8, v0
-; SI-NEXT: v_or_b32_e32 v1, v7, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
@@ -6694,16 +6726,12 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v11
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB36_2
@@ -6711,95 +6739,103 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; SI-NEXT: v_or_b32_e32 v3, v1, v0
+; SI-NEXT: v_or_b32_e32 v12, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v5, v12, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_or_b32_e32 v13, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v11, v14, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
+; SI-NEXT: v_or_b32_e32 v15, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9
-; SI-NEXT: v_or_b32_e32 v13, v1, v0
+; SI-NEXT: v_or_b32_e32 v16, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v15, v16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
+; SI-NEXT: v_or_b32_e32 v17, v1, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: .LBB36_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB36_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v5, v16, v5
-; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v6
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v3, v17, v3
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x300, v8
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v4, v14, v4
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v12, v1
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v9, v8
+; SI-NEXT: s_mov_b32 s7, 0x3000000
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v8
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v4
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
; SI-NEXT: .LBB36_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v13
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v16
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7442,19 +7478,13 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v6bf16_to_v12i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v1
+; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v17, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -7477,42 +7507,54 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB38_3: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v12
-; SI-NEXT: v_alignbit_b32 v0, v0, v17, 16
-; SI-NEXT: v_alignbit_b32 v4, v6, v15, 16
-; SI-NEXT: v_alignbit_b32 v8, v10, v13, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v14
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v13
+; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
+; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v12
+; SI-NEXT: v_alignbit_b32 v4, v6, v1, 16
+; SI-NEXT: v_alignbit_b32 v8, v10, v8, 16
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
-; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v14
-; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v12
+; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v5
; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: .LBB38_4: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v17
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v14
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v15
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v7
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v12
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13
; SI-NEXT: v_alignbit_b32 v4, v6, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v11
@@ -8520,110 +8562,116 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v11
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB40_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v15
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v12, v3
-; SI-NEXT: v_or_b32_e32 v3, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v12, v0, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_or_b32_e32 v13, v4, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
+; SI-NEXT: v_alignbit_b32 v14, v13, v2, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NEXT: v_or_b32_e32 v11, v0, v2
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_or_b32_e32 v15, v0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: .LBB40_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB40_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v0, v15, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v0, v9, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v14, v13, v12, 16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
; SI-NEXT: .LBB40_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v17
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -9360,25 +9408,29 @@ define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) {
; VI-NEXT: v_mov_b32_e32 v14, v1
; VI-NEXT: v_mov_b32_e32 v13, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
; VI-NEXT: ; implicit-def: $vgpr1
+; VI-NEXT: ; implicit-def: $vgpr2
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB42_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v8
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v14
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v13
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[8:9]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14]
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v13
-; VI-NEXT: ; %bb.2: ; %Flow
+; VI-NEXT: .LBB42_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB42_4
; VI-NEXT: ; %bb.3: ; %cmp.true
@@ -9883,110 +9935,116 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v11
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v15
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v12, v3
-; SI-NEXT: v_or_b32_e32 v3, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v7
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_or_b32_e32 v1, v0, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: v_or_b32_e32 v12, v0, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: v_or_b32_e32 v13, v4, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
+; SI-NEXT: v_alignbit_b32 v14, v13, v2, 16
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v11
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NEXT: v_or_b32_e32 v11, v0, v2
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_or_b32_e32 v15, v0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: .LBB44_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_or_b32_e32 v0, v15, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v10
-; SI-NEXT: v_or_b32_e32 v0, v9, v0
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
-; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v14, v13, v12, 16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
; SI-NEXT: .LBB44_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v17
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -10637,11 +10695,8 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; SI-NEXT: v_mov_b32_e32 v14, v0
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v12
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v10
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -10663,11 +10718,14 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB46_3: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v17
-; SI-NEXT: v_or_b32_e32 v4, v1, v16
-; SI-NEXT: v_or_b32_e32 v8, v7, v15
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
+; SI-NEXT: v_or_b32_e32 v4, v1, v2
+; SI-NEXT: v_or_b32_e32 v8, v7, v8
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -10676,25 +10734,26 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; SI-NEXT: v_bfe_u32 v7, v6, 8, 8
; SI-NEXT: v_bfe_u32 v11, v10, 8, 8
; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_2
; SI-NEXT: .LBB46_4: ; %cmp.true
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v15
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_or_b32_e32 v1, v15, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
@@ -10713,29 +10772,32 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v0
-; VI-NEXT: ; implicit-def: $vgpr16
+; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
+; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: ; implicit-def: $vgpr8
; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB46_2
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v0
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v16, v0
+; VI-NEXT: v_mov_b32_e32 v13, v0
; VI-NEXT: v_mov_b32_e32 v14, v1
; VI-NEXT: v_mov_b32_e32 v8, v2
; VI-NEXT: ; implicit-def: $vgpr1
@@ -10746,13 +10808,13 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 3
; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v13, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v16, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v14, 3, v1
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
-; VI-NEXT: v_add_u16_e32 v16, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
+; VI-NEXT: v_add_u16_e32 v13, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; VI-NEXT: v_or_b32_e32 v1, v14, v1
-; VI-NEXT: v_or_b32_e32 v0, v16, v0
+; VI-NEXT: v_or_b32_e32 v0, v13, v0
; VI-NEXT: v_add_u16_sdwa v10, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
@@ -10765,9 +10827,9 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
; VI-NEXT: v_bfe_u32 v7, v6, 8, 8
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v0, v16
+; VI-NEXT: v_mov_b32_e32 v0, v13
; VI-NEXT: v_mov_b32_e32 v1, v15
-; VI-NEXT: v_mov_b32_e32 v2, v13
+; VI-NEXT: v_mov_b32_e32 v2, v16
; VI-NEXT: v_mov_b32_e32 v4, v14
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -11219,76 +11281,83 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v6bf16_to_v6f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v8
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v4
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB48_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_alignbit_b32 v4, v1, v7, 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v10
-; SI-NEXT: v_alignbit_b32 v5, v4, v0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; SI-NEXT: v_alignbit_b32 v0, v0, v11, 16
-; SI-NEXT: v_alignbit_b32 v3, v2, v9, 16
-; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v9
+; SI-NEXT: v_alignbit_b32 v3, v1, v0, 16
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; SI-NEXT: v_alignbit_b32 v5, v3, v2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
+; SI-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_mul_f32_e32 v4, 1.0, v7
+; SI-NEXT: v_alignbit_b32 v4, v2, v4, 16
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: .LBB48_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB48_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_alignbit_b32 v3, v2, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
+; SI-NEXT: v_alignbit_b32 v4, v2, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_alignbit_b32 v4, v1, v4, 16
+; SI-NEXT: v_alignbit_b32 v3, v1, v3, 16
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_alignbit_b32 v5, v4, v5, 16
+; SI-NEXT: v_alignbit_b32 v5, v3, v5, 16
; SI-NEXT: .LBB48_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -12289,73 +12358,80 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) {
; SI-LABEL: bitcast_v6bf16_to_v6i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v0
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v6
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v1
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v5
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v4
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB52_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v8
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: .LBB52_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB52_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11
-; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v1
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v1
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v8
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v9
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
+; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v7
; SI-NEXT: v_alignbit_b32 v2, v3, v1, 16
-; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
-; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_alignbit_b32 v1, v4, v1, 16
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; SI-NEXT: v_alignbit_b32 v5, v1, v5, 16
+; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_alignbit_b32 v1, v5, v1, 16
+; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; SI-NEXT: v_alignbit_b32 v4, v1, v4, 16
; SI-NEXT: .LBB52_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v0, v0, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
; SI-NEXT: v_or_b32_e32 v1, v1, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -13021,60 +13097,69 @@ define <6 x bfloat> @bitcast_v6i16_to_v6bf16(<6 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v6i16_to_v6bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; %bb.2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB54_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: v_mul_f32_e32 v0, 1.0, v3
+; SI-NEXT: v_mul_f32_e32 v0, 1.0, v5
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v8
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -13579,46 +13664,48 @@ define <6 x half> @bitcast_v6i16_to_v6f16(<6 x i16> %a, i32 %b) {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v4
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v5
+; SI-NEXT: v_or_b32_e32 v6, v1, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v6, v1, v11
-; SI-NEXT: v_or_b32_e32 v3, v0, v10
+; SI-NEXT: v_alignbit_b32 v7, v6, v1, 16
+; SI-NEXT: v_or_b32_e32 v3, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_alignbit_b32 v7, v6, v10, 16
-; SI-NEXT: v_or_b32_e32 v8, v0, v9
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; SI-NEXT: v_or_b32_e32 v8, v0, v1
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; %bb.2: ; %Flow
+; SI-NEXT: .LBB58_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v9
+; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v11, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v9, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v7, v6, v3, 16
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v6
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 6a09b269867c9..84bfcfc844e70 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -746,42 +746,44 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: add_i32_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: s_nop 1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX8_DPP-NEXT: ; implicit-def: $vgpr0
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v3, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_add_rtn_u32 v0, v3, v0
+; GFX8_DPP-NEXT: ds_add_rtn_u32 v0, v0, v3
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB2_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_add_u32_e32 v0, vcc, s4, v0
@@ -791,41 +793,43 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: add_i32_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: s_nop 1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9_DPP-NEXT: ; implicit-def: $vgpr0
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s2
-; GFX9_DPP-NEXT: ds_add_rtn_u32 v0, v3, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v3, s2
+; GFX9_DPP-NEXT: ds_add_rtn_u32 v0, v0, v3
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB2_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_add_u32_e32 v0, s4, v0
@@ -859,7 +863,6 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -869,8 +872,9 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064_DPP-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1064_DPP-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB2_2:
@@ -901,7 +905,6 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
@@ -912,8 +915,9 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032_DPP-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1032_DPP-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB2_2:
@@ -962,9 +966,8 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -974,8 +977,9 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164_DPP-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1164_DPP-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB2_2:
@@ -1012,10 +1016,10 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1132_DPP-NEXT: s_mov_b32 s0, s2
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -1023,8 +1027,9 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1132_DPP-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1132_DPP-NEXT: ds_add_rtn_u32 v0, v0, v4
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB2_2:
@@ -1256,9 +1261,8 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
;
; GFX8_DPP-LABEL: add_i32_varying_nouse:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
@@ -1276,22 +1280,22 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: s_mov_b32 s0, s2
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, s0
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_add_u32 v2, v0
+; GFX8_DPP-NEXT: ds_add_u32 v0, v2
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB3_2:
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: add_i32_varying_nouse:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
@@ -1309,12 +1313,13 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: s_mov_b32 s0, s2
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX9_DPP-NEXT: ds_add_u32 v2, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, s0
+; GFX9_DPP-NEXT: ds_add_u32 v0, v2
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB3_2:
; GFX9_DPP-NEXT: s_endpgm
@@ -1335,13 +1340,13 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 0
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_add_i32 s0, s2, s3
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX1064_DPP-NEXT: ; %bb.1:
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_DPP-NEXT: ds_add_u32 v0, v3
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -1360,14 +1365,14 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v2, v1, 0, 0
; GFX1032_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v3, v1
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, v1
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: ds_add_u32 v0, v3
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1032_DPP-NEXT: ds_add_u32 v3, v0
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB3_2:
@@ -1396,16 +1401,16 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, v1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v3
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: ds_add_u32 v0, v3
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: ds_add_u32 v3, v0
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB3_2:
@@ -1428,14 +1433,15 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1132_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v1
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX1132_DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v3
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB3_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: ds_add_u32 v0, v3
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1132_DPP-NEXT: ds_add_u32 v3, v0
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB3_2:
@@ -2295,155 +2301,159 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: add_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_addc_u32_e32 v4, vcc, v2, v4, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX8_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX8_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_add_rtn_u64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_add_rtn_u64 v[6:7], v0, v[6:7]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB6_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v6
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v6
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, v2
; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s4
-; GFX8_DPP-NEXT: v_add_u32_e32 v5, vcc, s5, v5
+; GFX8_DPP-NEXT: v_add_u32_e32 v6, vcc, s5, v6
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
-; GFX8_DPP-NEXT: v_addc_u32_e32 v6, vcc, v0, v6, vcc
+; GFX8_DPP-NEXT: v_addc_u32_e32 v7, vcc, v0, v7, vcc
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX8_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: add_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v4, vcc, v2, v4, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX9_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_add_rtn_u64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s2
+; GFX9_DPP-NEXT: ds_add_rtn_u64 v[6:7], v0, v[6:7]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB6_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v6
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v6
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, v2
; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s4
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v5, vcc, s5, v5
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v6, vcc, s5, v6
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v6, vcc, v0, v6, vcc
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v7, vcc, v0, v7, vcc
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX9_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX9_DPP-NEXT: s_endpgm
;
; GFX1064_DPP-LABEL: add_i64_varying:
@@ -2458,7 +2468,6 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v3 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v2, v1
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v3, v4, vcc
; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -2493,58 +2502,59 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, s3
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v3
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v5, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v8, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v7, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s2, 16
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s3, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v9, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s9, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s8, 48
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s9, 48
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1064_DPP-NEXT: ; implicit-def: $vgpr9_vgpr10
+; GFX1064_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v10, s1
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v9, s0
-; GFX1064_DPP-NEXT: ds_add_rtn_u64 v[9:10], v0, v[9:10]
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v9, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s0
+; GFX1064_DPP-NEXT: ds_add_rtn_u64 v[8:9], v0, v[8:9]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB6_2:
; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1064_DPP-NEXT: v_mov_b32_e32 v11, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v12, v8
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
-; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v10
-; GFX1064_DPP-NEXT: v_add_co_u32 v9, vcc, s3, v11
-; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v10, vcc, s4, v12, vcc
+; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1064_DPP-NEXT: v_add_co_u32 v8, vcc, s3, v10
+; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v9, vcc, s4, v11, vcc
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064_DPP-NEXT: buffer_store_dwordx2 v[9:10], off, s[0:3], 0
+; GFX1064_DPP-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0
; GFX1064_DPP-NEXT: s_endpgm
;
; GFX1032_DPP-LABEL: add_i64_varying:
@@ -2559,7 +2569,6 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v3 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v2, v1
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v4, vcc_lo
; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -2584,46 +2593,47 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v6, v2, -1, -1
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v8, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v7, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v9, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
-; GFX1032_DPP-NEXT: v_writelane_b32 v8, s6, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v7, s3, 16
+; GFX1032_DPP-NEXT: v_writelane_b32 v7, s6, 16
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1032_DPP-NEXT: ; implicit-def: $vgpr9_vgpr10
+; GFX1032_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v10, s1
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v9, s0
-; GFX1032_DPP-NEXT: ds_add_rtn_u64 v[9:10], v0, v[9:10]
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v9, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s0
+; GFX1032_DPP-NEXT: ds_add_rtn_u64 v[8:9], v0, v[8:9]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB6_2:
; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1032_DPP-NEXT: v_mov_b32_e32 v11, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v12, v8
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
-; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v10
-; GFX1032_DPP-NEXT: v_add_co_u32 v9, vcc_lo, s3, v11
-; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, s4, v12, vcc_lo
+; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1032_DPP-NEXT: v_add_co_u32 v8, vcc_lo, s3, v10
+; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, s4, v11, vcc_lo
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032_DPP-NEXT: buffer_store_dwordx2 v[9:10], off, s[0:3], 0
+; GFX1032_DPP-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0
; GFX1032_DPP-NEXT: s_endpgm
;
; GFX1164_DPP-LABEL: add_i64_varying:
@@ -2635,102 +2645,103 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s2, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s8, 48
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
-; GFX1164_DPP-NEXT: ds_add_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, s0
+; GFX1164_DPP-NEXT: ds_add_rtn_u64 v[6:7], v0, v[6:7]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB6_2:
; GFX1164_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v6
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v10, v6
-; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v8
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_add_co_u32 v7, vcc, s3, v9
+; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_add_co_u32 v6, vcc, s3, v8
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v7, null, s4, v9, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
+; GFX1164_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
;
; GFX1132_DPP-LABEL: add_i64_varying:
@@ -2780,19 +2791,19 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v8, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v7, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB6_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, s1
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s0
; GFX1132_DPP-NEXT: ds_add_rtn_u64 v[8:9], v0, v[8:9]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -3058,50 +3069,51 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
;
; GFX8_DPP-LABEL: add_i64_varying_nouse:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v1, vcc, v3, v1
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v2, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
@@ -3109,59 +3121,61 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s0
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_add_u64 v5, v[6:7]
+; GFX8_DPP-NEXT: ds_add_u64 v0, v[6:7]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB7_2:
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: add_i64_varying_nouse:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v1, vcc, v3, v1
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v2, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
@@ -3169,8 +3183,9 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s0
-; GFX9_DPP-NEXT: ds_add_u64 v5, v[6:7]
+; GFX9_DPP-NEXT: ds_add_u64 v0, v[6:7]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB7_2:
; GFX9_DPP-NEXT: s_endpgm
@@ -3194,16 +3209,16 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_xmask:2 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v6
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v5, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, 0
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v2 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v4
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v3, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v2 row_xmask:8 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v6
-; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v5, vcc
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v2 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v5
+; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v6, vcc
; GFX1064_DPP-NEXT: v_permlanex16_b32 v3, v1, 0, 0
; GFX1064_DPP-NEXT: v_permlanex16_b32 v4, v2, 0, 0
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v3
@@ -3216,15 +3231,15 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1064_DPP-NEXT: v_readlane_b32 s4, v1, 32
; GFX1064_DPP-NEXT: v_readlane_b32 s5, v2, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_add_u32 s0, s3, s4
; GFX1064_DPP-NEXT: s_addc_u32 s1, s2, s5
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_add_u64 v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -3251,29 +3266,29 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_xmask:2 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v6
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, 0
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v2 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v4
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v3, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_xmask:8 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v6
-; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v2 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v5
+; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v6, vcc_lo
; GFX1032_DPP-NEXT: v_permlanex16_b32 v3, v1, 0, 0
; GFX1032_DPP-NEXT: v_permlanex16_b32 v4, v2, 0, 0
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v9, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, v1
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, v2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1032_DPP-NEXT: ; %bb.1:
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: ds_add_u64 v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
@@ -3329,15 +3344,15 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v4, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, v2
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, v3
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v7
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1164_DPP-NEXT: ; %bb.1:
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: ds_add_u64 v0, v[5:6]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
@@ -3380,14 +3395,14 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1132_DPP-NEXT: v_permlanex16_b32 v4, v1, 0, 0
; GFX1132_DPP-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v4, vcc_lo
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, v2
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v6, v3
+; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v3
; GFX1132_DPP-NEXT: s_mov_b32 s0, exec_lo
-; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v7
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1132_DPP-NEXT: ; %bb.1:
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1132_DPP-NEXT: ds_add_u64 v0, v[5:6]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -4137,42 +4152,44 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: sub_i32_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: s_nop 1
+; GFX8_DPP-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX8_DPP-NEXT: ; implicit-def: $vgpr0
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v3, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_sub_rtn_u32 v0, v3, v0
+; GFX8_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v3
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB10_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
@@ -4182,41 +4199,43 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: sub_i32_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_add_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: s_nop 1
+; GFX9_DPP-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9_DPP-NEXT: ; implicit-def: $vgpr0
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s2
-; GFX9_DPP-NEXT: ds_sub_rtn_u32 v0, v3, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v3, s2
+; GFX9_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v3
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB10_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_sub_u32_e32 v0, s4, v0
@@ -4250,7 +4269,6 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -4260,8 +4278,9 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064_DPP-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1064_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB10_2:
@@ -4292,7 +4311,6 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
@@ -4303,8 +4321,9 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032_DPP-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1032_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB10_2:
@@ -4353,9 +4372,8 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -4365,8 +4383,9 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164_DPP-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1164_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB10_2:
@@ -4403,10 +4422,10 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1132_DPP-NEXT: s_mov_b32 s0, s2
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -4414,8 +4433,9 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB10_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1132_DPP-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1132_DPP-NEXT: ds_sub_rtn_u32 v0, v0, v4
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB10_2:
@@ -4647,9 +4667,8 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
;
; GFX8_DPP-LABEL: sub_i32_varying_nouse:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
@@ -4667,22 +4686,22 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: s_mov_b32 s0, s2
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, s0
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_sub_u32 v2, v0
+; GFX8_DPP-NEXT: ds_sub_u32 v0, v2
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB11_2:
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: sub_i32_varying_nouse:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
@@ -4700,12 +4719,13 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: s_mov_b32 s0, s2
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX9_DPP-NEXT: ds_sub_u32 v2, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, s0
+; GFX9_DPP-NEXT: ds_sub_u32 v0, v2
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB11_2:
; GFX9_DPP-NEXT: s_endpgm
@@ -4726,13 +4746,13 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 0
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_add_i32 s0, s2, s3
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1064_DPP-NEXT: ; %bb.1:
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_DPP-NEXT: ds_sub_u32 v0, v3
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -4751,14 +4771,14 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v2, v1, 0, 0
; GFX1032_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v3, v1
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, v1
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: ds_sub_u32 v0, v3
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1032_DPP-NEXT: ds_sub_u32 v3, v0
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB11_2:
@@ -4787,16 +4807,16 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, v1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v3
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: ds_sub_u32 v0, v3
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: ds_sub_u32 v3, v0
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB11_2:
@@ -4819,14 +4839,15 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1132_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v1
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX1132_DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v3
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: ds_sub_u32 v0, v3
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1132_DPP-NEXT: ds_sub_u32 v3, v0
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB11_2:
@@ -5707,155 +5728,159 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: sub_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX8_DPP-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_addc_u32_e32 v4, vcc, v2, v4, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX8_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX8_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_sub_rtn_u64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_sub_rtn_u64 v[6:7], v0, v[6:7]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB14_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v6
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v6
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, v2
; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s4
-; GFX8_DPP-NEXT: v_sub_u32_e32 v5, vcc, s5, v5
+; GFX8_DPP-NEXT: v_sub_u32_e32 v6, vcc, s5, v6
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
-; GFX8_DPP-NEXT: v_subb_u32_e32 v6, vcc, v0, v6, vcc
+; GFX8_DPP-NEXT: v_subb_u32_e32 v7, vcc, v0, v7, vcc
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX8_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: sub_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v4, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_addc_co_u32_e32 v4, vcc, v2, v4, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX9_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_sub_rtn_u64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s2
+; GFX9_DPP-NEXT: ds_sub_rtn_u64 v[6:7], v0, v[6:7]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB14_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v6
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v6
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, v2
; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s4
-; GFX9_DPP-NEXT: v_sub_co_u32_e32 v5, vcc, s5, v5
+; GFX9_DPP-NEXT: v_sub_co_u32_e32 v6, vcc, s5, v6
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
-; GFX9_DPP-NEXT: v_subb_co_u32_e32 v6, vcc, v0, v6, vcc
+; GFX9_DPP-NEXT: v_subb_co_u32_e32 v7, vcc, v0, v7, vcc
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX9_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX9_DPP-NEXT: s_endpgm
;
; GFX1064_DPP-LABEL: sub_i64_varying:
@@ -5870,7 +5895,6 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX1064_DPP-NEXT: v_mov_b32_dpp v4, v3 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v2, v1
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v3, v4, vcc
; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -5905,58 +5929,59 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, s3
; GFX1064_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1064_DPP-NEXT: v_mov_b32_dpp v5, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064_DPP-NEXT: v_add_co_u32 v1, vcc, v1, v3
; GFX1064_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc, v2, v5, vcc
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1064_DPP-NEXT: v_mov_b32_dpp v8, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1064_DPP-NEXT: v_mov_b32_dpp v7, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1064_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s7, v1, 31
; GFX1064_DPP-NEXT: v_readlane_b32 s8, v1, 47
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s2, 16
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s3, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s2, 16
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1064_DPP-NEXT: v_readlane_b32 s2, v1, 63
; GFX1064_DPP-NEXT: v_readlane_b32 s9, v2, 47
; GFX1064_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s6, 32
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s7, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s6, 32
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v9, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX1064_DPP-NEXT: v_writelane_b32 v8, s9, 48
-; GFX1064_DPP-NEXT: v_writelane_b32 v7, s8, 48
+; GFX1064_DPP-NEXT: v_writelane_b32 v7, s9, 48
+; GFX1064_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1064_DPP-NEXT: ; implicit-def: $vgpr9_vgpr10
+; GFX1064_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v10, s1
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v9, s0
-; GFX1064_DPP-NEXT: ds_sub_rtn_u64 v[9:10], v0, v[9:10]
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v9, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s0
+; GFX1064_DPP-NEXT: ds_sub_rtn_u64 v[8:9], v0, v[8:9]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB14_2:
; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1064_DPP-NEXT: v_mov_b32_e32 v11, v7
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v12, v8
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
-; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v10
-; GFX1064_DPP-NEXT: v_sub_co_u32 v9, vcc, s3, v11
-; GFX1064_DPP-NEXT: v_sub_co_ci_u32_e32 v10, vcc, s4, v12, vcc
+; GFX1064_DPP-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1064_DPP-NEXT: v_sub_co_u32 v8, vcc, s3, v10
+; GFX1064_DPP-NEXT: v_sub_co_ci_u32_e32 v9, vcc, s4, v11, vcc
; GFX1064_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064_DPP-NEXT: buffer_store_dwordx2 v[9:10], off, s[0:3], 0
+; GFX1064_DPP-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0
; GFX1064_DPP-NEXT: s_endpgm
;
; GFX1032_DPP-LABEL: sub_i64_varying:
@@ -5971,7 +5996,6 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v3 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v2, v1
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v4, vcc_lo
; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -5996,46 +6020,47 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_permlanex16_b32 v6, v2, -1, -1
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032_DPP-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX1032_DPP-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX1032_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1032_DPP-NEXT: v_readlane_b32 s0, v1, 31
; GFX1032_DPP-NEXT: v_readlane_b32 s1, v2, 31
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX1032_DPP-NEXT: v_mov_b32_dpp v8, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1032_DPP-NEXT: v_mov_b32_dpp v7, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v9, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
-; GFX1032_DPP-NEXT: v_writelane_b32 v8, s6, 16
-; GFX1032_DPP-NEXT: v_writelane_b32 v7, s3, 16
+; GFX1032_DPP-NEXT: v_writelane_b32 v7, s6, 16
+; GFX1032_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1032_DPP-NEXT: ; implicit-def: $vgpr9_vgpr10
+; GFX1032_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v10, s1
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v9, s0
-; GFX1032_DPP-NEXT: ds_sub_rtn_u64 v[9:10], v0, v[9:10]
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v9, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s0
+; GFX1032_DPP-NEXT: ds_sub_rtn_u64 v[8:9], v0, v[8:9]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB14_2:
; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1032_DPP-NEXT: v_mov_b32_e32 v11, v7
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v12, v8
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
-; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v10
-; GFX1032_DPP-NEXT: v_sub_co_u32 v9, vcc_lo, s3, v11
-; GFX1032_DPP-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, s4, v12, vcc_lo
+; GFX1032_DPP-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1032_DPP-NEXT: v_sub_co_u32 v8, vcc_lo, s3, v10
+; GFX1032_DPP-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, s4, v11, vcc_lo
; GFX1032_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032_DPP-NEXT: buffer_store_dwordx2 v[9:10], off, s[0:3], 0
+; GFX1032_DPP-NEXT: buffer_store_dwordx2 v[8:9], off, s[0:3], 0
; GFX1032_DPP-NEXT: s_endpgm
;
; GFX1164_DPP-LABEL: sub_i64_varying:
@@ -6047,102 +6072,103 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
-; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v2, 31
; GFX1164_DPP-NEXT: v_readlane_b32 s7, v1, 31
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s2, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1164_DPP-NEXT: v_readlane_b32 s8, v2, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s9, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s6, 32
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s7, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s6, 32
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
-; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
+; GFX1164_DPP-NEXT: v_writelane_b32 v4, s8, 48
+; GFX1164_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
-; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
-; GFX1164_DPP-NEXT: ds_sub_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, s0
+; GFX1164_DPP-NEXT: ds_sub_rtn_u64 v[6:7], v0, v[6:7]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB14_2:
; GFX1164_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1164_DPP-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v6
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v5
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v10, v6
-; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v8
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_sub_co_u32 v7, vcc, s3, v9
+; GFX1164_DPP-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_sub_co_u32 v6, vcc, s3, v8
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1164_DPP-NEXT: v_sub_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1164_DPP-NEXT: v_sub_co_ci_u32_e64 v7, null, s4, v9, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
+; GFX1164_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], 0
; GFX1164_DPP-NEXT: s_endpgm
;
; GFX1132_DPP-LABEL: sub_i64_varying:
@@ -6192,19 +6218,19 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v8, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v7, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB14_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, s1
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s0
; GFX1132_DPP-NEXT: ds_sub_rtn_u64 v[8:9], v0, v[8:9]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -7171,7 +7197,6 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-LABEL: and_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, -1, 0, s[0:1]
@@ -7205,9 +7230,10 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_and_rtn_b64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_and_rtn_b64 v[5:6], v0, v[5:6]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB16_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -7227,7 +7253,6 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-LABEL: and_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, -1, 0, s[0:1]
@@ -7261,8 +7286,9 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_and_rtn_b64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: ds_and_rtn_b64 v[5:6], v0, v[5:6]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB16_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -7322,20 +7348,20 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -7382,19 +7408,19 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -7472,20 +7498,20 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -7540,19 +7566,19 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB16_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -7876,42 +7902,44 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: or_i32_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: s_nop 1
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX8_DPP-NEXT: ; implicit-def: $vgpr0
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v3, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_or_rtn_b32 v0, v3, v0
+; GFX8_DPP-NEXT: ds_or_rtn_b32 v0, v0, v3
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB17_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_or_b32_e32 v0, s4, v0
@@ -7921,41 +7949,43 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: or_i32_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: s_nop 1
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9_DPP-NEXT: ; implicit-def: $vgpr0
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s2
-; GFX9_DPP-NEXT: ds_or_rtn_b32 v0, v3, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v3, s2
+; GFX9_DPP-NEXT: ds_or_rtn_b32 v0, v0, v3
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB17_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_or_b32_e32 v0, s4, v0
@@ -7989,7 +8019,6 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -7999,8 +8028,9 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064_DPP-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1064_DPP-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB17_2:
@@ -8031,7 +8061,6 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
@@ -8042,8 +8071,9 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032_DPP-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1032_DPP-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB17_2:
@@ -8092,9 +8122,8 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -8104,8 +8133,9 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164_DPP-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1164_DPP-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB17_2:
@@ -8142,10 +8172,10 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1132_DPP-NEXT: s_mov_b32 s0, s2
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -8153,8 +8183,9 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB17_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1132_DPP-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1132_DPP-NEXT: ds_or_rtn_b32 v0, v0, v4
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB17_2:
@@ -8517,34 +8548,36 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: or_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: s_nop 0
; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: s_nop 0
; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_or_b32_dpp v4, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_DPP-NEXT: v_or_b32_dpp v4, v4, v4 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_or_b32_dpp v4, v4, v4 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GFX8_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
@@ -8552,17 +8585,18 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_or_rtn_b64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_or_rtn_b64 v[5:6], v0, v[5:6]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB18_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v6
; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v2
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_or_b32_e32 v6, s4, v6
@@ -8573,34 +8607,36 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: or_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: s_nop 0
; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: s_nop 0
; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_or_b32_dpp v4, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_DPP-NEXT: v_or_b32_dpp v4, v4, v4 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_or_b32_dpp v4, v4, v4 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_or_b32_dpp v3, v3, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GFX9_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
@@ -8608,16 +8644,17 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_or_rtn_b64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: ds_or_rtn_b64 v[5:6], v0, v[5:6]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB18_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v6
; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v2
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_or_b32_e32 v6, s4, v6
@@ -8669,20 +8706,20 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -8729,19 +8766,19 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -8819,20 +8856,20 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -8887,19 +8924,19 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB18_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -9223,42 +9260,44 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: xor_i32_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: s_nop 1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX8_DPP-NEXT: ; implicit-def: $vgpr0
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v3, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_xor_rtn_b32 v0, v3, v0
+; GFX8_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v3
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB19_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_xor_b32_e32 v0, s4, v0
@@ -9268,41 +9307,43 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: xor_i32_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: s_nop 1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9_DPP-NEXT: ; implicit-def: $vgpr0
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s2
-; GFX9_DPP-NEXT: ds_xor_rtn_b32 v0, v3, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v3, s2
+; GFX9_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v3
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB19_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_xor_b32_e32 v0, s4, v0
@@ -9336,7 +9377,6 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -9346,8 +9386,9 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064_DPP-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1064_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB19_2:
@@ -9378,7 +9419,6 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
@@ -9389,8 +9429,9 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032_DPP-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1032_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB19_2:
@@ -9439,9 +9480,8 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -9451,8 +9491,9 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164_DPP-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1164_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB19_2:
@@ -9489,10 +9530,10 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1132_DPP-NEXT: s_mov_b32 s0, s2
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -9500,8 +9541,9 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB19_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1132_DPP-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1132_DPP-NEXT: ds_xor_rtn_b32 v0, v0, v4
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB19_2:
@@ -9864,34 +9906,36 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: xor_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: s_nop 0
; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: s_nop 0
; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_xor_b32_dpp v4, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_DPP-NEXT: v_xor_b32_dpp v4, v4, v4 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_xor_b32_dpp v4, v4, v4 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GFX8_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
@@ -9899,17 +9943,18 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_xor_rtn_b64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_xor_rtn_b64 v[5:6], v0, v[5:6]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB20_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v6
; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v2
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_xor_b32_e32 v6, s4, v6
@@ -9920,34 +9965,36 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: xor_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: s_nop 0
; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: s_nop 0
; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_xor_b32_dpp v4, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_DPP-NEXT: v_xor_b32_dpp v4, v4, v4 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v1, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
-; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_xor_b32_dpp v4, v4, v4 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_xor_b32_dpp v3, v3, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v4, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v3, 63
+; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GFX9_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
@@ -9955,16 +10002,17 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_xor_rtn_b64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: ds_xor_rtn_b64 v[5:6], v0, v[5:6]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB20_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v6
; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v5
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v4
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v2
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_xor_b32_e32 v6, s4, v6
@@ -10016,20 +10064,20 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -10076,19 +10124,19 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -10166,20 +10214,20 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v6, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -10234,19 +10282,19 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v2, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
; GFX1132_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v6, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB20_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -11497,8 +11545,10 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: max_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v9, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v7
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_bfrev_b32_e32 v2, 1
@@ -11506,7 +11556,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX8_DPP-NEXT: v_bfrev_b32_e32 v6, 1
; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_nop 0
; GFX8_DPP-NEXT: v_mov_b32_dpp v6, v4 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[3:4], v[5:6]
@@ -11563,9 +11613,10 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v8, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_max_rtn_i64 v[7:8], v9, v[7:8]
+; GFX8_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB23_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -11587,8 +11638,10 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: max_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v9, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v7
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_bfrev_b32_e32 v2, 1
@@ -11596,7 +11649,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
; GFX9_DPP-NEXT: v_bfrev_b32_e32 v6, 1
; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_nop 0
; GFX9_DPP-NEXT: v_mov_b32_dpp v6, v4 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[3:4], v[5:6]
@@ -11653,8 +11706,9 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v8, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s2
-; GFX9_DPP-NEXT: ds_max_rtn_i64 v[7:8], v9, v[7:8]
+; GFX9_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB23_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -11747,20 +11801,20 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -11833,19 +11887,19 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -11963,21 +12017,20 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -11992,6 +12045,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[7:8]
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -12056,19 +12110,19 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB23_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -13321,7 +13375,6 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-LABEL: min_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v9, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v7
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_bfrev_b32_e32 v2, -2
@@ -13386,9 +13439,10 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v8, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_min_rtn_i64 v[7:8], v9, v[7:8]
+; GFX8_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB26_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -13411,7 +13465,6 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-LABEL: min_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v9, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v7
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_bfrev_b32_e32 v2, -2
@@ -13476,8 +13529,9 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v8, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s2
-; GFX9_DPP-NEXT: ds_min_rtn_i64 v[7:8], v9, v[7:8]
+; GFX9_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB26_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -13570,20 +13624,20 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -13656,19 +13710,19 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -13786,21 +13840,20 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -13815,6 +13868,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[7:8]
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -13879,19 +13933,19 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB26_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -14216,42 +14270,44 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: umax_i32_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX8_DPP-NEXT: s_nop 1
-; GFX8_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX8_DPP-NEXT: s_nop 1
+; GFX8_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX8_DPP-NEXT: s_nop 0
-; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX8_DPP-NEXT: ; implicit-def: $vgpr0
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v3, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_max_rtn_u32 v0, v3, v0
+; GFX8_DPP-NEXT: ds_max_rtn_u32 v0, v0, v3
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB27_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
; GFX8_DPP-NEXT: v_max_u32_e32 v0, s4, v0
@@ -14261,41 +14317,43 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
;
; GFX9_DPP-LABEL: umax_i32_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v4
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
-; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
-; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX9_DPP-NEXT: s_nop 1
-; GFX9_DPP-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
+; GFX9_DPP-NEXT: s_nop 1
+; GFX9_DPP-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v2, 63
; GFX9_DPP-NEXT: s_nop 0
-; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9_DPP-NEXT: ; implicit-def: $vgpr0
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s2
-; GFX9_DPP-NEXT: ds_max_rtn_u32 v0, v3, v0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v3, s2
+; GFX9_DPP-NEXT: ds_max_rtn_u32 v0, v0, v3
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB27_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, v1
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
; GFX9_DPP-NEXT: v_max_u32_e32 v0, s4, v0
@@ -14329,7 +14387,6 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1064_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -14339,8 +14396,9 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX1064_DPP-NEXT: ; %bb.1:
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064_DPP-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1064_DPP-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB27_2:
@@ -14371,7 +14429,6 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s0
@@ -14382,8 +14439,9 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX1032_DPP-NEXT: ; %bb.1:
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032_DPP-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1032_DPP-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB27_2:
@@ -14432,9 +14490,8 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s2, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -14444,8 +14501,9 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX1164_DPP-NEXT: ; %bb.1:
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164_DPP-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s6
+; GFX1164_DPP-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: .LBB27_2:
@@ -14482,10 +14540,10 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s0, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v3, s1, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s0
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1132_DPP-NEXT: s_mov_b32 s0, s2
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
@@ -14493,8 +14551,9 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_and_saveexec_b32 s1, vcc_lo
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB27_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, s0
-; GFX1132_DPP-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v4, s0
+; GFX1132_DPP-NEXT: ds_max_rtn_u32 v0, v0, v4
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB27_2:
@@ -15132,183 +15191,187 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
;
; GFX8_DPP-LABEL: umax_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
-; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
-; GFX8_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, 0, 0, s[0:1]
+; GFX8_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX8_DPP-NEXT: s_nop 0
+; GFX8_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX8_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX8_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX8_DPP-NEXT: v_mov_b32_dpp v4, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX8_DPP-NEXT: v_mov_b32_dpp v3, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_DPP-NEXT: v_readlane_b32 s3, v3, 63
+; GFX8_DPP-NEXT: v_readlane_b32 s2, v4, 63
+; GFX8_DPP-NEXT: v_mov_b32_dpp v2, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX8_DPP-NEXT: v_mov_b32_dpp v1, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX8_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX8_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX8_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX8_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, s2
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_max_rtn_u64 v[5:6], v7, v[5:6]
+; GFX8_DPP-NEXT: ds_max_rtn_u64 v[6:7], v0, v[6:7]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB29_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v6
-; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v5
-; GFX8_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v4
-; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[5:6]
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s5, v7
+; GFX8_DPP-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX8_DPP-NEXT: v_mov_b32_e32 v7, v2
+; GFX8_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[6:7]
; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s5
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s4
; GFX8_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s2, -1
-; GFX8_DPP-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8_DPP-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX8_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX8_DPP-NEXT: s_endpgm
;
; GFX9_DPP-LABEL: umax_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
-; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v5, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, 0
-; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v5, exec_hi, v5
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
-; GFX9_DPP-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v1, 0
+; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
+; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
+; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, 0, 0, s[0:1]
+; GFX9_DPP-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:8 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:15 row_mask:0xa bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:15 row_mask:0xa bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX9_DPP-NEXT: s_nop 0
+; GFX9_DPP-NEXT: v_mov_b32_dpp v5, v3 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 row_bcast:31 row_mask:0xc bank_mask:0xf
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v3, 0
-; GFX9_DPP-NEXT: v_readlane_b32 s3, v2, 63
-; GFX9_DPP-NEXT: v_readlane_b32 s2, v1, 63
-; GFX9_DPP-NEXT: v_mov_b32_dpp v4, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
-; GFX9_DPP-NEXT: v_mov_b32_dpp v3, v1 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9_DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_DPP-NEXT: v_readlane_b32 s3, v3, 63
+; GFX9_DPP-NEXT: v_readlane_b32 s2, v4, 63
+; GFX9_DPP-NEXT: v_mov_b32_dpp v2, v3 wave_shr:1 row_mask:0xf bank_mask:0xf
+; GFX9_DPP-NEXT: v_mov_b32_dpp v1, v4 wave_shr:1 row_mask:0xf bank_mask:0xf
; GFX9_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GFX9_DPP-NEXT: ; implicit-def: $vgpr5_vgpr6
+; GFX9_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9_DPP-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, s2
-; GFX9_DPP-NEXT: ds_max_rtn_u64 v[5:6], v7, v[5:6]
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s2
+; GFX9_DPP-NEXT: ds_max_rtn_u64 v[6:7], v0, v[6:7]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB29_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v6
-; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v5
-; GFX9_DPP-NEXT: v_mov_b32_e32 v5, v3
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v4
-; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[5:6]
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s5, v7
+; GFX9_DPP-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, v1
+; GFX9_DPP-NEXT: v_mov_b32_e32 v7, v2
+; GFX9_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[6:7]
; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s5
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s4
; GFX9_DPP-NEXT: s_mov_b32 s3, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s2, -1
-; GFX9_DPP-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX9_DPP-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9_DPP-NEXT: buffer_store_dwordx2 v[5:6], off, s[0:3], 0
+; GFX9_DPP-NEXT: buffer_store_dwordx2 v[6:7], off, s[0:3], 0
; GFX9_DPP-NEXT: s_endpgm
;
; GFX1064_DPP-LABEL: umax_i64_varying:
@@ -15384,20 +15447,20 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -15470,19 +15533,19 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -15600,21 +15663,20 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -15629,6 +15691,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[7:8]
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -15687,19 +15750,19 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB29_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
@@ -16942,7 +17005,6 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-LABEL: umin_i64_varying:
; GFX8_DPP: ; %bb.0: ; %entry
; GFX8_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX8_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX8_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
; GFX8_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX8_DPP-NEXT: v_cndmask_b32_e64 v3, -1, 0, s[0:1]
@@ -17007,9 +17069,10 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX8_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX8_DPP-NEXT: ; %bb.1:
; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s2
; GFX8_DPP-NEXT: s_mov_b32 m0, -1
-; GFX8_DPP-NEXT: ds_min_rtn_u64 v[6:7], v8, v[6:7]
+; GFX8_DPP-NEXT: ds_min_rtn_u64 v[6:7], v0, v[6:7]
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: .LBB32_2:
; GFX8_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -17032,7 +17095,6 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-LABEL: umin_i64_varying:
; GFX9_DPP: ; %bb.0: ; %entry
; GFX9_DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX9_DPP-NEXT: v_mov_b32_e32 v8, 0
; GFX9_DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v6
; GFX9_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9_DPP-NEXT: v_cndmask_b32_e64 v3, -1, 0, s[0:1]
@@ -17097,8 +17159,9 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX9_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX9_DPP-NEXT: ; %bb.1:
; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s2
-; GFX9_DPP-NEXT: ds_min_rtn_u64 v[6:7], v8, v[6:7]
+; GFX9_DPP-NEXT: ds_min_rtn_u64 v[6:7], v0, v[6:7]
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: .LBB32_2:
; GFX9_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
@@ -17191,20 +17254,20 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s6, 32
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1064_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1064_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1064_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1064_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1064_DPP-NEXT: s_mov_b32 s2, -1
; GFX1064_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1064_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX1064_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX1064_DPP-NEXT: ; %bb.1:
; GFX1064_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1064_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1064_DPP-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -17277,19 +17340,19 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1032_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1032_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1032_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1032_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1032_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1032_DPP-NEXT: s_mov_b32 s2, -1
; GFX1032_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1032_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
; GFX1032_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX1032_DPP-NEXT: ; %bb.1:
; GFX1032_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1032_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1032_DPP-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -17407,21 +17470,20 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s7, 32
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164_DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1164_DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
; GFX1164_DPP-NEXT: v_writelane_b32 v5, s8, 48
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
-; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1164_DPP-NEXT: s_mov_b64 s[6:7], exec
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1164_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1164_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX1164_DPP-NEXT: ; %bb.1:
; GFX1164_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX1164_DPP-NEXT: v_mov_b32_e32 v7, s0
; GFX1164_DPP-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -17436,6 +17498,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[7:8]
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
; GFX1164_DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -17494,19 +17557,19 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1132_DPP-NEXT: v_readlane_b32 s6, v1, 15
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v0, 0
+; GFX1132_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1132_DPP-NEXT: s_or_saveexec_b32 s2, -1
; GFX1132_DPP-NEXT: v_writelane_b32 v5, s3, 16
; GFX1132_DPP-NEXT: v_writelane_b32 v4, s6, 16
; GFX1132_DPP-NEXT: s_mov_b32 exec_lo, s2
-; GFX1132_DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
; GFX1132_DPP-NEXT: s_mov_b32 s2, -1
+; GFX1132_DPP-NEXT: s_mov_b32 s3, exec_lo
; GFX1132_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
-; GFX1132_DPP-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1132_DPP-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX1132_DPP-NEXT: s_cbranch_execz .LBB32_2
; GFX1132_DPP-NEXT: ; %bb.1:
-; GFX1132_DPP-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1132_DPP-NEXT: v_mov_b32_e32 v8, s1
+; GFX1132_DPP-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s0
; GFX1132_DPP-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl0_inv
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
index e784c33918f9b..4b8f10e21bb27 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
@@ -10,9 +10,7 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[0:1] offset:4
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, -4
@@ -29,7 +27,7 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -37,19 +35,20 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, v1, s3, v0
-; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v0, v4, v[0:1], s[0:1] glc
+; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
; GFX11-TRUE16-NEXT: buffer_gl0_inv
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index bc88acf521bd1..24a8415815217 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -25,15 +25,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: S_BITCMP1_B32 renamable $sgpr20, 8, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr30_sgpr31 = S_CSELECT_B64 -1, 0, implicit killed $scc
; GFX90A-NEXT: renamable $sgpr30_sgpr31 = S_XOR_B64 killed renamable $sgpr30_sgpr31, -1, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $vgpr5 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr4 = DS_READ_B32_gfx9 renamable $vgpr5, 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(3) null`, align 8, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2 = DS_READ_B32_gfx9 renamable $vgpr3, 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(3) null`, align 8, addrspace 3)
; GFX90A-NEXT: renamable $sgpr40_sgpr41 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, renamable $sgpr28_sgpr29, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCZ %bb.2, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1.bb103:
; GFX90A-NEXT: successors: %bb.58(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, renamable $sgpr30_sgpr31, implicit-def dead $scc
@@ -41,10 +41,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: successors: %bb.3(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56, $sgpr57, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr4, $vgpr5
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56, $sgpr57, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr2, $vgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF implicit-def $vgpr16
- ; GFX90A-NEXT: renamable $vgpr3 = IMPLICIT_DEF implicit-def $vgpr2
+ ; GFX90A-NEXT: renamable $vgpr15 = IMPLICIT_DEF implicit-def $vgpr14
+ ; GFX90A-NEXT: renamable $vgpr25 = IMPLICIT_DEF implicit-def $vgpr24
; GFX90A-NEXT: renamable $vgpr27 = IMPLICIT_DEF implicit-def $vgpr26
; GFX90A-NEXT: renamable $vgpr29 = IMPLICIT_DEF implicit-def $vgpr28
; GFX90A-NEXT: renamable $vgpr33 = IMPLICIT_DEF implicit-def $vgpr32
@@ -52,22 +52,21 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.Flow17:
; GFX90A-NEXT: successors: %bb.4(0x40000000), %bb.57(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr16_vgpr17:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr6 = V_AND_B32_e32 1023, $vgpr31, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr4 = V_AND_B32_e32 1023, $vgpr31, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCZ %bb.57, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.4.bb15:
; GFX90A-NEXT: successors: %bb.35(0x40000000), %bb.5(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr0_vgpr1 = nsw V_LSHLREV_B64_e64 2, $vgpr4_vgpr5, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = COPY renamable $sgpr25, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr0_vgpr1 = nsw V_LSHLREV_B64_e64 2, $vgpr2_vgpr3, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr5 = COPY renamable $sgpr25, implicit $exec
; GFX90A-NEXT: renamable $vgpr46, renamable $vcc = V_ADD_CO_U32_e64 $sgpr24, $vgpr0, 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr47, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr2, killed $vgpr1, killed $vcc, 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr47, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr5, killed $vgpr1, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, $vgpr4, implicit $exec
; GFX90A-NEXT: renamable $vgpr40, renamable $vcc = V_ADD_CO_U32_e64 $vgpr46, killed $vgpr0, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr41, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr47, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, renamable $sgpr30_sgpr31, implicit-def dead $scc
@@ -75,7 +74,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.5:
; GFX90A-NEXT: successors: %bb.6(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
@@ -88,9 +87,9 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
@@ -98,32 +97,33 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr44_vgpr45 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr42_vgpr43 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.6.Flow20:
; GFX90A-NEXT: successors: %bb.7(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: renamable $vgpr24 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr26 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr28 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr33 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr17 = COPY killed renamable $sgpr18, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr15 = COPY killed renamable $sgpr18, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr25 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr27 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr29 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.7.Flow19:
; GFX90A-NEXT: successors: %bb.62(0x40000000), %bb.8(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_MOV_B64 0
; GFX90A-NEXT: $sgpr18_sgpr19 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -131,7 +131,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.8.Flow32:
; GFX90A-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr40_sgpr41, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -140,15 +140,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.9.bb89:
; GFX90A-NEXT: successors: %bb.10(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.10.Flow33:
; GFX90A-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr46_sgpr47, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -157,15 +157,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.11.bb84:
; GFX90A-NEXT: successors: %bb.12(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.12.Flow34:
; GFX90A-NEXT: successors: %bb.13(0x40000000), %bb.14(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr44_sgpr45, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -174,10 +174,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.13.bb79:
; GFX90A-NEXT: successors: %bb.14(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.14.Flow35:
@@ -360,7 +360,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.35.bb20:
; GFX90A-NEXT: successors: %bb.37(0x40000000), %bb.36(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_SBYTE renamable $vgpr40_vgpr41, 1024, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i23)
; GFX90A-NEXT: renamable $vgpr42 = V_ADD_CO_U32_e32 1024, $vgpr40, implicit-def $vcc, implicit $exec
@@ -377,37 +377,37 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr43, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_LT_I16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr44_vgpr45 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr24_sgpr25 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.37, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.36.Flow21:
; GFX90A-NEXT: successors: %bb.6(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def $scc
; GFX90A-NEXT: S_BRANCH %bb.6
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.37.bb27:
; GFX90A-NEXT: successors: %bb.39(0x40000000), %bb.38(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_UBYTE renamable $vgpr40_vgpr41, 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i30)
; GFX90A-NEXT: renamable $vgpr44 = V_ADD_CO_U32_e32 2048, $vgpr40, implicit-def $vcc, implicit $exec
@@ -417,29 +417,29 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr45, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr38_sgpr39 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.39, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.38.Flow22:
; GFX90A-NEXT: successors: %bb.36(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -460,7 +460,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.39.bb34:
; GFX90A-NEXT: successors: %bb.41(0x40000000), %bb.40(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_UBYTE renamable $vgpr40_vgpr41, 3072, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i37)
; GFX90A-NEXT: renamable $vgpr56 = V_ADD_CO_U32_e32 3072, $vgpr40, implicit-def $vcc, implicit $exec
@@ -470,28 +470,28 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr57, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr40_sgpr41 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.41, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.40.Flow23:
; GFX90A-NEXT: successors: %bb.38(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr68_sgpr69, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr68_sgpr69, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr40_sgpr41, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -511,7 +511,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.41.bb41:
; GFX90A-NEXT: successors: %bb.46(0x40000000), %bb.42(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr66_sgpr67, $sgpr68_sgpr69
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr66_sgpr67, $sgpr68_sgpr69
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr58 = V_ADD_CO_U32_e32 4096, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $vgpr1, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, $vgpr41, $vcc, 0, implicit $exec
@@ -521,27 +521,27 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
; GFX90A-NEXT: renamable $vgpr59, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr42_sgpr43 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.46, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.42.Flow24:
; GFX90A-NEXT: successors: %bb.40(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr42_sgpr43, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -560,7 +560,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.43.bb55:
; GFX90A-NEXT: successors: %bb.48(0x40000000), %bb.44(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_BITCMP1_B32 renamable $sgpr20, 16, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_CSELECT_B64 -1, 0, implicit killed $scc
@@ -572,27 +572,27 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.44:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr57, $vgpr62, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr61, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr4, $vgpr5, $vgpr6, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr58, $vgpr60, $vgpr63, $vgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr57, $vgpr62, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr61, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr3, $vgpr4, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr58, $vgpr60, $vgpr63, $vgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.45.Flow26:
; GFX90A-NEXT: successors: %bb.47(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_XOR_B64 $exec, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
@@ -608,7 +608,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.46.bb48:
; GFX90A-NEXT: successors: %bb.43(0x40000000), %bb.47(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr66_sgpr67, $sgpr58_sgpr59, $sgpr68_sgpr69, $sgpr64_sgpr65, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr66_sgpr67, $sgpr58_sgpr59, $sgpr68_sgpr69, $sgpr64_sgpr65, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr60 = V_ADD_CO_U32_e32 5120, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr18_sgpr19 = COPY $vcc
@@ -620,26 +620,26 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr70_sgpr71 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr61, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr18_sgpr19, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr44_sgpr45 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.43, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.47.Flow25:
; GFX90A-NEXT: successors: %bb.42(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $sgpr70_sgpr71, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $sgpr70_sgpr71, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr44_sgpr45, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -657,138 +657,139 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.48.bb63:
; GFX90A-NEXT: successors: %bb.50(0x40000000), %bb.49(0x40000000)
- ; GFX90A-NEXT: liveins: $vcc, $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $vcc, $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.50, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.49:
; GFX90A-NEXT: successors: %bb.44(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 -1
; GFX90A-NEXT: S_BRANCH %bb.44
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.50.bb68:
; GFX90A-NEXT: successors: %bb.54(0x40000000), %bb.51(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 3, $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 3, $vgpr4, implicit $exec
; GFX90A-NEXT: renamable $vgpr1 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.54, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.51:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: S_BRANCH %bb.45
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.52.bb80:
; GFX90A-NEXT: successors: %bb.59(0x40000000), %bb.53(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: dead renamable $sgpr15 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def $scc
- ; GFX90A-NEXT: renamable $vgpr10 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr11, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr8 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr9, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: S_CBRANCH_SCC0 %bb.59, implicit killed $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.53:
; GFX90A-NEXT: successors: %bb.61(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr66_sgpr67 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: S_BRANCH %bb.61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.54.bb73:
; GFX90A-NEXT: successors: %bb.52(0x40000000), %bb.55(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr3 = FLAT_LOAD_UBYTE renamable $vgpr0_vgpr1, 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i76)
- ; GFX90A-NEXT: renamable $vgpr8 = V_ADD_CO_U32_e32 2048, $vgpr0, implicit-def $vcc, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr5 = FLAT_LOAD_UBYTE renamable $vgpr0_vgpr1, 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i76)
+ ; GFX90A-NEXT: renamable $vgpr6 = V_ADD_CO_U32_e32 2048, $vgpr0, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr58_sgpr59 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr9, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
- ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr3, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr7, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr5, implicit $exec
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr62_sgpr63 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.52, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.55.Flow29:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr62_sgpr63, implicit-def $scc
; GFX90A-NEXT: S_BRANCH %bb.45
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.56.bb90:
; GFX90A-NEXT: successors: %bb.60(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr30 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $sgpr64_sgpr65, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr7 = COPY renamable $sgpr21, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr24_vgpr25 = DS_READ_B64_gfx9 killed renamable $vgpr7, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr22_vgpr23 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr3 = COPY renamable $sgpr22, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr20_vgpr21 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr5 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = COPY renamable $sgpr21, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr22_vgpr23 = DS_READ_B64_gfx9 killed renamable $vgpr12, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr20_vgpr21 = DS_READ_B64_gfx9 killed renamable $vgpr5, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr5 = COPY renamable $sgpr22, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr18_vgpr19 = DS_READ_B64_gfx9 killed renamable $vgpr5, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_LSHR_B64 killed renamable $sgpr56_sgpr57, 1, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $vgpr18_vgpr19 = V_LSHRREV_B64_e64 1, $vgpr24_vgpr25, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr7 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14_vgpr15 = V_LSHRREV_B64_e64 1, $vgpr22_vgpr23, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr16_vgpr17 = V_LSHRREV_B64_e64 1, $vgpr22_vgpr23, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr5 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = V_LSHRREV_B64_e64 1, $vgpr20_vgpr21, implicit $exec
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $vgpr16 = COPY renamable $vgpr22, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr14 = COPY renamable $vgpr20, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.60
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.57:
; GFX90A-NEXT: successors: %bb.7(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr24 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr20 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr21 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr30 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr5 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr22 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr18 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr19 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr30 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr20 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr16 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 0
@@ -799,9 +800,9 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
@@ -811,22 +812,21 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr42_vgpr43 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr40_vgpr41 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr46_vgpr47 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = COPY renamable $vgpr5, implicit $exec
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 0
; GFX90A-NEXT: S_BRANCH %bb.7
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.58.bb105:
; GFX90A-NEXT: successors: %bb.3(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr28_vgpr29 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr23, implicit $exec
; GFX90A-NEXT: renamable $vgpr26_vgpr27 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.419, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr21, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2_vgpr3 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr24_vgpr25 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY killed renamable $sgpr15, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr16_vgpr17 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.420, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr14_vgpr15 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.420, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr22, implicit $exec
; GFX90A-NEXT: renamable $vgpr32_vgpr33 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
; GFX90A-NEXT: renamable $sgpr36_sgpr37 = S_MOV_B64 -1
@@ -834,36 +834,36 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.59.bb85:
; GFX90A-NEXT: successors: %bb.56(0x40000000), %bb.60(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr12 = V_OR_B32_e32 1, $vgpr10, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr13 = COPY renamable $vgpr11, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = FLAT_LOAD_UBYTE renamable $vgpr12_vgpr13, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i86)
+ ; GFX90A-NEXT: renamable $vgpr10 = V_OR_B32_e32 1, $vgpr8, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr11 = COPY renamable $vgpr9, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr5 = FLAT_LOAD_UBYTE renamable $vgpr10_vgpr11, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i86)
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 -1
- ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr3, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr5, implicit $exec
; GFX90A-NEXT: renamable $sgpr66_sgpr67 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr5 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr54_sgpr55 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.56, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.60.Flow31:
; GFX90A-NEXT: successors: %bb.61(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr54_sgpr55, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.61.Flow30:
; GFX90A-NEXT: successors: %bb.55(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr58_sgpr59 = S_XOR_B64 $exec, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
@@ -875,7 +875,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.62.bb140:
; GFX90A-NEXT: successors: %bb.68(0x40000000), %bb.63(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr24_sgpr25 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
@@ -883,122 +883,122 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.63.Flow13:
; GFX90A-NEXT: successors: %bb.64(0x40000000), %bb.66(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.66, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.64.bb159:
; GFX90A-NEXT: successors: %bb.67(0x40000000), %bb.65(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vcc = V_CMP_NE_U32_e64 0, killed $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_NE_U32_e64 0, killed $vgpr4, implicit $exec
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.67, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.65.Flow10:
; GFX90A-NEXT: successors: %bb.66(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $sgpr12_sgpr13 = S_ANDN2_SAVEEXEC_B64 $sgpr12_sgpr13, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.66.Flow14:
; GFX90A-NEXT: successors: %bb.8(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = COPY $exec
; GFX90A-NEXT: S_BRANCH %bb.8
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.67.bb161:
; GFX90A-NEXT: successors: %bb.65(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr27, killed $vgpr29, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr33, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = V_OR_B32_e32 killed $vgpr17, killed $vgpr3, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr3 = V_OR_B32_e32 killed $vgpr15, killed $vgpr25, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr3, killed $vgpr2, implicit $exec
; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr30, 0, $vgpr3, 0, 0, 6, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, killed $vgpr2, killed $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr4 = V_OR_B32_e32 killed $vgpr18, killed $vgpr21, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr4 = V_OR_B32_e32 killed $vgpr16, killed $vgpr19, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr4, killed $vgpr2, implicit $exec
- ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr7, 0, $vgpr3, 0, 0, 6, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr5, 0, $vgpr3, 0, 0, 6, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, killed $vgpr2, killed $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr14, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr12, implicit $exec
; GFX90A-NEXT: DS_WRITE2_B32_gfx9 killed renamable $vgpr3, killed renamable $vgpr2, renamable $vgpr3, 0, 1, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, align 4, addrspace 3)
; GFX90A-NEXT: S_BRANCH %bb.65
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.68.bb174:
; GFX90A-NEXT: successors: %bb.72(0x40000000), %bb.69(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $agpr0 = COPY killed renamable $vgpr14, implicit $exec
+ ; GFX90A-NEXT: renamable $agpr0 = COPY killed renamable $vgpr12, implicit $exec
; GFX90A-NEXT: renamable $vgpr34 = V_OR_B32_e32 1, $vgpr32, implicit $exec
; GFX90A-NEXT: renamable $vgpr54 = V_OR_B32_e32 $vgpr34, $vgpr28, implicit $exec
; GFX90A-NEXT: renamable $vgpr48 = V_OR_B32_e32 $vgpr54, $vgpr26, implicit $exec
; GFX90A-NEXT: renamable $vgpr36 = V_CNDMASK_B32_e64 0, $vgpr48, 0, 0, $sgpr12_sgpr13, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr52 = V_OR_B32_e32 $vgpr36, $vgpr2, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr50 = V_OR_B32_e32 $vgpr52, $vgpr16, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr38 = V_OR_B32_e32 $vgpr50, $vgpr20, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr38, killed $sgpr12_sgpr13, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr52 = V_OR_B32_e32 $vgpr36, $vgpr24, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr50 = V_OR_B32_e32 $vgpr52, $vgpr14, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr38 = V_OR_B32_e32 $vgpr50, $vgpr18, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr38, killed $sgpr12_sgpr13, implicit $exec
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr28_sgpr29, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.72, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.69.Flow:
; GFX90A-NEXT: successors: %bb.70(0x40000000), %bb.71(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.71, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.70.bb186:
; GFX90A-NEXT: successors: %bb.71(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr4_vgpr5 = nsw V_LSHLREV_B64_e64 3, killed $vgpr4_vgpr5, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = COPY renamable $sgpr27, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr4, renamable $vcc = V_ADD_CO_U32_e64 killed $sgpr26, $vgpr4, 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr2, killed $vgpr5, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2_vgpr3 = nsw V_LSHLREV_B64_e64 3, killed $vgpr2_vgpr3, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr13 = COPY renamable $sgpr27, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2, renamable $vcc = V_ADD_CO_U32_e64 killed $sgpr26, $vgpr2, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr3, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr13, killed $vgpr3, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr35 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr55 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: renamable $vgpr49 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: renamable $vgpr53 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: renamable $vgpr51 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: renamable $vgpr37 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr15 = COPY renamable $vgpr35, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr13 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: renamable $vgpr39 = COPY renamable $vgpr35, implicit $exec
; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, renamable $vgpr34_vgpr35, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr5 = COPY renamable $sgpr21, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr54_vgpr55, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr16 = COPY killed renamable $sgpr22, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr16, killed renamable $vgpr48_vgpr49, 0, 0, implicit $exec :: (store (s64) into %ir.5, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr14 = COPY renamable $sgpr21, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr14, killed renamable $vgpr54_vgpr55, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr17 = COPY killed renamable $sgpr22, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr17, killed renamable $vgpr48_vgpr49, 0, 0, implicit $exec :: (store (s64) into %ir.5, addrspace 3)
; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, killed renamable $vgpr52_vgpr53, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr50_vgpr51, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr14, killed renamable $vgpr50_vgpr51, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, killed renamable $vgpr36_vgpr37, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr5, killed renamable $vgpr14_vgpr15, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr14, killed renamable $vgpr12_vgpr13, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr35, killed renamable $vgpr38_vgpr39, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.71.Flow9:
; GFX90A-NEXT: successors: %bb.63(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr24_sgpr25 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr14 = COPY killed renamable $agpr0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = COPY killed renamable $agpr0, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.63
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.72.bb196:
; GFX90A-NEXT: successors: %bb.69(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr5, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x0000000000000003, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x0000000000000003, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 $vgpr14, killed $vgpr24, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr22 = V_OR_B32_e32 killed $vgpr2, killed $vgpr22, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr23 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr23, renamable $vgpr22_vgpr23, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr13 = V_OR_B32_e32 $vgpr12, killed $vgpr22, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr20 = V_OR_B32_e32 killed $vgpr13, killed $vgpr20, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr21 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr21, renamable $vgpr20_vgpr21, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_MOV_B64 0
; GFX90A-NEXT: S_BRANCH %bb.69
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index 2f287d269e4d8..09785f69eafd8 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -382,9 +382,10 @@ define amdgpu_kernel void @nested_if_if_else(ptr addrspace(1) nocapture %arg) {
; GCN-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GCN-NEXT: s_cbranch_execz .LBB2_5
; GCN-NEXT: ; %bb.1: ; %bb.outer.then
-; GCN-NEXT: v_mov_b32_e32 v4, s1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v1
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT: s_waitcnt expcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_add_i32_e32 v1, vcc, s0, v1
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 2, v0
; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GCN-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -395,8 +396,8 @@ define amdgpu_kernel void @nested_if_if_else(ptr addrspace(1) nocapture %arg) {
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s6
; GCN-NEXT: v_mov_b32_e32 v0, 2
-; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 offset:8
-; GCN-NEXT: ; implicit-def: $vgpr3_vgpr4
+; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8
+; GCN-NEXT: ; implicit-def: $vgpr1_vgpr2
; GCN-NEXT: .LBB2_3: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
; GCN-NEXT: s_cbranch_execz .LBB2_5
@@ -407,13 +408,14 @@ define amdgpu_kernel void @nested_if_if_else(ptr addrspace(1) nocapture %arg) {
; GCN-NEXT: s_mov_b32 s5, s6
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 offset:4
+; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:4
; GCN-NEXT: .LBB2_5: ; %bb.outer.end
; GCN-NEXT: s_or_b64 exec, exec, s[2:3]
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 3
+; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 m0, -1
-; GCN-NEXT: ds_write_b32 v2, v0
+; GCN-NEXT: ds_write_b32 v1, v0
; GCN-NEXT: s_endpgm
;
; GCN-O0-LABEL: nested_if_if_else:
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 581f7a2b83ceb..2e0838d4d4ad7 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -21,15 +21,15 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, 0, v4
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, 0, v5, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, 0, v6, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v17, 31, v3
+; GFX9-NEXT: v_ashrrev_i32_e32 v16, 31, v3
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v21, v5, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v22, v4, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v21, v4, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
-; GFX9-NEXT: v_or_b32_e32 v3, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v22, v0
+; GFX9-NEXT: v_or_b32_e32 v3, v20, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v21, v0
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_or_b32_e32 v3, v9, v11
; GFX9-NEXT: v_or_b32_e32 v2, v8, v10
@@ -38,9 +38,9 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v2, 32, v2
; GFX9-NEXT: v_ffbh_u32_e32 v3, v1
; GFX9-NEXT: v_min_u32_e32 v2, v2, v3
-; GFX9-NEXT: v_ffbh_u32_e32 v3, v22
+; GFX9-NEXT: v_ffbh_u32_e32 v3, v21
; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
-; GFX9-NEXT: v_ffbh_u32_e32 v4, v21
+; GFX9-NEXT: v_ffbh_u32_e32 v4, v20
; GFX9-NEXT: v_min_u32_e32 v3, v3, v4
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, 64, v3
@@ -52,7 +52,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
; GFX9-NEXT: v_min_u32_e32 v3, v3, v6
; GFX9-NEXT: v_ffbh_u32_e32 v6, v8
-; GFX9-NEXT: v_ashrrev_i32_e32 v18, 31, v7
+; GFX9-NEXT: v_ashrrev_i32_e32 v17, 31, v7
; GFX9-NEXT: v_add_u32_e32 v6, 32, v6
; GFX9-NEXT: v_ffbh_u32_e32 v7, v9
; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
@@ -69,10 +69,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v19, v17
+; GFX9-NEXT: v_mov_b32_e32 v18, v16
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v20, v18
+; GFX9-NEXT: v_mov_b32_e32 v19, v17
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
@@ -92,14 +92,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_6
; GFX9-NEXT: ; %bb.1: ; %udiv-bb1
-; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, 1, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 1, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 0x7f, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v5, vcc
; GFX9-NEXT: v_sub_u32_e32 v12, 64, v7
-; GFX9-NEXT: v_or_b32_e32 v4, v24, v26
-; GFX9-NEXT: v_or_b32_e32 v3, v23, v25
+; GFX9-NEXT: v_or_b32_e32 v4, v23, v25
+; GFX9-NEXT: v_or_b32_e32 v3, v22, v24
; GFX9-NEXT: v_lshlrev_b64 v[5:6], v7, v[10:11]
; GFX9-NEXT: v_lshrrev_b64 v[12:13], v12, v[8:9]
; GFX9-NEXT: v_sub_u32_e32 v2, 63, v2
@@ -122,71 +122,73 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_5
; GFX9-NEXT: ; %bb.2: ; %udiv-preheader
-; GFX9-NEXT: v_sub_u32_e32 v12, 64, v23
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v23, v[8:9]
+; GFX9-NEXT: v_sub_u32_e32 v12, 64, v22
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], v22, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[12:13], v12, v[10:11]
-; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23
-; GFX9-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX9-NEXT: v_subrev_u32_e32 v6, 64, v23
+; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v22
+; GFX9-NEXT: v_or_b32_e32 v12, v6, v12
+; GFX9-NEXT: v_subrev_u32_e32 v6, 64, v22
; GFX9-NEXT: v_or_b32_e32 v13, v7, v13
; GFX9-NEXT: v_lshrrev_b64 v[6:7], v6, v[10:11]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v22
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v7, v9, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v6, v14, vcc
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v23, v[10:11]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v9, v8, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v6, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, -1, v22
-; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v21, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v7, v9, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v6, v12, vcc
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], v22, v[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v26, vcc, -1, v21
+; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v20, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: v_mov_b32_e32 v14, 0
; GFX9-NEXT: v_mov_b32_e32 v15, 0
-; GFX9-NEXT: v_mov_b32_e32 v16, 0
; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: .LBB0_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshlrev_b64 v[30:31], 1, v[4:5]
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v5
-; GFX9-NEXT: v_or_b32_e32 v4, v15, v30
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 31, v12
-; GFX9-NEXT: v_lshlrev_b64 v[11:12], 1, v[11:12]
-; GFX9-NEXT: v_or_b32_e32 v5, v16, v31
-; GFX9-NEXT: v_lshlrev_b64 v[13:14], 1, v[13:14]
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 31, v3
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v16
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
-; GFX9-NEXT: v_sub_co_u32_e32 v15, vcc, v10, v11
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v27, v12, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v28, v13, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v29, v14, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v30, 31, v15
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v22
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v3
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, v11, v15
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v21
-; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v12, v15, vcc
-; GFX9-NEXT: v_or3_b32 v2, v2, v6, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 31, v5
+; GFX9-NEXT: v_or3_b32 v2, v2, v30, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 31, v9
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v26, v6
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v14
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v27, v9, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v28, v10, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v29, v11, vcc
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
+; GFX9-NEXT: v_ashrrev_i32_e32 v30, 31, v8
+; GFX9-NEXT: v_and_b32_e32 v8, v30, v21
+; GFX9-NEXT: v_or_b32_e32 v4, v12, v4
+; GFX9-NEXT: v_and_b32_e32 v12, v30, v20
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v6, v8
+; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v9, v12, vcc
; GFX9-NEXT: v_and_b32_e32 v6, v30, v0
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v1
-; GFX9-NEXT: v_subb_co_u32_e32 v13, vcc, v13, v6, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v14, v15, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, -1, v23
+; GFX9-NEXT: v_and_b32_e32 v12, v30, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v10, v6, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v11, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, -1, v22
+; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
-; GFX9-NEXT: v_or_b32_e32 v15, v23, v25
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v26
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[15:16]
+; GFX9-NEXT: v_or_b32_e32 v5, v13, v5
+; GFX9-NEXT: v_or_b32_e32 v12, v22, v24
+; GFX9-NEXT: v_or_b32_e32 v13, v23, v25
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: v_and_b32_e32 v6, 1, v30
-; GFX9-NEXT: v_mov_b32_e32 v16, v7
-; GFX9-NEXT: v_or3_b32 v3, v3, 0, v9
+; GFX9-NEXT: v_mov_b32_e32 v13, v7
+; GFX9-NEXT: v_or3_b32 v3, v3, 0, v15
+; GFX9-NEXT: v_mov_b32_e32 v14, 0
+; GFX9-NEXT: v_mov_b32_e32 v15, 0
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v15, v6
+; GFX9-NEXT: v_mov_b32_e32 v12, v6
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB0_3
; GFX9-NEXT: ; %bb.4: ; %Flow
@@ -201,8 +203,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_or_b32_e32 v6, v6, v0
; GFX9-NEXT: .LBB0_6: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
-; GFX9-NEXT: v_xor_b32_e32 v2, v18, v17
-; GFX9-NEXT: v_xor_b32_e32 v3, v20, v19
+; GFX9-NEXT: v_xor_b32_e32 v2, v17, v16
+; GFX9-NEXT: v_xor_b32_e32 v3, v19, v18
; GFX9-NEXT: v_xor_b32_e32 v0, v6, v2
; GFX9-NEXT: v_xor_b32_e32 v1, v7, v3
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
@@ -2368,63 +2370,65 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subrev_u32_e32 v12, 64, v18
; GFX9-NEXT: v_or_b32_e32 v15, v13, v15
; GFX9-NEXT: v_lshrrev_b64 v[12:13], v12, v[2:3]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX9-NEXT: v_lshrrev_b64 v[2:3], v18, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v15, v13, v1, s[4:5]
-; GFX9-NEXT: v_lshrrev_b64 v[1:2], v18, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, -1, v4
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v14, v12, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v12, v0, s[4:5]
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v7, vcc
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v14, 0
+; GFX9-NEXT: v_mov_b32_e32 v15, 0
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v16, 0
; GFX9-NEXT: v_mov_b32_e32 v17, 0
; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: .LBB1_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 31, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 31, v11
; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 31, v9
+; GFX9-NEXT: v_or_b32_e32 v10, v14, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 31, v1
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_or_b32_e32 v10, v16, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 31, v15
-; GFX9-NEXT: v_lshlrev_b64 v[14:15], 1, v[14:15]
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 31, v9
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v16
-; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v22, v14
-; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v23, v15, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v24, v2, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v25, v3, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v26, 31, v16
-; GFX9-NEXT: v_and_b32_e32 v16, v26, v4
-; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v14, v16
-; GFX9-NEXT: v_and_b32_e32 v16, v26, v5
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v16, vcc
-; GFX9-NEXT: v_and_b32_e32 v16, v26, v6
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v16, vcc
-; GFX9-NEXT: v_and_b32_e32 v16, v26, v7
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v16, vcc
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v12
+; GFX9-NEXT: v_sub_co_u32_e32 v12, vcc, v22, v0
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v14
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v23, v1, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v24, v2, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v25, v3, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v12, 31, v12
+; GFX9-NEXT: v_and_b32_e32 v14, v12, v4
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v14
+; GFX9-NEXT: v_and_b32_e32 v14, v12, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v14, vcc
+; GFX9-NEXT: v_and_b32_e32 v14, v12, v6
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v14, vcc
+; GFX9-NEXT: v_and_b32_e32 v14, v12, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v14, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, -1, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, -1, v19, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v20, vcc, -1, v20, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, -1, v21, vcc
-; GFX9-NEXT: v_or_b32_e32 v11, v17, v11
+; GFX9-NEXT: v_or_b32_e32 v11, v15, v11
+; GFX9-NEXT: v_or_b32_e32 v14, v18, v20
+; GFX9-NEXT: v_or_b32_e32 v15, v19, v21
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
-; GFX9-NEXT: v_or_b32_e32 v16, v18, v20
-; GFX9-NEXT: v_or_b32_e32 v17, v19, v21
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
-; GFX9-NEXT: v_or3_b32 v8, v8, v12, v0
-; GFX9-NEXT: v_and_b32_e32 v12, 1, v26
-; GFX9-NEXT: v_mov_b32_e32 v17, v13
-; GFX9-NEXT: v_or3_b32 v9, v9, 0, v1
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_mov_b32_e32 v15, v13
+; GFX9-NEXT: v_or3_b32 v8, v8, v26, v16
+; GFX9-NEXT: v_or3_b32 v9, v9, 0, v17
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mov_b32_e32 v17, 0
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v16, v12
+; GFX9-NEXT: v_mov_b32_e32 v14, v12
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB1_3
; GFX9-NEXT: ; %bb.4: ; %Flow
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index 0eebada5c1c9e..82faa76ee6ca9 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -96,95 +96,97 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v10, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v11, vcc
; SDAG-NEXT: v_or_b32_e32 v9, v30, v32
-; SDAG-NEXT: v_sub_i32_e32 v34, vcc, 0x7f, v8
+; SDAG-NEXT: v_sub_i32_e32 v11, vcc, 0x7f, v8
; SDAG-NEXT: v_or_b32_e32 v10, v31, v33
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v34
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v34
-; SDAG-NEXT: v_lshl_b64 v[22:23], v[18:19], v34
+; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v11
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v11
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[18:19], v11
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
; SDAG-NEXT: v_lshr_b64 v[8:9], v[18:19], v8
; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
; SDAG-NEXT: v_or_b32_e32 v8, v20, v8
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v34
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v11
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v23, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v22, s[4:5]
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34
+; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v23, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v22, s[4:5]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
-; SDAG-NEXT: v_mov_b32_e32 v8, 0
-; SDAG-NEXT: v_mov_b32_e32 v9, 0
+; SDAG-NEXT: v_mov_b32_e32 v10, 0
+; SDAG-NEXT: v_mov_b32_e32 v11, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_5
; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[18:19], v30
+; SDAG-NEXT: v_lshr_b64 v[10:11], v[18:19], v30
; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v30
; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v20
-; SDAG-NEXT: v_or_b32_e32 v21, v9, v21
-; SDAG-NEXT: v_or_b32_e32 v20, v8, v20
+; SDAG-NEXT: v_or_b32_e32 v21, v11, v21
+; SDAG-NEXT: v_or_b32_e32 v20, v10, v20
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v30
-; SDAG-NEXT: v_subrev_i32_e64 v8, s[4:5], 64, v30
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[16:17], v8
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v21, vcc
+; SDAG-NEXT: v_subrev_i32_e64 v10, s[4:5], 64, v30
+; SDAG-NEXT: v_lshr_b64 v[10:11], v[16:17], v10
+; SDAG-NEXT: v_cndmask_b32_e32 v11, v11, v21, vcc
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v30
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v9, v19, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v20, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v8, v18, s[4:5]
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[16:17], v30
-; SDAG-NEXT: v_cndmask_b32_e32 v23, 0, v9, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v22, 0, v8, vcc
+; SDAG-NEXT: v_cndmask_b32_e64 v19, v11, v19, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v10, v10, v20, vcc
+; SDAG-NEXT: v_cndmask_b32_e64 v18, v10, v18, s[4:5]
+; SDAG-NEXT: v_lshr_b64 v[10:11], v[16:17], v30
+; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v11, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v10, vcc
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29
; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc
; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc
-; SDAG-NEXT: v_mov_b32_e32 v16, 0
-; SDAG-NEXT: v_mov_b32_e32 v17, 0
-; SDAG-NEXT: s_mov_b64 s[4:5], 0
-; SDAG-NEXT: v_mov_b32_e32 v9, 0
; SDAG-NEXT: v_mov_b32_e32 v20, 0
; SDAG-NEXT: v_mov_b32_e32 v21, 0
+; SDAG-NEXT: s_mov_b64 s[4:5], 0
+; SDAG-NEXT: v_mov_b32_e32 v11, 0
+; SDAG-NEXT: v_mov_b32_e32 v22, 0
+; SDAG-NEXT: v_mov_b32_e32 v23, 0
; SDAG-NEXT: .LBB0_3: ; %udiv-do-while3
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshrrev_b32_e32 v8, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
-; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v19
-; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v1
+; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v1
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; SDAG-NEXT: v_or_b32_e32 v11, v21, v11
-; SDAG-NEXT: v_or_b32_e32 v10, v20, v10
-; SDAG-NEXT: v_or_b32_e32 v20, v22, v38
-; SDAG-NEXT: v_or_b32_e32 v18, v18, v39
-; SDAG-NEXT: v_or_b32_e32 v0, v0, v8
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v34, v18
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v35, v19, vcc
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v36, v20, vcc
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v37, v23, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; SDAG-NEXT: v_and_b32_e32 v21, v8, v29
-; SDAG-NEXT: v_and_b32_e32 v22, v8, v28
-; SDAG-NEXT: v_and_b32_e32 v38, v8, v2
-; SDAG-NEXT: v_and_b32_e32 v39, v8, v3
-; SDAG-NEXT: v_and_b32_e32 v8, 1, v8
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v18, v21
-; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v19, v22, vcc
-; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v20, v38, vcc
-; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v39, vcc
+; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v19
+; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
+; SDAG-NEXT: v_or_b32_e32 v8, v20, v8
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v10
+; SDAG-NEXT: v_or_b32_e32 v1, v23, v1
+; SDAG-NEXT: v_or_b32_e32 v16, v16, v39
+; SDAG-NEXT: v_or_b32_e32 v18, v18, v38
+; SDAG-NEXT: v_or_b32_e32 v0, v22, v0
+; SDAG-NEXT: v_sub_i32_e32 v10, vcc, v34, v18
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v35, v19, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v36, v16, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v37, v17, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; SDAG-NEXT: v_and_b32_e32 v20, v10, v29
+; SDAG-NEXT: v_and_b32_e32 v21, v10, v28
+; SDAG-NEXT: v_and_b32_e32 v22, v10, v2
+; SDAG-NEXT: v_and_b32_e32 v23, v10, v3
+; SDAG-NEXT: v_and_b32_e32 v10, 1, v10
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v18, v20
+; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v19, v21, vcc
+; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v22, vcc
+; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v23, vcc
; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30
; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
-; SDAG-NEXT: v_or_b32_e32 v20, v30, v32
; SDAG-NEXT: v_or_b32_e32 v21, v31, v33
+; SDAG-NEXT: v_or_b32_e32 v20, v30, v32
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[20:21]
-; SDAG-NEXT: v_or_b32_e32 v1, v17, v1
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v0, v16, v0
-; SDAG-NEXT: v_mov_b32_e32 v21, v9
-; SDAG-NEXT: v_mov_b32_e32 v20, v8
+; SDAG-NEXT: v_mov_b32_e32 v22, 0
+; SDAG-NEXT: v_mov_b32_e32 v23, 0
+; SDAG-NEXT: v_mov_b32_e32 v21, v11
+; SDAG-NEXT: v_mov_b32_e32 v20, v10
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB0_3
; SDAG-NEXT: ; %bb.4: ; %Flow13
@@ -192,11 +194,11 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: .LBB0_5: ; %Flow14
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[2:3], v[10:11], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[2:3], v[8:9], 1
; SDAG-NEXT: v_or_b32_e32 v0, v0, v16
-; SDAG-NEXT: v_or_b32_e32 v20, v9, v3
-; SDAG-NEXT: v_or_b32_e32 v21, v8, v2
+; SDAG-NEXT: v_or_b32_e32 v20, v11, v3
+; SDAG-NEXT: v_or_b32_e32 v21, v10, v2
; SDAG-NEXT: .LBB0_6: ; %Flow16
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
; SDAG-NEXT: v_ashrrev_i32_e32 v18, 31, v7
@@ -212,186 +214,188 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cndmask_b32_e64 v5, v5, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v8, v6, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
; SDAG-NEXT: v_ffbh_u32_e32 v3, v4
-; SDAG-NEXT: v_ffbh_u32_e32 v6, v5
-; SDAG-NEXT: v_cndmask_b32_e64 v9, v7, v2, s[4:5]
-; SDAG-NEXT: v_sub_i32_e32 v7, vcc, 0, v12
-; SDAG-NEXT: v_or_b32_e32 v2, v4, v8
-; SDAG-NEXT: v_ffbh_u32_e32 v10, v8
+; SDAG-NEXT: v_ffbh_u32_e32 v8, v5
+; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v2, s[4:5]
+; SDAG-NEXT: v_sub_i32_e32 v9, vcc, 0, v12
+; SDAG-NEXT: v_or_b32_e32 v2, v4, v6
+; SDAG-NEXT: v_ffbh_u32_e32 v10, v6
; SDAG-NEXT: v_add_i32_e64 v16, s[4:5], 32, v3
; SDAG-NEXT: v_subb_u32_e32 v17, vcc, 0, v13, vcc
-; SDAG-NEXT: v_or_b32_e32 v3, v5, v9
+; SDAG-NEXT: v_or_b32_e32 v3, v5, v7
; SDAG-NEXT: v_add_i32_e64 v10, s[4:5], 32, v10
-; SDAG-NEXT: v_ffbh_u32_e32 v30, v9
-; SDAG-NEXT: v_min_u32_e32 v6, v16, v6
+; SDAG-NEXT: v_ffbh_u32_e32 v30, v7
+; SDAG-NEXT: v_min_u32_e32 v8, v16, v8
; SDAG-NEXT: v_subb_u32_e32 v16, vcc, 0, v14, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v15
; SDAG-NEXT: v_cndmask_b32_e64 v28, v13, v17, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v29, v12, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v29, v12, v9, s[4:5]
; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[2:3]
; SDAG-NEXT: v_min_u32_e32 v3, v10, v30
-; SDAG-NEXT: v_add_i32_e64 v6, s[8:9], 64, v6
-; SDAG-NEXT: v_addc_u32_e64 v7, s[8:9], 0, 0, s[8:9]
+; SDAG-NEXT: v_add_i32_e64 v8, s[8:9], 64, v8
+; SDAG-NEXT: v_addc_u32_e64 v9, s[8:9], 0, 0, s[8:9]
; SDAG-NEXT: v_subb_u32_e32 v10, vcc, 0, v15, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v2, v14, v16, s[4:5]
; SDAG-NEXT: v_ffbh_u32_e32 v12, v29
; SDAG-NEXT: v_ffbh_u32_e32 v13, v28
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; SDAG-NEXT: v_cndmask_b32_e64 v14, v7, 0, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v16, v6, v3, vcc
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
+; SDAG-NEXT: v_cndmask_b32_e64 v14, v9, 0, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v16, v8, v3, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v3, v15, v10, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v6, v29, v2
+; SDAG-NEXT: v_or_b32_e32 v8, v29, v2
; SDAG-NEXT: v_ffbh_u32_e32 v10, v2
; SDAG-NEXT: v_add_i32_e32 v12, vcc, 32, v12
-; SDAG-NEXT: v_or_b32_e32 v7, v28, v3
+; SDAG-NEXT: v_or_b32_e32 v9, v28, v3
; SDAG-NEXT: v_add_i32_e32 v10, vcc, 32, v10
; SDAG-NEXT: v_ffbh_u32_e32 v15, v3
; SDAG-NEXT: v_min_u32_e32 v12, v12, v13
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
-; SDAG-NEXT: v_min_u32_e32 v6, v10, v15
-; SDAG-NEXT: v_add_i32_e64 v7, s[4:5], 64, v12
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; SDAG-NEXT: v_min_u32_e32 v8, v10, v15
+; SDAG-NEXT: v_add_i32_e64 v9, s[4:5], 64, v12
; SDAG-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; SDAG-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; SDAG-NEXT: v_sub_i32_e32 v6, vcc, v6, v16
-; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v10, v14, vcc
-; SDAG-NEXT: v_xor_b32_e32 v12, 0x7f, v6
+; SDAG-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v8, v16
+; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v10, v14, vcc
+; SDAG-NEXT: v_xor_b32_e32 v12, 0x7f, v8
; SDAG-NEXT: v_subb_u32_e32 v10, vcc, 0, v11, vcc
-; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[10:11], v[6:7]
+; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[10:11], v[8:9]
; SDAG-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc
; SDAG-NEXT: v_or_b32_e32 v12, v12, v10
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
; SDAG-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; SDAG-NEXT: v_or_b32_e32 v13, v7, v11
+; SDAG-NEXT: v_or_b32_e32 v13, v9, v11
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; SDAG-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
; SDAG-NEXT: v_and_b32_e32 v12, 1, v14
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
; SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v15, v9, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v15, v7, 0, s[4:5]
; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; SDAG-NEXT: v_cndmask_b32_e64 v14, v8, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v14, v6, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v13, v5, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v12, v4, 0, s[4:5]
; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc
-; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
+; SDAG-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_12
; SDAG-NEXT: ; %bb.7: ; %udiv-bb1
-; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v6
-; SDAG-NEXT: v_sub_i32_e64 v12, s[4:5], 63, v6
-; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v7, vcc
+; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v8
+; SDAG-NEXT: v_sub_i32_e64 v12, s[4:5], 63, v8
+; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v9, vcc
; SDAG-NEXT: v_lshl_b64 v[12:13], v[4:5], v12
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v10, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v11, vcc
-; SDAG-NEXT: v_or_b32_e32 v10, v30, v32
-; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v6
-; SDAG-NEXT: v_or_b32_e32 v11, v31, v33
-; SDAG-NEXT: v_lshl_b64 v[6:7], v[8:9], v16
-; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v16
-; SDAG-NEXT: v_lshl_b64 v[14:15], v[4:5], v16
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; SDAG-NEXT: v_lshr_b64 v[10:11], v[4:5], v17
-; SDAG-NEXT: v_or_b32_e32 v7, v7, v11
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v10
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v16
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v6, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v15, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5]
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; SDAG-NEXT: v_or_b32_e32 v9, v30, v32
+; SDAG-NEXT: v_sub_i32_e32 v11, vcc, 0x7f, v8
+; SDAG-NEXT: v_or_b32_e32 v10, v31, v33
+; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], v11
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v11
+; SDAG-NEXT: v_lshl_b64 v[16:17], v[4:5], v11
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
+; SDAG-NEXT: v_lshr_b64 v[8:9], v[4:5], v8
+; SDAG-NEXT: v_or_b32_e32 v9, v15, v9
+; SDAG-NEXT: v_or_b32_e32 v8, v14, v8
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v11
+; SDAG-NEXT: v_cndmask_b32_e64 v10, v13, v9, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v12, v12, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v17, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v16, s[4:5]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
+; SDAG-NEXT: v_cndmask_b32_e64 v11, v10, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v10, v12, v6, s[4:5]
; SDAG-NEXT: v_mov_b32_e32 v12, 0
; SDAG-NEXT: v_mov_b32_e32 v13, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
+; SDAG-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_11
; SDAG-NEXT: ; %bb.8: ; %udiv-preheader
; SDAG-NEXT: v_lshr_b64 v[16:17], v[4:5], v30
; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 64, v30
; SDAG-NEXT: v_subrev_i32_e32 v35, vcc, 64, v30
-; SDAG-NEXT: v_lshr_b64 v[37:38], v[8:9], v30
+; SDAG-NEXT: v_lshr_b64 v[36:37], v[6:7], v30
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29
; SDAG-NEXT: v_mov_b32_e32 v14, 0
; SDAG-NEXT: v_mov_b32_e32 v15, 0
-; SDAG-NEXT: s_mov_b64 s[10:11], 0
+; SDAG-NEXT: s_mov_b64 s[12:13], 0
; SDAG-NEXT: v_mov_b32_e32 v13, 0
-; SDAG-NEXT: v_lshl_b64 v[48:49], v[8:9], v12
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[8:9], v35
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v30
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v30
+; SDAG-NEXT: v_lshl_b64 v[38:39], v[6:7], v12
+; SDAG-NEXT: v_lshr_b64 v[48:49], v[6:7], v35
; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc
-; SDAG-NEXT: v_or_b32_e32 v12, v17, v49
-; SDAG-NEXT: v_or_b32_e32 v16, v16, v48
+; SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v37, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v36, s[4:5]
+; SDAG-NEXT: v_or_b32_e32 v12, v17, v39
+; SDAG-NEXT: v_or_b32_e32 v16, v16, v38
; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v30
-; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v12, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v16, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v17, 0, v38, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v16, 0, v37, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v12, v49, v12, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v16, v48, v16, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v30
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v5, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc
-; SDAG-NEXT: v_mov_b32_e32 v4, 0
-; SDAG-NEXT: v_mov_b32_e32 v5, 0
+; SDAG-NEXT: v_cndmask_b32_e64 v5, v12, v5, s[6:7]
+; SDAG-NEXT: v_cndmask_b32_e64 v4, v16, v4, s[6:7]
+; SDAG-NEXT: v_mov_b32_e32 v16, 0
+; SDAG-NEXT: v_mov_b32_e32 v17, 0
; SDAG-NEXT: .LBB0_9: ; %udiv-do-while
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
+; SDAG-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v9
; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v7
-; SDAG-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v5
+; SDAG-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v11
; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
-; SDAG-NEXT: v_or_b32_e32 v12, v16, v12
-; SDAG-NEXT: v_or_b32_e32 v8, v8, v38
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v39
-; SDAG-NEXT: v_or_b32_e32 v7, v15, v7
-; SDAG-NEXT: v_or_b32_e32 v11, v5, v11
-; SDAG-NEXT: v_sub_i32_e32 v5, vcc, v34, v8
-; SDAG-NEXT: v_or_b32_e32 v6, v14, v6
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v35, v9, vcc
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v36, v12, vcc
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v37, v17, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v5
-; SDAG-NEXT: v_and_b32_e32 v16, v5, v29
-; SDAG-NEXT: v_and_b32_e32 v38, v5, v28
-; SDAG-NEXT: v_and_b32_e32 v39, v5, v2
-; SDAG-NEXT: v_and_b32_e32 v48, v5, v3
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v8, v16
-; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v9, v38, vcc
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v12, v39, vcc
-; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v48, vcc
+; SDAG-NEXT: v_or_b32_e32 v9, v15, v9
+; SDAG-NEXT: v_or_b32_e32 v8, v14, v8
+; SDAG-NEXT: v_or_b32_e32 v6, v6, v38
+; SDAG-NEXT: v_or_b32_e32 v4, v4, v39
+; SDAG-NEXT: v_or_b32_e32 v10, v10, v12
+; SDAG-NEXT: v_or_b32_e32 v11, v17, v11
+; SDAG-NEXT: v_or_b32_e32 v10, v16, v10
+; SDAG-NEXT: v_sub_i32_e32 v12, vcc, v34, v4
+; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v35, v5, vcc
+; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v36, v6, vcc
+; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v37, v7, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v14, 31, v12
+; SDAG-NEXT: v_and_b32_e32 v12, 1, v14
+; SDAG-NEXT: v_and_b32_e32 v15, v14, v3
+; SDAG-NEXT: v_and_b32_e32 v16, v14, v2
+; SDAG-NEXT: v_and_b32_e32 v17, v14, v28
+; SDAG-NEXT: v_and_b32_e32 v14, v14, v29
+; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v14
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v17, vcc
+; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v16, vcc
+; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v15, vcc
; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30
; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
-; SDAG-NEXT: v_or_b32_e32 v38, v30, v32
-; SDAG-NEXT: v_or_b32_e32 v39, v31, v33
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[38:39]
-; SDAG-NEXT: v_and_b32_e32 v12, 1, v5
-; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v10, v4, v10
-; SDAG-NEXT: v_mov_b32_e32 v4, v12
-; SDAG-NEXT: v_mov_b32_e32 v5, v13
-; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
+; SDAG-NEXT: v_or_b32_e32 v15, v31, v33
+; SDAG-NEXT: v_or_b32_e32 v14, v30, v32
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; SDAG-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
+; SDAG-NEXT: v_mov_b32_e32 v16, 0
+; SDAG-NEXT: v_mov_b32_e32 v17, 0
+; SDAG-NEXT: v_mov_b32_e32 v15, v13
+; SDAG-NEXT: v_mov_b32_e32 v14, v12
+; SDAG-NEXT: s_andn2_b64 exec, exec, s[12:13]
; SDAG-NEXT: s_cbranch_execnz .LBB0_9
; SDAG-NEXT: ; %bb.10: ; %Flow
-; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
+; SDAG-NEXT: s_or_b64 exec, exec, s[12:13]
; SDAG-NEXT: .LBB0_11: ; %Flow11
-; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
-; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[2:3], v[10:11], 1
+; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
+; SDAG-NEXT: v_lshl_b64 v[14:15], v[10:11], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[2:3], v[8:9], 1
; SDAG-NEXT: v_or_b32_e32 v14, v14, v4
; SDAG-NEXT: v_or_b32_e32 v13, v13, v3
; SDAG-NEXT: v_or_b32_e32 v12, v12, v2
; SDAG-NEXT: .LBB0_12: ; %Flow12
-; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
+; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
; SDAG-NEXT: v_xor_b32_e32 v3, v27, v26
; SDAG-NEXT: v_xor_b32_e32 v2, v25, v24
; SDAG-NEXT: v_xor_b32_e32 v7, v23, v22
@@ -1007,44 +1011,46 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_mov_b32_e32 v25, 0
; SDAG-NEXT: .LBB2_3: ; %udiv-do-while3
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshrrev_b32_e32 v34, 31, v19
+; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
-; SDAG-NEXT: v_or_b32_e32 v19, v25, v19
-; SDAG-NEXT: v_or_b32_e32 v18, v24, v18
+; SDAG-NEXT: v_or_b32_e32 v19, v23, v19
+; SDAG-NEXT: v_or_b32_e32 v18, v22, v18
+; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v3
+; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
+; SDAG-NEXT: v_or_b32_e32 v2, v2, v20
+; SDAG-NEXT: v_or_b32_e32 v3, v25, v3
+; SDAG-NEXT: v_or_b32_e32 v2, v24, v2
; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v1
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SDAG-NEXT: v_or_b32_e32 v16, v16, v20
-; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v3
-; SDAG-NEXT: v_or_b32_e32 v0, v0, v20
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v22
; SDAG-NEXT: v_sub_i32_e32 v20, vcc, v30, v0
; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v31, v1, vcc
; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v32, v16, vcc
; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v33, v17, vcc
; SDAG-NEXT: v_ashrrev_i32_e32 v20, 31, v20
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v8
-; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v24
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v9
-; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v24, vcc
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v10
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v24, vcc
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v11
-; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v24, vcc
+; SDAG-NEXT: v_and_b32_e32 v22, v20, v8
+; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v22
+; SDAG-NEXT: v_and_b32_e32 v22, v20, v9
+; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v22, vcc
+; SDAG-NEXT: v_and_b32_e32 v22, v20, v10
+; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v22, vcc
+; SDAG-NEXT: v_and_b32_e32 v22, v20, v11
+; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v22, vcc
; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v26
; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc
; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
-; SDAG-NEXT: v_or_b32_e32 v24, v26, v28
-; SDAG-NEXT: v_or_b32_e32 v25, v27, v29
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25]
+; SDAG-NEXT: v_or_b32_e32 v22, v26, v28
+; SDAG-NEXT: v_or_b32_e32 v23, v27, v29
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23]
; SDAG-NEXT: v_and_b32_e32 v20, 1, v20
-; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; SDAG-NEXT: v_or_b32_e32 v2, v2, v34
-; SDAG-NEXT: v_or_b32_e32 v3, v23, v3
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v2, v22, v2
-; SDAG-NEXT: v_mov_b32_e32 v25, v21
-; SDAG-NEXT: v_mov_b32_e32 v24, v20
+; SDAG-NEXT: v_mov_b32_e32 v24, 0
+; SDAG-NEXT: v_mov_b32_e32 v25, 0
+; SDAG-NEXT: v_mov_b32_e32 v23, v21
+; SDAG-NEXT: v_mov_b32_e32 v22, v20
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB2_3
; SDAG-NEXT: ; %bb.4: ; %Flow13
@@ -1137,13 +1143,13 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_or_b32_e32 v1, v1, v11
; SDAG-NEXT: v_or_b32_e32 v0, v0, v10
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v20
-; SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v17, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v16, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v1, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v17, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, v16, s[4:5]
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v20
-; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v6, s[4:5]
; SDAG-NEXT: v_mov_b32_e32 v16, 0
; SDAG-NEXT: v_mov_b32_e32 v17, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -1155,8 +1161,8 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_subrev_i32_e32 v27, vcc, 64, v22
; SDAG-NEXT: v_lshr_b64 v[29:30], v[6:7], v22
; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v12
-; SDAG-NEXT: v_mov_b32_e32 v8, 0
-; SDAG-NEXT: v_mov_b32_e32 v9, 0
+; SDAG-NEXT: v_mov_b32_e32 v10, 0
+; SDAG-NEXT: v_mov_b32_e32 v11, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
; SDAG-NEXT: v_mov_b32_e32 v17, 0
; SDAG-NEXT: v_lshl_b64 v[31:32], v[6:7], v16
@@ -1166,65 +1172,67 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_or_b32_e32 v20, v20, v31
; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v22
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v20, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v21, 0, v30, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v20, 0, v29, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v16, v7, v16, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v6, v20, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v7, 0, v30, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v29, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc
; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v22
-; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
-; SDAG-NEXT: v_mov_b32_e32 v4, 0
-; SDAG-NEXT: v_mov_b32_e32 v5, 0
+; SDAG-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; SDAG-NEXT: v_mov_b32_e32 v20, 0
+; SDAG-NEXT: v_mov_b32_e32 v21, 0
; SDAG-NEXT: .LBB2_9: ; %udiv-do-while
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v7
; SDAG-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v30, 31, v1
+; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v5
+; SDAG-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v30, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v31, 31, v1
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v31, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
-; SDAG-NEXT: v_or_b32_e32 v20, v20, v16
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v30
-; SDAG-NEXT: v_or_b32_e32 v0, v0, v31
-; SDAG-NEXT: v_or_b32_e32 v1, v9, v1
-; SDAG-NEXT: v_sub_i32_e32 v16, vcc, v26, v6
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v27, v7, vcc
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v28, v20, vcc
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v29, v21, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v30, 31, v16
-; SDAG-NEXT: v_and_b32_e32 v16, v30, v13
-; SDAG-NEXT: v_and_b32_e32 v31, v30, v12
-; SDAG-NEXT: v_sub_i32_e32 v6, vcc, v6, v31
-; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v16, vcc
-; SDAG-NEXT: v_or_b32_e32 v11, v5, v11
-; SDAG-NEXT: v_or_b32_e32 v0, v8, v0
-; SDAG-NEXT: v_and_b32_e32 v16, 1, v30
-; SDAG-NEXT: v_and_b32_e32 v5, v30, v15
-; SDAG-NEXT: v_and_b32_e32 v30, v30, v14
-; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v20, v30, vcc
-; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v5, vcc
+; SDAG-NEXT: v_or_b32_e32 v6, v6, v16
+; SDAG-NEXT: v_or_b32_e32 v4, v4, v30
+; SDAG-NEXT: v_or_b32_e32 v8, v8, v31
+; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
+; SDAG-NEXT: v_or_b32_e32 v1, v11, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v10, v0
+; SDAG-NEXT: v_or_b32_e32 v8, v20, v8
+; SDAG-NEXT: v_sub_i32_e32 v10, vcc, v26, v4
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v27, v5, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v28, v6, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v29, v7, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; SDAG-NEXT: v_and_b32_e32 v16, 1, v10
+; SDAG-NEXT: v_and_b32_e32 v11, v10, v15
+; SDAG-NEXT: v_and_b32_e32 v20, v10, v14
+; SDAG-NEXT: v_and_b32_e32 v21, v10, v13
+; SDAG-NEXT: v_and_b32_e32 v10, v10, v12
+; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v10
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v21, vcc
+; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v20, vcc
+; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v11, vcc
; SDAG-NEXT: v_add_i32_e32 v22, vcc, -1, v22
; SDAG-NEXT: v_addc_u32_e32 v23, vcc, -1, v23, vcc
; SDAG-NEXT: v_addc_u32_e32 v24, vcc, -1, v24, vcc
; SDAG-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc
-; SDAG-NEXT: v_or_b32_e32 v31, v23, v25
-; SDAG-NEXT: v_or_b32_e32 v30, v22, v24
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[30:31]
+; SDAG-NEXT: v_or_b32_e32 v11, v23, v25
+; SDAG-NEXT: v_or_b32_e32 v10, v22, v24
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v10, v4, v10
-; SDAG-NEXT: v_mov_b32_e32 v4, v16
-; SDAG-NEXT: v_mov_b32_e32 v5, v17
+; SDAG-NEXT: v_mov_b32_e32 v20, 0
+; SDAG-NEXT: v_mov_b32_e32 v21, 0
+; SDAG-NEXT: v_mov_b32_e32 v10, v16
+; SDAG-NEXT: v_mov_b32_e32 v11, v17
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB2_9
; SDAG-NEXT: ; %bb.10: ; %Flow
; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
; SDAG-NEXT: .LBB2_11: ; %Flow11
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
-; SDAG-NEXT: v_lshl_b64 v[8:9], v[0:1], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[0:1], v[10:11], 1
+; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v1
+; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; SDAG-NEXT: v_or_b32_e32 v8, v8, v4
; SDAG-NEXT: v_or_b32_e32 v10, v17, v1
; SDAG-NEXT: v_or_b32_e32 v11, v16, v0
@@ -1638,7 +1646,6 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-LABEL: v_srem_v2i128_vv:
; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0, v0
; SDAG-NEXT: v_mov_b32_e32 v19, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0x7f
@@ -1739,83 +1746,85 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v22
; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v19, 0, v21, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v18, 0, v20, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v21, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v20, s[4:5]
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v22
; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v1, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[4:5]
-; SDAG-NEXT: v_mov_b32_e32 v10, 0
-; SDAG-NEXT: v_mov_b32_e32 v11, 0
+; SDAG-NEXT: v_mov_b32_e32 v18, 0
+; SDAG-NEXT: v_mov_b32_e32 v19, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB4_5
; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4
-; SDAG-NEXT: v_lshr_b64 v[22:23], v[16:17], v32
-; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 64, v32
+; SDAG-NEXT: v_lshr_b64 v[20:21], v[16:17], v32
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v32
; SDAG-NEXT: v_subrev_i32_e32 v37, vcc, 64, v32
-; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v32
+; SDAG-NEXT: v_lshr_b64 v[22:23], v[0:1], v32
; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v31
-; SDAG-NEXT: v_mov_b32_e32 v20, 0
-; SDAG-NEXT: v_mov_b32_e32 v21, 0
+; SDAG-NEXT: v_mov_b32_e32 v24, 0
+; SDAG-NEXT: v_mov_b32_e32 v25, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
-; SDAG-NEXT: v_mov_b32_e32 v11, 0
-; SDAG-NEXT: v_lshl_b64 v[26:27], v[0:1], v10
+; SDAG-NEXT: v_mov_b32_e32 v19, 0
+; SDAG-NEXT: v_lshl_b64 v[26:27], v[0:1], v18
; SDAG-NEXT: v_lshr_b64 v[48:49], v[0:1], v37
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v30, vcc
-; SDAG-NEXT: v_or_b32_e32 v10, v23, v27
-; SDAG-NEXT: v_or_b32_e32 v22, v22, v26
+; SDAG-NEXT: v_or_b32_e32 v18, v21, v27
+; SDAG-NEXT: v_or_b32_e32 v20, v20, v26
; SDAG-NEXT: v_addc_u32_e32 v38, vcc, -1, v2, vcc
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v32
-; SDAG-NEXT: v_cndmask_b32_e64 v10, v49, v10, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v22, v48, v22, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v27, 0, v25, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v26, 0, v24, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v18, v49, v18, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v48, v20, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v23, 0, v23, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, 0, v22, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v3, vcc
; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v32
-; SDAG-NEXT: v_cndmask_b32_e32 v25, v10, v17, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v16, vcc
-; SDAG-NEXT: v_mov_b32_e32 v22, 0
-; SDAG-NEXT: v_mov_b32_e32 v23, 0
+; SDAG-NEXT: v_cndmask_b32_e32 v21, v18, v17, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v20, v20, v16, vcc
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
; SDAG-NEXT: .LBB4_3: ; %udiv-do-while3
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v19
-; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
-; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v48, 31, v25
-; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v49, 31, v9
+; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v11
+; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v48, 31, v9
; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
-; SDAG-NEXT: v_or_b32_e32 v19, v23, v19
-; SDAG-NEXT: v_or_b32_e32 v18, v22, v18
-; SDAG-NEXT: v_or_b32_e32 v22, v26, v48
-; SDAG-NEXT: v_or_b32_e32 v23, v24, v49
-; SDAG-NEXT: v_or_b32_e32 v8, v8, v10
-; SDAG-NEXT: v_sub_i32_e32 v10, vcc, v36, v23
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v37, v25, vcc
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v38, v22, vcc
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v39, v27, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v10
-; SDAG-NEXT: v_and_b32_e32 v24, v10, v31
-; SDAG-NEXT: v_and_b32_e32 v26, v10, v30
-; SDAG-NEXT: v_and_b32_e32 v48, v10, v2
-; SDAG-NEXT: v_and_b32_e32 v49, v10, v3
-; SDAG-NEXT: v_and_b32_e32 v10, 1, v10
-; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v23, v24
-; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v26, vcc
-; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v22, v48, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v49, vcc
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v49, 31, v21
+; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
+; SDAG-NEXT: v_or_b32_e32 v11, v25, v11
+; SDAG-NEXT: v_or_b32_e32 v10, v24, v10
+; SDAG-NEXT: v_or_b32_e32 v8, v8, v18
+; SDAG-NEXT: v_or_b32_e32 v9, v27, v9
+; SDAG-NEXT: v_or_b32_e32 v22, v22, v49
+; SDAG-NEXT: v_or_b32_e32 v20, v20, v48
+; SDAG-NEXT: v_or_b32_e32 v8, v26, v8
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v36, v20
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v37, v21, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v38, v22, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v39, v23, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v18, 31, v18
+; SDAG-NEXT: v_and_b32_e32 v24, v18, v31
+; SDAG-NEXT: v_and_b32_e32 v25, v18, v30
+; SDAG-NEXT: v_and_b32_e32 v26, v18, v2
+; SDAG-NEXT: v_and_b32_e32 v27, v18, v3
+; SDAG-NEXT: v_and_b32_e32 v18, 1, v18
+; SDAG-NEXT: v_sub_i32_e32 v20, vcc, v20, v24
+; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v25, vcc
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v22, v26, vcc
+; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v27, vcc
; SDAG-NEXT: v_add_i32_e32 v32, vcc, -1, v32
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
; SDAG-NEXT: v_addc_u32_e32 v34, vcc, -1, v34, vcc
; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc
-; SDAG-NEXT: v_or_b32_e32 v22, v32, v34
-; SDAG-NEXT: v_or_b32_e32 v23, v33, v35
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23]
-; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
+; SDAG-NEXT: v_or_b32_e32 v25, v33, v35
+; SDAG-NEXT: v_or_b32_e32 v24, v32, v34
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v8, v20, v8
-; SDAG-NEXT: v_mov_b32_e32 v23, v11
-; SDAG-NEXT: v_mov_b32_e32 v22, v10
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
+; SDAG-NEXT: v_mov_b32_e32 v25, v19
+; SDAG-NEXT: v_mov_b32_e32 v24, v18
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB4_3
; SDAG-NEXT: ; %bb.4: ; %Flow13
@@ -1823,11 +1832,11 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: .LBB4_5: ; %Flow14
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19
-; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v11
+; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; SDAG-NEXT: v_or_b32_e32 v8, v8, v20
-; SDAG-NEXT: v_or_b32_e32 v33, v11, v19
-; SDAG-NEXT: v_or_b32_e32 v34, v10, v18
+; SDAG-NEXT: v_or_b32_e32 v33, v19, v11
+; SDAG-NEXT: v_or_b32_e32 v34, v18, v10
; SDAG-NEXT: .LBB4_6: ; %Flow16
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
; SDAG-NEXT: v_ashrrev_i32_e32 v32, 31, v7
@@ -1959,54 +1968,56 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v38
; SDAG-NEXT: v_cndmask_b32_e64 v18, v54, v18, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v22, v53, v22, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v27, 0, v25, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v26, 0, v24, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v25, 0, v25, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v53, vcc, -1, v7, vcc
; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v38
-; SDAG-NEXT: v_cndmask_b32_e32 v25, v18, v11, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v10, vcc
-; SDAG-NEXT: v_mov_b32_e32 v22, 0
-; SDAG-NEXT: v_mov_b32_e32 v23, 0
+; SDAG-NEXT: v_cndmask_b32_e32 v23, v18, v11, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v22, v22, v10, vcc
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
; SDAG-NEXT: .LBB4_9: ; %udiv-do-while
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v25
; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v23
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v54, 31, v15
; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v55, 31, v13
; SDAG-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
-; SDAG-NEXT: v_or_b32_e32 v26, v26, v18
-; SDAG-NEXT: v_or_b32_e32 v24, v24, v54
+; SDAG-NEXT: v_or_b32_e32 v24, v24, v18
+; SDAG-NEXT: v_or_b32_e32 v22, v22, v54
; SDAG-NEXT: v_or_b32_e32 v14, v14, v55
-; SDAG-NEXT: v_or_b32_e32 v15, v21, v15
-; SDAG-NEXT: v_or_b32_e32 v13, v23, v13
-; SDAG-NEXT: v_or_b32_e32 v14, v20, v14
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v50, v24
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v51, v25, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v52, v26, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v53, v27, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v23, 31, v18
-; SDAG-NEXT: v_and_b32_e32 v18, 1, v23
-; SDAG-NEXT: v_and_b32_e32 v54, v23, v7
-; SDAG-NEXT: v_and_b32_e32 v55, v23, v6
-; SDAG-NEXT: v_and_b32_e32 v40, v23, v36
-; SDAG-NEXT: v_and_b32_e32 v23, v23, v37
-; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v24, v23
-; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v40, vcc
-; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v55, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v54, vcc
+; SDAG-NEXT: v_or_b32_e32 v15, v27, v15
+; SDAG-NEXT: v_or_b32_e32 v13, v21, v13
+; SDAG-NEXT: v_or_b32_e32 v12, v20, v12
+; SDAG-NEXT: v_or_b32_e32 v14, v26, v14
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v50, v22
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v51, v23, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v52, v24, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v53, v25, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v20, 31, v18
+; SDAG-NEXT: v_and_b32_e32 v18, 1, v20
+; SDAG-NEXT: v_and_b32_e32 v21, v20, v7
+; SDAG-NEXT: v_and_b32_e32 v26, v20, v6
+; SDAG-NEXT: v_and_b32_e32 v27, v20, v36
+; SDAG-NEXT: v_and_b32_e32 v20, v20, v37
+; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v22, v20
+; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v27, vcc
+; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v24, v26, vcc
+; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v21, vcc
; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v38
; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v39, vcc
; SDAG-NEXT: v_addc_u32_e32 v48, vcc, -1, v48, vcc
; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v49, vcc
-; SDAG-NEXT: v_or_b32_e32 v55, v39, v49
-; SDAG-NEXT: v_or_b32_e32 v54, v38, v48
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[54:55]
+; SDAG-NEXT: v_or_b32_e32 v21, v39, v49
+; SDAG-NEXT: v_or_b32_e32 v20, v38, v48
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[20:21]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v12, v22, v12
-; SDAG-NEXT: v_mov_b32_e32 v23, v19
-; SDAG-NEXT: v_mov_b32_e32 v22, v18
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
+; SDAG-NEXT: v_mov_b32_e32 v21, v19
+; SDAG-NEXT: v_mov_b32_e32 v20, v18
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB4_9
; SDAG-NEXT: ; %bb.10: ; %Flow
@@ -2084,8 +2095,6 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v6, v35, vcc
; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v7, v32, vcc
; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v9, v35, vcc
-; SDAG-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
-; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: v_srem_v2i128_vv:
@@ -2610,83 +2619,85 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v25
; SDAG-NEXT: v_cndmask_b32_e64 v17, v17, v19, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, v18, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v21, 0, v24, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v20, 0, v23, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v19, 0, v24, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v18, 0, v23, s[4:5]
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v25
; SDAG-NEXT: v_cndmask_b32_e64 v17, v17, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, v2, s[4:5]
-; SDAG-NEXT: v_mov_b32_e32 v18, 0
-; SDAG-NEXT: v_mov_b32_e32 v19, 0
+; SDAG-NEXT: v_mov_b32_e32 v20, 0
+; SDAG-NEXT: v_mov_b32_e32 v21, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB5_5
; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4
-; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v30
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v30
+; SDAG-NEXT: v_lshr_b64 v[22:23], v[0:1], v30
+; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v30
; SDAG-NEXT: v_subrev_i32_e32 v35, vcc, 64, v30
-; SDAG-NEXT: v_lshr_b64 v[26:27], v[2:3], v30
+; SDAG-NEXT: v_lshr_b64 v[24:25], v[2:3], v30
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v8
-; SDAG-NEXT: v_mov_b32_e32 v22, 0
-; SDAG-NEXT: v_mov_b32_e32 v23, 0
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
-; SDAG-NEXT: v_mov_b32_e32 v19, 0
-; SDAG-NEXT: v_lshl_b64 v[28:29], v[2:3], v18
+; SDAG-NEXT: v_mov_b32_e32 v21, 0
+; SDAG-NEXT: v_lshl_b64 v[28:29], v[2:3], v20
; SDAG-NEXT: v_lshr_b64 v[37:38], v[2:3], v35
; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v9, vcc
-; SDAG-NEXT: v_or_b32_e32 v18, v25, v29
-; SDAG-NEXT: v_or_b32_e32 v24, v24, v28
+; SDAG-NEXT: v_or_b32_e32 v20, v23, v29
+; SDAG-NEXT: v_or_b32_e32 v22, v22, v28
; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v10, vcc
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v30
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v38, v18, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v24, v37, v24, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v29, 0, v27, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v28, 0, v26, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v38, v20, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, v37, v22, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v25, 0, v25, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v24, 0, v24, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v11, vcc
; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v30
-; SDAG-NEXT: v_cndmask_b32_e32 v27, v18, v1, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v26, v24, v0, vcc
-; SDAG-NEXT: v_mov_b32_e32 v24, 0
-; SDAG-NEXT: v_mov_b32_e32 v25, 0
+; SDAG-NEXT: v_cndmask_b32_e32 v23, v20, v1, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; SDAG-NEXT: v_mov_b32_e32 v28, 0
+; SDAG-NEXT: v_mov_b32_e32 v29, 0
; SDAG-NEXT: .LBB5_3: ; %udiv-do-while3
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v21
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
-; SDAG-NEXT: v_lshl_b64 v[28:29], v[28:29], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v27
-; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v17
+; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19
+; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v17
; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
-; SDAG-NEXT: v_or_b32_e32 v21, v25, v21
-; SDAG-NEXT: v_or_b32_e32 v20, v24, v20
-; SDAG-NEXT: v_or_b32_e32 v24, v28, v38
-; SDAG-NEXT: v_or_b32_e32 v25, v26, v39
-; SDAG-NEXT: v_or_b32_e32 v16, v16, v18
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v34, v25
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v35, v27, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v36, v24, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v37, v29, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v18, 31, v18
-; SDAG-NEXT: v_and_b32_e32 v26, v18, v8
-; SDAG-NEXT: v_and_b32_e32 v28, v18, v9
-; SDAG-NEXT: v_and_b32_e32 v38, v18, v10
-; SDAG-NEXT: v_and_b32_e32 v39, v18, v11
-; SDAG-NEXT: v_and_b32_e32 v18, 1, v18
-; SDAG-NEXT: v_sub_i32_e32 v26, vcc, v25, v26
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v28, vcc
-; SDAG-NEXT: v_subb_u32_e32 v28, vcc, v24, v38, vcc
-; SDAG-NEXT: v_subb_u32_e32 v29, vcc, v29, v39, vcc
+; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v23
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
+; SDAG-NEXT: v_or_b32_e32 v19, v27, v19
+; SDAG-NEXT: v_or_b32_e32 v18, v26, v18
+; SDAG-NEXT: v_or_b32_e32 v16, v16, v20
+; SDAG-NEXT: v_or_b32_e32 v17, v29, v17
+; SDAG-NEXT: v_or_b32_e32 v20, v24, v39
+; SDAG-NEXT: v_or_b32_e32 v22, v22, v38
+; SDAG-NEXT: v_or_b32_e32 v16, v28, v16
+; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v34, v22
+; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v35, v23, vcc
+; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v36, v20, vcc
+; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v37, v25, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v28, 31, v24
+; SDAG-NEXT: v_and_b32_e32 v24, v28, v8
+; SDAG-NEXT: v_and_b32_e32 v26, v28, v9
+; SDAG-NEXT: v_and_b32_e32 v27, v28, v10
+; SDAG-NEXT: v_and_b32_e32 v29, v28, v11
+; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v22, v24
+; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v26, vcc
+; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v20, v27, vcc
+; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v29, vcc
; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30
; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
-; SDAG-NEXT: v_or_b32_e32 v24, v30, v32
-; SDAG-NEXT: v_or_b32_e32 v25, v31, v33
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25]
-; SDAG-NEXT: v_or_b32_e32 v17, v23, v17
+; SDAG-NEXT: v_or_b32_e32 v26, v30, v32
+; SDAG-NEXT: v_or_b32_e32 v27, v31, v33
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[26:27]
+; SDAG-NEXT: v_and_b32_e32 v20, 1, v28
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v16, v22, v16
-; SDAG-NEXT: v_mov_b32_e32 v25, v19
-; SDAG-NEXT: v_mov_b32_e32 v24, v18
+; SDAG-NEXT: v_mov_b32_e32 v28, 0
+; SDAG-NEXT: v_mov_b32_e32 v29, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, v21
+; SDAG-NEXT: v_mov_b32_e32 v26, v20
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB5_3
; SDAG-NEXT: ; %bb.4: ; %Flow13
@@ -2694,11 +2705,11 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: .LBB5_5: ; %Flow14
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v21
+; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v19
; SDAG-NEXT: v_or_b32_e32 v16, v16, v22
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
-; SDAG-NEXT: v_or_b32_e32 v32, v19, v21
-; SDAG-NEXT: v_or_b32_e32 v33, v18, v20
+; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_or_b32_e32 v32, v21, v19
+; SDAG-NEXT: v_or_b32_e32 v33, v20, v18
; SDAG-NEXT: .LBB5_6: ; %Flow16
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
; SDAG-NEXT: v_or_b32_e32 v19, v13, v15
@@ -2736,126 +2747,128 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; SDAG-NEXT: v_cndmask_b32_e64 v19, v23, 0, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc
-; SDAG-NEXT: v_sub_i32_e32 v20, vcc, v18, v20
-; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v22, v19, vcc
-; SDAG-NEXT: v_xor_b32_e32 v18, 0x7f, v20
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v18, v20
+; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v22, v19, vcc
+; SDAG-NEXT: v_xor_b32_e32 v20, 0x7f, v18
; SDAG-NEXT: v_subb_u32_e32 v22, vcc, 0, v30, vcc
-; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[8:9], v[20:21]
+; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[8:9], v[18:19]
; SDAG-NEXT: v_cndmask_b32_e64 v24, 0, 1, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v23, vcc, 0, v30, vcc
-; SDAG-NEXT: v_or_b32_e32 v18, v18, v22
+; SDAG-NEXT: v_or_b32_e32 v20, v20, v22
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23]
; SDAG-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc
-; SDAG-NEXT: v_or_b32_e32 v19, v21, v23
+; SDAG-NEXT: v_or_b32_e32 v21, v19, v23
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23]
; SDAG-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19]
-; SDAG-NEXT: v_and_b32_e32 v18, 1, v24
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v18
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21]
+; SDAG-NEXT: v_and_b32_e32 v20, 1, v24
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v20
; SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v7, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v21, v7, 0, s[4:5]
; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v6, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v6, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v24, v5, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v25, v4, 0, s[4:5]
; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB5_12
; SDAG-NEXT: ; %bb.7: ; %udiv-bb1
-; SDAG-NEXT: v_add_i32_e32 v34, vcc, 1, v20
-; SDAG-NEXT: v_sub_i32_e64 v18, s[4:5], 63, v20
-; SDAG-NEXT: v_addc_u32_e32 v35, vcc, 0, v21, vcc
-; SDAG-NEXT: v_lshl_b64 v[18:19], v[4:5], v18
+; SDAG-NEXT: v_add_i32_e32 v34, vcc, 1, v18
+; SDAG-NEXT: v_sub_i32_e64 v20, s[4:5], 63, v18
+; SDAG-NEXT: v_addc_u32_e32 v35, vcc, 0, v19, vcc
+; SDAG-NEXT: v_lshl_b64 v[19:20], v[4:5], v20
; SDAG-NEXT: v_addc_u32_e32 v36, vcc, 0, v22, vcc
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, 0, v23, vcc
; SDAG-NEXT: v_or_b32_e32 v21, v34, v36
-; SDAG-NEXT: v_sub_i32_e32 v27, vcc, 0x7f, v20
+; SDAG-NEXT: v_sub_i32_e32 v27, vcc, 0x7f, v18
; SDAG-NEXT: v_or_b32_e32 v22, v35, v37
; SDAG-NEXT: v_lshl_b64 v[23:24], v[6:7], v27
-; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v27
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v27
; SDAG-NEXT: v_lshl_b64 v[25:26], v[4:5], v27
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[21:22]
-; SDAG-NEXT: v_lshr_b64 v[20:21], v[4:5], v20
-; SDAG-NEXT: v_or_b32_e32 v21, v24, v21
-; SDAG-NEXT: v_or_b32_e32 v20, v23, v20
+; SDAG-NEXT: v_lshr_b64 v[21:22], v[4:5], v18
+; SDAG-NEXT: v_or_b32_e32 v18, v24, v22
+; SDAG-NEXT: v_or_b32_e32 v21, v23, v21
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v27
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v19, v21, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v18, v20, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v21, 0, v26, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v20, 0, v25, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v20, v18, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, v19, v21, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v19, 0, v26, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v18, 0, v25, s[4:5]
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v27
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v19, v7, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v18, v6, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v21, v20, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v22, v6, s[4:5]
; SDAG-NEXT: v_mov_b32_e32 v22, 0
; SDAG-NEXT: v_mov_b32_e32 v23, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB5_11
; SDAG-NEXT: ; %bb.8: ; %udiv-preheader
-; SDAG-NEXT: v_lshr_b64 v[26:27], v[4:5], v34
+; SDAG-NEXT: v_lshr_b64 v[24:25], v[4:5], v34
; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 64, v34
; SDAG-NEXT: v_subrev_i32_e32 v39, vcc, 64, v34
; SDAG-NEXT: v_lshr_b64 v[28:29], v[6:7], v34
; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v12
-; SDAG-NEXT: v_mov_b32_e32 v24, 0
-; SDAG-NEXT: v_mov_b32_e32 v25, 0
+; SDAG-NEXT: v_mov_b32_e32 v26, 0
+; SDAG-NEXT: v_mov_b32_e32 v27, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
; SDAG-NEXT: v_mov_b32_e32 v23, 0
; SDAG-NEXT: v_lshl_b64 v[30:31], v[6:7], v22
; SDAG-NEXT: v_lshr_b64 v[49:50], v[6:7], v39
; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v13, vcc
-; SDAG-NEXT: v_or_b32_e32 v22, v27, v31
-; SDAG-NEXT: v_or_b32_e32 v26, v26, v30
+; SDAG-NEXT: v_or_b32_e32 v22, v25, v31
+; SDAG-NEXT: v_or_b32_e32 v24, v24, v30
; SDAG-NEXT: v_addc_u32_e32 v48, vcc, -1, v14, vcc
; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v34
; SDAG-NEXT: v_cndmask_b32_e64 v22, v50, v22, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v26, v49, v26, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v24, v49, v24, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v31, 0, v29, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v30, 0, v28, s[4:5]
; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v15, vcc
; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v34
-; SDAG-NEXT: v_cndmask_b32_e32 v29, v22, v5, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v28, v26, v4, vcc
-; SDAG-NEXT: v_mov_b32_e32 v26, 0
-; SDAG-NEXT: v_mov_b32_e32 v27, 0
+; SDAG-NEXT: v_cndmask_b32_e32 v25, v22, v5, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v24, v24, v4, vcc
+; SDAG-NEXT: v_mov_b32_e32 v28, 0
+; SDAG-NEXT: v_mov_b32_e32 v29, 0
; SDAG-NEXT: .LBB5_9: ; %udiv-do-while
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; SDAG-NEXT: v_lshl_b64 v[30:31], v[30:31], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v29
-; SDAG-NEXT: v_lshl_b64 v[28:29], v[28:29], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v50, 31, v19
+; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v19
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v50, 31, v25
+; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v51, 31, v21
; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
-; SDAG-NEXT: v_or_b32_e32 v22, v30, v22
-; SDAG-NEXT: v_or_b32_e32 v28, v28, v50
-; SDAG-NEXT: v_or_b32_e32 v18, v18, v51
-; SDAG-NEXT: v_or_b32_e32 v19, v25, v19
-; SDAG-NEXT: v_or_b32_e32 v21, v27, v21
-; SDAG-NEXT: v_sub_i32_e32 v27, vcc, v38, v28
-; SDAG-NEXT: v_or_b32_e32 v18, v24, v18
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v39, v29, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v48, v22, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v49, v31, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v27, 31, v27
-; SDAG-NEXT: v_and_b32_e32 v30, v27, v12
-; SDAG-NEXT: v_and_b32_e32 v50, v27, v13
-; SDAG-NEXT: v_and_b32_e32 v51, v27, v14
-; SDAG-NEXT: v_and_b32_e32 v52, v27, v15
-; SDAG-NEXT: v_sub_i32_e32 v28, vcc, v28, v30
-; SDAG-NEXT: v_subb_u32_e32 v29, vcc, v29, v50, vcc
-; SDAG-NEXT: v_subb_u32_e32 v30, vcc, v22, v51, vcc
-; SDAG-NEXT: v_subb_u32_e32 v31, vcc, v31, v52, vcc
+; SDAG-NEXT: v_or_b32_e32 v19, v27, v19
+; SDAG-NEXT: v_or_b32_e32 v18, v26, v18
+; SDAG-NEXT: v_or_b32_e32 v26, v30, v50
+; SDAG-NEXT: v_or_b32_e32 v24, v24, v51
+; SDAG-NEXT: v_or_b32_e32 v20, v20, v22
+; SDAG-NEXT: v_or_b32_e32 v21, v29, v21
+; SDAG-NEXT: v_or_b32_e32 v20, v28, v20
+; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v38, v24
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v39, v25, vcc
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v48, v26, vcc
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v49, v31, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v27, 31, v22
+; SDAG-NEXT: v_and_b32_e32 v22, 1, v27
+; SDAG-NEXT: v_and_b32_e32 v28, v27, v15
+; SDAG-NEXT: v_and_b32_e32 v29, v27, v14
+; SDAG-NEXT: v_and_b32_e32 v30, v27, v13
+; SDAG-NEXT: v_and_b32_e32 v27, v27, v12
+; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v24, v27
+; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v30, vcc
+; SDAG-NEXT: v_subb_u32_e32 v30, vcc, v26, v29, vcc
+; SDAG-NEXT: v_subb_u32_e32 v31, vcc, v31, v28, vcc
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v34
; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc
; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v36, vcc
; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc
-; SDAG-NEXT: v_or_b32_e32 v50, v34, v36
-; SDAG-NEXT: v_or_b32_e32 v51, v35, v37
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[50:51]
-; SDAG-NEXT: v_and_b32_e32 v22, 1, v27
+; SDAG-NEXT: v_or_b32_e32 v27, v35, v37
+; SDAG-NEXT: v_or_b32_e32 v26, v34, v36
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[26:27]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v20, v26, v20
+; SDAG-NEXT: v_mov_b32_e32 v28, 0
+; SDAG-NEXT: v_mov_b32_e32 v29, 0
; SDAG-NEXT: v_mov_b32_e32 v27, v23
; SDAG-NEXT: v_mov_b32_e32 v26, v22
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
@@ -2864,58 +2877,58 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
; SDAG-NEXT: .LBB5_11: ; %Flow11
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
-; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v21
; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
-; SDAG-NEXT: v_or_b32_e32 v18, v18, v24
-; SDAG-NEXT: v_or_b32_e32 v24, v23, v21
-; SDAG-NEXT: v_or_b32_e32 v25, v22, v20
+; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v19
+; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; SDAG-NEXT: v_or_b32_e32 v20, v20, v24
+; SDAG-NEXT: v_or_b32_e32 v24, v23, v19
+; SDAG-NEXT: v_or_b32_e32 v25, v22, v18
; SDAG-NEXT: .LBB5_12: ; %Flow12
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
-; SDAG-NEXT: v_mul_lo_u32 v23, v33, v11
-; SDAG-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v33, v10, 0
-; SDAG-NEXT: v_mul_lo_u32 v28, v32, v10
-; SDAG-NEXT: v_mul_lo_u32 v29, v17, v8
-; SDAG-NEXT: v_mul_lo_u32 v30, v16, v9
-; SDAG-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v8, v33, 0
-; SDAG-NEXT: v_mov_b32_e32 v22, 0
-; SDAG-NEXT: v_mul_lo_u32 v17, v25, v15
+; SDAG-NEXT: v_mul_lo_u32 v26, v33, v11
+; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v33, v10, 0
+; SDAG-NEXT: v_mul_lo_u32 v27, v32, v10
+; SDAG-NEXT: v_mul_lo_u32 v28, v17, v8
+; SDAG-NEXT: v_mul_lo_u32 v29, v16, v9
+; SDAG-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v8, v33, 0
+; SDAG-NEXT: v_mov_b32_e32 v19, 0
+; SDAG-NEXT: v_mul_lo_u32 v30, v25, v15
; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v25, v14, 0
; SDAG-NEXT: v_mul_lo_u32 v31, v24, v14
-; SDAG-NEXT: v_mul_lo_u32 v34, v19, v12
-; SDAG-NEXT: v_mul_lo_u32 v35, v18, v13
-; SDAG-NEXT: v_add_i32_e32 v19, vcc, v27, v23
-; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v9, v33, v[21:22]
-; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v20
-; SDAG-NEXT: v_add_i32_e64 v11, s[4:5], v11, v17
-; SDAG-NEXT: v_add_i32_e64 v27, s[4:5], v19, v28
-; SDAG-NEXT: v_mov_b32_e32 v21, v14
-; SDAG-NEXT: v_mad_u64_u32 v[19:20], s[4:5], v8, v32, v[21:22]
+; SDAG-NEXT: v_mul_lo_u32 v34, v21, v12
+; SDAG-NEXT: v_mul_lo_u32 v35, v20, v13
+; SDAG-NEXT: v_add_i32_e32 v21, vcc, v23, v26
+; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v9, v33, v[18:19]
+; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v17
+; SDAG-NEXT: v_add_i32_e64 v11, s[4:5], v11, v30
+; SDAG-NEXT: v_add_i32_e64 v23, s[4:5], v21, v27
+; SDAG-NEXT: v_mov_b32_e32 v18, v14
+; SDAG-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v8, v32, v[18:19]
; SDAG-NEXT: v_add_i32_e64 v11, s[4:5], v11, v31
-; SDAG-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v16, v8, v[26:27]
-; SDAG-NEXT: v_add_i32_e64 v14, s[4:5], v15, v20
+; SDAG-NEXT: v_mad_u64_u32 v[21:22], s[4:5], v16, v8, v[22:23]
+; SDAG-NEXT: v_add_i32_e64 v14, s[4:5], v15, v18
; SDAG-NEXT: v_addc_u32_e64 v15, s[4:5], 0, 0, s[4:5]
-; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v19, vcc
-; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v18, v12, v[10:11]
-; SDAG-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v12, v25, 0
-; SDAG-NEXT: v_add_i32_e64 v17, s[4:5], v29, v17
+; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v17, vcc
+; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v20, v12, v[10:11]
+; SDAG-NEXT: v_mad_u64_u32 v[17:18], s[4:5], v12, v25, 0
+; SDAG-NEXT: v_add_i32_e64 v16, s[4:5], v28, v22
; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v9, v32, v[14:15]
; SDAG-NEXT: v_add_i32_e64 v11, s[4:5], v34, v11
-; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v13, v25, v[21:22]
-; SDAG-NEXT: v_add_i32_e64 v17, s[4:5], v30, v17
-; SDAG-NEXT: v_add_i32_e64 v18, s[4:5], v35, v11
-; SDAG-NEXT: v_mov_b32_e32 v21, v14
-; SDAG-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v12, v24, v[21:22]
-; SDAG-NEXT: v_add_i32_e64 v8, s[4:5], v8, v16
-; SDAG-NEXT: v_addc_u32_e64 v14, s[4:5], v9, v17, s[4:5]
+; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v13, v25, v[18:19]
+; SDAG-NEXT: v_add_i32_e64 v16, s[4:5], v29, v16
+; SDAG-NEXT: v_add_i32_e64 v20, s[4:5], v35, v11
+; SDAG-NEXT: v_mov_b32_e32 v18, v14
+; SDAG-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v12, v24, v[18:19]
+; SDAG-NEXT: v_add_i32_e64 v8, s[4:5], v8, v21
+; SDAG-NEXT: v_addc_u32_e64 v14, s[4:5], v9, v16, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v8, vcc
; SDAG-NEXT: v_add_i32_e64 v8, s[4:5], v15, v12
; SDAG-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v14, vcc
; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v24, v[8:9]
; SDAG-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v9, v18, vcc
-; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v20
+; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v9, v20, vcc
+; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v17
; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v11, vcc
; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v8, vcc
; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 6737e2ce3c72c..f9db6aa6b73be 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -2802,29 +2802,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,25 +2833,26 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
@@ -2898,29 +2899,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB18_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -2928,22 +2929,23 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB18_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB18_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3033,90 +3035,95 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB18_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB18_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB18_6
+; GFX908-NEXT: .LBB18_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB18_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB18_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB18_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB18_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB18_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB18_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB18_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB18_2
+; GFX908-NEXT: .LBB18_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB18_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB18_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB18_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB18_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB18_6
@@ -3124,17 +3131,18 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -3192,7 +3200,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3213,6 +3220,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3239,6 +3247,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB19_2
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
@@ -3295,7 +3304,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3313,6 +3321,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3339,6 +3348,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_cbranch_execz .LBB19_2
; GFX11-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX11-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3436,7 +3446,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_add_co_u32_e32 v4, vcc, 0x7f8, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
@@ -3453,6 +3462,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3476,6 +3486,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_cbranch_execz .LBB19_2
; GFX908-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
@@ -3491,7 +3502,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7f8, v0
@@ -3513,6 +3523,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_load_dword v1, v[0:1]
; GFX8-NEXT: flat_load_dword v0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3536,6 +3547,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_cbranch_execz .LBB19_2
; GFX8-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
; GFX8-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
@@ -3604,7 +3616,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3625,6 +3636,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3651,6 +3663,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB20_2
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
@@ -3708,7 +3721,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3726,6 +3738,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3752,6 +3765,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_cbranch_execz .LBB20_2
; GFX11-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX11-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3849,7 +3863,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_add_co_u32_e32 v4, vcc, 0xfffff800, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_addc_co_u32_e32 v5, vcc, -1, v1, vcc
@@ -3866,6 +3879,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3889,6 +3903,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_cbranch_execz .LBB20_2
; GFX908-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
@@ -3904,7 +3919,6 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0xfffff800, v0
@@ -3926,6 +3940,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_load_dword v1, v[0:1]
; GFX8-NEXT: flat_load_dword v0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3949,6 +3964,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_cbranch_execz .LBB20_2
; GFX8-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
; GFX8-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
@@ -4017,7 +4033,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4034,6 +4049,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4055,19 +4071,20 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4113,7 +4130,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-LABEL: flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
@@ -4127,6 +4143,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4148,18 +4165,19 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB21_2
; GFX11-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[6:7]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -4245,7 +4263,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-LABEL: flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -4259,6 +4276,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4277,19 +4295,20 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB21_2
; GFX908-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[6:7]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -4297,7 +4316,6 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-LABEL: flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
@@ -4312,10 +4330,11 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v5, v[2:3]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4334,20 +4353,21 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB21_2
; GFX8-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[6:7]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4423,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4441,21 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4463,21 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4504,13 +4525,12 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB22_3
; GFX11-NEXT: ; %bb.1: ; %Flow2
@@ -4520,40 +4540,42 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: s_cbranch_execnz .LBB22_4
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB22_2
; GFX11-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -4643,11 +4665,10 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX908-NEXT: v_add_co_u32_e32 v6, vcc, 0x7f8, v0
+; GFX908-NEXT: v_add_co_u32_e32 v0, vcc, 0x7f8, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v7
+; GFX908-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX908-NEXT: s_cbranch_execnz .LBB22_3
@@ -4658,38 +4679,40 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[6:7]
+; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX908-NEXT: v_mov_b32_e32 v3, v1
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX908-NEXT: v_mov_b32_e32 v5, v3
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX908-NEXT: v_mov_b32_e32 v2, v0
+; GFX908-NEXT: v_mov_b32_e32 v4, v2
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX908-NEXT: s_cbranch_execnz .LBB22_4
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB22_2
; GFX908-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -4697,13 +4720,12 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7f8, v0
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x7f8, v0
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v7
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execnz .LBB22_3
@@ -4714,42 +4736,44 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v6
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: flat_load_dword v2, v[6:7]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB22_4
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB22_2
; GFX8-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4832,13 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4850,21 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4872,21 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4910,13 +4935,12 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB23_3
; GFX11-NEXT: ; %bb.1: ; %Flow2
@@ -4926,40 +4950,42 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: s_cbranch_execnz .LBB23_4
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB23_2
; GFX11-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -5049,11 +5075,10 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX908-NEXT: v_add_co_u32_e32 v6, vcc, 0xfffff800, v0
+; GFX908-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_addc_co_u32_e32 v7, vcc, -1, v1, vcc
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v7
+; GFX908-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX908-NEXT: s_cbranch_execnz .LBB23_3
@@ -5064,38 +5089,40 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[6:7]
+; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX908-NEXT: v_mov_b32_e32 v3, v1
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX908-NEXT: v_mov_b32_e32 v5, v3
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX908-NEXT: v_mov_b32_e32 v2, v0
+; GFX908-NEXT: v_mov_b32_e32 v4, v2
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX908-NEXT: s_cbranch_execnz .LBB23_4
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB23_2
; GFX908-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -5103,13 +5130,12 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0xfffff800, v0
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0xfffff800, v0
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v7
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execnz .LBB23_3
@@ -5120,42 +5146,44 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v6
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: flat_load_dword v2, v[6:7]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB23_4
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB23_2
; GFX8-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5242,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,25 +5273,26 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
@@ -5310,29 +5339,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX11-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -5340,76 +5369,82 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB24_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s5, v1
+; GFX10-NEXT: v_mov_b32_e32 v4, v0
+; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s5, v5
; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX10-NEXT: s_cbranch_execz .LBB24_4
-; GFX10-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX10-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX10-NEXT: s_cbranch_execnz .LBB24_3
+; GFX10-NEXT: ; %bb.1: ; %Flow2
+; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
+; GFX10-NEXT: s_cbranch_execnz .LBB24_6
+; GFX10-NEXT: .LBB24_2: ; %atomicrmw.phi
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10-NEXT: .LBB24_3: ; %atomicrmw.global
+; GFX10-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX10-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX10-NEXT: s_mov_b32 s5, 0
-; GFX10-NEXT: .LBB24_2: ; %atomicrmw.start
+; GFX10-NEXT: .LBB24_4: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_mov_b32_e32 v8, v2
-; GFX10-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v9, v1
+; GFX10-NEXT: v_mov_b32_e32 v8, v0
+; GFX10-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX10-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX10-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: s_cbranch_execnz .LBB24_2
-; GFX10-NEXT: ; %bb.3: ; %Flow
+; GFX10-NEXT: s_cbranch_execnz .LBB24_4
+; GFX10-NEXT: ; %bb.5: ; %Flow
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: .LBB24_4: ; %Flow2
+; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
-; GFX10-NEXT: s_cbranch_execz .LBB24_6
-; GFX10-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
+; GFX10-NEXT: s_cbranch_execz .LBB24_2
+; GFX10-NEXT: .LBB24_6: ; %atomicrmw.private
+; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX10-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX10-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX10-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: .LBB24_6: ; %atomicrmw.phi
+; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: v_mov_b32_e32 v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
@@ -5417,138 +5452,144 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX90A-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
-; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB24_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX90A-NEXT: flat_load_dwordx2 v[6:7], v[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], 0
+; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX90A-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
-; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[6:7]
-; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
+; GFX90A-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX90A-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
+; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_wbinvl1
-; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX90A-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX90A-NEXT: s_cbranch_execnz .LBB24_2
; GFX90A-NEXT: ; %bb.3: ; %Flow
; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: .LBB24_4: ; %Flow2
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB24_6
; GFX90A-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v5, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX90A-NEXT: v_max_f64 v[0:1], v[0:1], v[6:7]
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX90A-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
+; GFX90A-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: v_mov_b32_e32 v0, v2
-; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: v_mov_b32_e32 v0, v4
+; GFX90A-NEXT: v_mov_b32_e32 v1, v5
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX908-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB24_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB24_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB24_6
+; GFX908-NEXT: .LBB24_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB24_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB24_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB24_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB24_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB24_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB24_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB24_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB24_2
+; GFX908-NEXT: .LBB24_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB24_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB24_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB24_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB24_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB24_6
@@ -5556,17 +5597,18 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -5575,37 +5617,37 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX7-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX7-NEXT: s_cbranch_execz .LBB24_4
; GFX7-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX7-NEXT: v_add_i32_e32 v2, vcc, 4, v0
-; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX7-NEXT: flat_load_dword v3, v[2:3]
-; GFX7-NEXT: flat_load_dword v2, v[0:1]
+; GFX7-NEXT: v_add_i32_e32 v4, vcc, 4, v0
+; GFX7-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX7-NEXT: flat_load_dword v5, v[4:5]
+; GFX7-NEXT: flat_load_dword v4, v[0:1]
+; GFX7-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX7-NEXT: s_mov_b64 s[6:7], 0
; GFX7-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v9, v3
-; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
+; GFX7-NEXT: v_mov_b32_e32 v6, v4
+; GFX7-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX7-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
+; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: buffer_wbinvl1
-; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX7-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX7-NEXT: s_cbranch_execnz .LBB24_2
; GFX7-NEXT: ; %bb.3: ; %Flow
; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX7-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX7-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX7-NEXT: .LBB24_4: ; %Flow2
; GFX7-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX7-NEXT: s_cbranch_execz .LBB24_6
@@ -5613,17 +5655,18 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX7-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX7-NEXT: v_add_i32_e32 v7, vcc, 4, v6
-; GFX7-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX7-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX7-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX7-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX7-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX7-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
; GFX7-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX7-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX7-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v0, v2
-; GFX7-NEXT: v_mov_b32_e32 v1, v3
+; GFX7-NEXT: v_mov_b32_e32 v0, v4
+; GFX7-NEXT: v_mov_b32_e32 v1, v5
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw fmax ptr %ptr, double %val syncscope("agent") seq_cst, !amdgpu.no.remote.memory !0
@@ -5638,29 +5681,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,25 +5712,26 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -5734,29 +5778,29 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX11-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB25_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -5764,22 +5808,23 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB25_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB25_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -5869,90 +5914,95 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX908-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB25_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB25_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB25_6
+; GFX908-NEXT: .LBB25_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB25_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB25_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB25_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB25_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB25_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB25_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB25_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB25_2
+; GFX908-NEXT: .LBB25_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB25_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB25_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_max_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB25_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB25_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB25_6
@@ -5960,17 +6010,18 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 61dd7bedfaee1..4a7ec48ef905b 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -2802,29 +2802,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2833,25 +2833,26 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB18_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
@@ -2898,29 +2899,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB18_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -2928,22 +2929,23 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB18_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB18_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
@@ -3033,90 +3035,95 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB18_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB18_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB18_6
+; GFX908-NEXT: .LBB18_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB18_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB18_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB18_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB18_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB18_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB18_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB18_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB18_2
+; GFX908-NEXT: .LBB18_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB18_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB18_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB18_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB18_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB18_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB18_6
@@ -3124,17 +3131,18 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB18_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -3192,7 +3200,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3213,6 +3220,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3239,6 +3247,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB19_2
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
@@ -3295,7 +3304,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
@@ -3313,6 +3321,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3339,6 +3348,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_cbranch_execz .LBB19_2
; GFX11-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX11-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3436,7 +3446,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_add_co_u32_e32 v4, vcc, 0x7f8, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
@@ -3453,6 +3462,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB19_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3476,6 +3486,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_cbranch_execz .LBB19_2
; GFX908-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
@@ -3491,7 +3502,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7f8, v0
@@ -3513,6 +3523,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_load_dword v1, v[0:1]
; GFX8-NEXT: flat_load_dword v0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB19_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3536,6 +3547,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_cbranch_execz .LBB19_2
; GFX8-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
; GFX8-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
@@ -3604,7 +3616,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3625,6 +3636,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3651,6 +3663,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB20_2
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
@@ -3708,7 +3721,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
@@ -3726,6 +3738,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[0:1], v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3752,6 +3765,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_cbranch_execz .LBB20_2
; GFX11-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX11-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3849,7 +3863,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_add_co_u32_e32 v4, vcc, 0xfffff800, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_addc_co_u32_e32 v5, vcc, -1, v1, vcc
@@ -3866,6 +3879,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB20_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3889,6 +3903,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_cbranch_execz .LBB20_2
; GFX908-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
@@ -3904,7 +3919,6 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0xfffff800, v0
@@ -3926,6 +3940,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_load_dword v1, v[0:1]
; GFX8-NEXT: flat_load_dword v0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB20_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3949,6 +3964,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_cbranch_execz .LBB20_2
; GFX8-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
; GFX8-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
@@ -4017,7 +4033,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4034,6 +4049,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4055,19 +4071,20 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4113,7 +4130,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-LABEL: flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
@@ -4127,6 +4143,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4148,18 +4165,19 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB21_2
; GFX11-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -4245,7 +4263,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-LABEL: flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -4259,6 +4276,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB21_3: ; %atomicrmw.global
; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4277,19 +4295,20 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB21_2
; GFX908-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -4297,7 +4316,6 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-LABEL: flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
@@ -4312,10 +4330,11 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB21_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v5, v[2:3]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB21_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4334,20 +4353,21 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB21_2
; GFX8-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4403,14 +4423,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4422,20 +4441,21 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4443,20 +4463,21 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4504,13 +4525,12 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB22_3
; GFX11-NEXT: ; %bb.1: ; %Flow2
@@ -4520,40 +4540,42 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: s_cbranch_execnz .LBB22_4
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB22_2
; GFX11-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -4643,11 +4665,10 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX908-NEXT: v_add_co_u32_e32 v6, vcc, 0x7f8, v0
+; GFX908-NEXT: v_add_co_u32_e32 v0, vcc, 0x7f8, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v7
+; GFX908-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX908-NEXT: s_cbranch_execnz .LBB22_3
@@ -4658,38 +4679,40 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[6:7]
+; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX908-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX908-NEXT: v_mov_b32_e32 v3, v1
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX908-NEXT: v_mov_b32_e32 v5, v3
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX908-NEXT: v_mov_b32_e32 v2, v0
+; GFX908-NEXT: v_mov_b32_e32 v4, v2
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX908-NEXT: s_cbranch_execnz .LBB22_4
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB22_2
; GFX908-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -4697,13 +4720,12 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7f8, v0
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x7f8, v0
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v7
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execnz .LBB22_3
@@ -4714,42 +4736,44 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB22_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v6
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: flat_load_dword v2, v[6:7]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB22_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB22_4
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB22_2
; GFX8-NEXT: .LBB22_6: ; %atomicrmw.private
-; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4808,14 +4832,13 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
-; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
@@ -4827,20 +4850,21 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
; GFX12-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4848,20 +4872,21 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX12-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4910,13 +4935,12 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v7
+; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execnz .LBB23_3
; GFX11-NEXT: ; %bb.1: ; %Flow2
@@ -4926,40 +4950,42 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[6:7]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[2:5] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: s_cbranch_execnz .LBB23_4
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB23_2
; GFX11-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[0:1], v2, off
+; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
+; GFX11-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -5049,11 +5075,10 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX908-NEXT: v_add_co_u32_e32 v6, vcc, 0xfffff800, v0
+; GFX908-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_addc_co_u32_e32 v7, vcc, -1, v1, vcc
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v7
+; GFX908-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX908-NEXT: s_cbranch_execnz .LBB23_3
@@ -5064,38 +5089,40 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_setpc_b64 s[30:31]
; GFX908-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[6:7]
+; GFX908-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX908-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
; GFX908-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX908-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX908-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX908-NEXT: v_mov_b32_e32 v3, v1
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX908-NEXT: v_mov_b32_e32 v5, v3
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX908-NEXT: v_mov_b32_e32 v2, v0
+; GFX908-NEXT: v_mov_b32_e32 v4, v2
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX908-NEXT: s_cbranch_execnz .LBB23_4
; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX908-NEXT: s_cbranch_execz .LBB23_2
; GFX908-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX908-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX908-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX908-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
+; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX908-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
@@ -5103,13 +5130,12 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-LABEL: flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_grained_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0xfffff800, v0
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0xfffff800, v0
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v7
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execnz .LBB23_3
@@ -5120,42 +5146,44 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: .LBB23_3: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v6
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: flat_load_dword v2, v[6:7]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB23_4: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB23_4
; GFX8-NEXT: ; %bb.5: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB23_2
; GFX8-NEXT: .LBB23_6: ; %atomicrmw.private
-; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
-; GFX8-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v4
+; GFX8-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
-; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
+; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
+; GFX8-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -5214,29 +5242,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5245,25 +5273,26 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB24_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
@@ -5310,29 +5339,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX11-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -5340,76 +5369,82 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB24_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s5, v1
+; GFX10-NEXT: v_mov_b32_e32 v4, v0
+; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s5, v5
; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo
; GFX10-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX10-NEXT: s_cbranch_execz .LBB24_4
-; GFX10-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX10-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX10-NEXT: s_cbranch_execnz .LBB24_3
+; GFX10-NEXT: ; %bb.1: ; %Flow2
+; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
+; GFX10-NEXT: s_cbranch_execnz .LBB24_6
+; GFX10-NEXT: .LBB24_2: ; %atomicrmw.phi
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10-NEXT: .LBB24_3: ; %atomicrmw.global
+; GFX10-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX10-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX10-NEXT: s_mov_b32 s5, 0
-; GFX10-NEXT: .LBB24_2: ; %atomicrmw.start
+; GFX10-NEXT: .LBB24_4: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_mov_b32_e32 v8, v2
-; GFX10-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v9, v1
+; GFX10-NEXT: v_mov_b32_e32 v8, v0
+; GFX10-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX10-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX10-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: s_cbranch_execnz .LBB24_2
-; GFX10-NEXT: ; %bb.3: ; %Flow
+; GFX10-NEXT: s_cbranch_execnz .LBB24_4
+; GFX10-NEXT: ; %bb.5: ; %Flow
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: .LBB24_4: ; %Flow2
+; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
-; GFX10-NEXT: s_cbranch_execz .LBB24_6
-; GFX10-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
+; GFX10-NEXT: s_cbranch_execz .LBB24_2
+; GFX10-NEXT: .LBB24_6: ; %atomicrmw.private
+; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX10-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX10-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX10-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: .LBB24_6: ; %atomicrmw.phi
+; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: v_mov_b32_e32 v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
@@ -5417,138 +5452,144 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX90A-NEXT: v_max_f64 v[6:7], v[2:3], v[2:3]
-; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB24_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
+; GFX90A-NEXT: flat_load_dwordx2 v[6:7], v[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], 0
+; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX90A-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
-; GFX90A-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
-; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc
+; GFX90A-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX90A-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
+; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_wbinvl1
-; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[4:5]
+; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX90A-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
-; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX90A-NEXT: s_cbranch_execnz .LBB24_2
; GFX90A-NEXT: ; %bb.3: ; %Flow
; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: .LBB24_4: ; %Flow2
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB24_6
; GFX90A-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
-; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
+; GFX90A-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v5, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX90A-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
-; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX90A-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX90A-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: v_mov_b32_e32 v0, v2
-; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: v_mov_b32_e32 v0, v4
+; GFX90A-NEXT: v_mov_b32_e32 v1, v5
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX908-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB24_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB24_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB24_6
+; GFX908-NEXT: .LBB24_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB24_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB24_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB24_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB24_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB24_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB24_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB24_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB24_2
+; GFX908-NEXT: .LBB24_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB24_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB24_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB24_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB24_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB24_6
@@ -5556,17 +5597,18 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -5575,37 +5617,37 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX7-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX7-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX7-NEXT: s_cbranch_execz .LBB24_4
; GFX7-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX7-NEXT: v_add_i32_e32 v2, vcc, 4, v0
-; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX7-NEXT: flat_load_dword v3, v[2:3]
-; GFX7-NEXT: flat_load_dword v2, v[0:1]
+; GFX7-NEXT: v_add_i32_e32 v4, vcc, 4, v0
+; GFX7-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX7-NEXT: flat_load_dword v5, v[4:5]
+; GFX7-NEXT: flat_load_dword v4, v[0:1]
+; GFX7-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX7-NEXT: s_mov_b64 s[6:7], 0
; GFX7-NEXT: .LBB24_2: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v9, v3
-; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
+; GFX7-NEXT: v_mov_b32_e32 v6, v4
+; GFX7-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX7-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
+; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: buffer_wbinvl1
-; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX7-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX7-NEXT: s_cbranch_execnz .LBB24_2
; GFX7-NEXT: ; %bb.3: ; %Flow
; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX7-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX7-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX7-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX7-NEXT: .LBB24_4: ; %Flow2
; GFX7-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX7-NEXT: s_cbranch_execz .LBB24_6
@@ -5613,17 +5655,18 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX7-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX7-NEXT: v_add_i32_e32 v7, vcc, 4, v6
-; GFX7-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX7-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX7-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX7-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX7-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX7-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
; GFX7-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX7-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX7-NEXT: .LBB24_6: ; %atomicrmw.phi
; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v0, v2
-; GFX7-NEXT: v_mov_b32_e32 v1, v3
+; GFX7-NEXT: v_mov_b32_e32 v0, v4
+; GFX7-NEXT: v_mov_b32_e32 v1, v5
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw fmin ptr %ptr, double %val syncscope("agent") seq_cst, !amdgpu.no.remote.memory !0
@@ -5638,29 +5681,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
; GFX12-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX12-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX12-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b32 s1, 0
; GFX12-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[8:9], v[8:9]
-; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[2:3], v[4:5]
+; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[6:7]
+; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[2:3]
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX12-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -5669,25 +5712,26 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; %bb.3: ; %Flow
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB25_4: ; %Flow2
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[2:3]
+; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -5734,29 +5778,29 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX11-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX11-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX11-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_cbranch_execz .LBB25_4
; GFX11-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX11-NEXT: flat_load_b64 v[2:3], v[0:1]
+; GFX11-NEXT: flat_load_b64 v[4:5], v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX11-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: flat_atomic_cmpswap_b64 v[2:3], v[0:1], v[6:9] glc
+; GFX11-NEXT: flat_atomic_cmpswap_b64 v[4:5], v[0:1], v[4:7] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
@@ -5764,22 +5808,23 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX11-NEXT: ; %bb.3: ; %Flow
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX11-NEXT: .LBB25_4: ; %Flow2
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB25_6
; GFX11-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
-; GFX11-NEXT: scratch_load_b64 v[2:3], v6, off
+; GFX11-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX11-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX11-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
@@ -5869,90 +5914,95 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX908-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX908: ; %bb.0:
; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
+; GFX908-NEXT: v_mov_b32_e32 v5, v1
; GFX908-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: v_mov_b32_e32 v4, v0
+; GFX908-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB25_4
-; GFX908-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX908-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GFX908-NEXT: s_cbranch_execnz .LBB25_3
+; GFX908-NEXT: ; %bb.1: ; %Flow2
+; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX908-NEXT: s_cbranch_execnz .LBB25_6
+; GFX908-NEXT: .LBB25_2: ; %atomicrmw.phi
+; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: s_setpc_b64 s[30:31]
+; GFX908-NEXT: .LBB25_3: ; %atomicrmw.global
+; GFX908-NEXT: flat_load_dwordx2 v[0:1], v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX908-NEXT: s_mov_b64 s[6:7], 0
-; GFX908-NEXT: .LBB25_2: ; %atomicrmw.start
+; GFX908-NEXT: .LBB25_4: ; %atomicrmw.start
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX908-NEXT: v_mov_b32_e32 v9, v3
-; GFX908-NEXT: v_mov_b32_e32 v8, v2
-; GFX908-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX908-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX908-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX908-NEXT: v_mov_b32_e32 v9, v1
+; GFX908-NEXT: v_mov_b32_e32 v8, v0
+; GFX908-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
+; GFX908-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
+; GFX908-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
-; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX908-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
; GFX908-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX908-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX908-NEXT: s_cbranch_execnz .LBB25_2
-; GFX908-NEXT: ; %bb.3: ; %Flow
+; GFX908-NEXT: s_cbranch_execnz .LBB25_4
+; GFX908-NEXT: ; %bb.5: ; %Flow
; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX908-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX908-NEXT: .LBB25_4: ; %Flow2
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB25_6
-; GFX908-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
-; GFX908-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
+; GFX908-NEXT: s_cbranch_execz .LBB25_2
+; GFX908-NEXT: .LBB25_6: ; %atomicrmw.private
+; GFX908-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX908-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX908-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX908-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX908-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
-; GFX908-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
-; GFX908-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX908-NEXT: .LBB25_6: ; %atomicrmw.phi
+; GFX908-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
+; GFX908-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX908-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
+; GFX908-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, v3
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[4:5], 0xc0
; GFX8-NEXT: s_load_dword s4, s[4:5], 0x0
-; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, s4, v1
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB25_4
; GFX8-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[2:3]
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_load_dword v5, v[4:5]
+; GFX8-NEXT: flat_load_dword v4, v[0:1]
+; GFX8-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX8-NEXT: s_mov_b64 s[6:7], 0
; GFX8-NEXT: .LBB25_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v3
-; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_max_f64 v[2:3], v[8:9], v[8:9]
-; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
-; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[6:7]
+; GFX8-NEXT: v_min_f64 v[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[8:9]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[4:5], v[6:7]
; GFX8-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX8-NEXT: s_andn2_b64 exec, exec, s[6:7]
; GFX8-NEXT: s_cbranch_execnz .LBB25_2
; GFX8-NEXT: ; %bb.3: ; %Flow
; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX8-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX8-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX8-NEXT: .LBB25_4: ; %Flow2
; GFX8-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX8-NEXT: s_cbranch_execz .LBB25_6
@@ -5960,17 +6010,18 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX8-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 4, v6
-; GFX8-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
-; GFX8-NEXT: buffer_load_dword v3, v7, s[0:3], 0 offen
-; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: buffer_load_dword v4, v6, s[0:3], 0 offen
+; GFX8-NEXT: buffer_load_dword v5, v7, s[0:3], 0 offen
; GFX8-NEXT: v_max_f64 v[0:1], v[2:3], v[2:3]
-; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
+; GFX8-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX8-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; GFX8-NEXT: .LBB25_6: ; %atomicrmw.phi
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v1, v3
+; GFX8-NEXT: v_mov_b32_e32 v0, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
index c6340ef5b6c0c..299150e8fb0aa 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
@@ -451,52 +451,52 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, -1, v4
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GISEL-NEXT: v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_lshlrev_b16_e32 v2, 1, v0
-; GISEL-NEXT: v_or_b32_e32 v1, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_lshlrev_b16_e32 v3, 2, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
+; GISEL-NEXT: v_lshlrev_b16_e32 v5, 3, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v7, 4, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v8, 5, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v9, 6, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v10, 7, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v11, 8, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v12, 9, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v13, 10, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v14, 11, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v15, 12, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v16, 13, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v17, 14, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v18, 15, v0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GISEL-NEXT: v_or_b32_e32 v1, v1, v2
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v3
; GISEL-NEXT: v_or_b32_e32 v1, v1, v3
-; GISEL-NEXT: v_lshlrev_b16_e32 v7, 3, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v3
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v5
+; GISEL-NEXT: v_or_b32_e32 v1, v1, v5
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v7
; GISEL-NEXT: v_or_b32_e32 v1, v1, v7
-; GISEL-NEXT: v_lshlrev_b16_e32 v8, 4, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v7
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v8
; GISEL-NEXT: v_or_b32_e32 v1, v1, v8
-; GISEL-NEXT: v_lshlrev_b16_e32 v9, 5, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v8
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v9
; GISEL-NEXT: v_or_b32_e32 v1, v1, v9
-; GISEL-NEXT: v_lshlrev_b16_e32 v10, 6, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v9
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v10
; GISEL-NEXT: v_or_b32_e32 v1, v1, v10
-; GISEL-NEXT: v_lshlrev_b16_e32 v11, 7, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v10
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v11
; GISEL-NEXT: v_or_b32_e32 v1, v1, v11
-; GISEL-NEXT: v_lshlrev_b16_e32 v12, 8, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v11
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v12
; GISEL-NEXT: v_or_b32_e32 v1, v1, v12
-; GISEL-NEXT: v_lshlrev_b16_e32 v13, 9, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v12
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v13
; GISEL-NEXT: v_or_b32_e32 v1, v1, v13
-; GISEL-NEXT: v_lshlrev_b16_e32 v14, 10, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v13
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v14
; GISEL-NEXT: v_or_b32_e32 v1, v1, v14
-; GISEL-NEXT: v_lshlrev_b16_e32 v15, 11, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v14
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v15
; GISEL-NEXT: v_or_b32_e32 v1, v1, v15
-; GISEL-NEXT: v_lshlrev_b16_e32 v16, 12, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v15
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v16
; GISEL-NEXT: v_or_b32_e32 v1, v1, v16
-; GISEL-NEXT: v_lshlrev_b16_e32 v17, 13, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v16
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v17
; GISEL-NEXT: v_or_b32_e32 v1, v1, v17
-; GISEL-NEXT: v_lshlrev_b16_e32 v18, 14, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v17
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v18
; GISEL-NEXT: v_or_b32_e32 v1, v1, v18
-; GISEL-NEXT: v_lshlrev_b16_e32 v0, 15, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v18
-; GISEL-NEXT: v_or_b32_e32 v1, v1, v0
-; GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v0
@@ -507,7 +507,6 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GISEL-NEXT: v_and_or_b32 v4, v4, v0, v1
; GISEL-NEXT: v_mov_b32_e32 v0, 0x96
-; GISEL-NEXT: v_mov_b32_e32 v5, 0
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -515,6 +514,7 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL-NEXT: s_cbranch_execz .LBB2_3
; GISEL-NEXT: ; %bb.2: ; %fp-to-i-if-exp.large
; GISEL-NEXT: v_add_u32_e32 v14, 0xffffff6a, v6
+; GISEL-NEXT: v_mov_b32_e32 v5, 0
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v14, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GISEL-NEXT: v_sub_u32_e32 v2, 64, v14
@@ -807,10 +807,10 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
; GISEL: ; %bb.0: ; %fp-to-i-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
-; GISEL-NEXT: v_lshrrev_b16_e32 v6, 7, v4
+; GISEL-NEXT: v_lshrrev_b16_e32 v5, 7, v4
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7f
; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v6, v0 src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v5, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
@@ -822,108 +822,108 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
; GISEL-NEXT: v_cmp_ge_i16_e32 vcc, -1, v4
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GISEL-NEXT: v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_lshlrev_b16_e32 v2, 1, v0
-; GISEL-NEXT: v_or_b32_e32 v1, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_lshlrev_b16_e32 v3, 2, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
+; GISEL-NEXT: v_lshlrev_b16_e32 v6, 3, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v7, 4, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v8, 5, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v9, 6, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v10, 7, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v11, 8, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v12, 9, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v13, 10, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v14, 11, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v15, 12, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v16, 13, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v17, 14, v0
+; GISEL-NEXT: v_lshlrev_b16_e32 v18, 15, v0
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GISEL-NEXT: v_or_b32_e32 v1, v1, v2
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v3
; GISEL-NEXT: v_or_b32_e32 v1, v1, v3
-; GISEL-NEXT: v_lshlrev_b16_e32 v7, 3, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v3
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v6
+; GISEL-NEXT: v_or_b32_e32 v1, v1, v6
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v7
; GISEL-NEXT: v_or_b32_e32 v1, v1, v7
-; GISEL-NEXT: v_lshlrev_b16_e32 v8, 4, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v7
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v8
; GISEL-NEXT: v_or_b32_e32 v1, v1, v8
-; GISEL-NEXT: v_lshlrev_b16_e32 v9, 5, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v8
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v9
; GISEL-NEXT: v_or_b32_e32 v1, v1, v9
-; GISEL-NEXT: v_lshlrev_b16_e32 v10, 6, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v9
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v10
; GISEL-NEXT: v_or_b32_e32 v1, v1, v10
-; GISEL-NEXT: v_lshlrev_b16_e32 v11, 7, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v10
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v11
; GISEL-NEXT: v_or_b32_e32 v1, v1, v11
-; GISEL-NEXT: v_lshlrev_b16_e32 v12, 8, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v11
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v12
; GISEL-NEXT: v_or_b32_e32 v1, v1, v12
-; GISEL-NEXT: v_lshlrev_b16_e32 v13, 9, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v12
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v13
; GISEL-NEXT: v_or_b32_e32 v1, v1, v13
-; GISEL-NEXT: v_lshlrev_b16_e32 v14, 10, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v13
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v14
; GISEL-NEXT: v_or_b32_e32 v1, v1, v14
-; GISEL-NEXT: v_lshlrev_b16_e32 v15, 11, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v14
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v15
; GISEL-NEXT: v_or_b32_e32 v1, v1, v15
-; GISEL-NEXT: v_lshlrev_b16_e32 v16, 12, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v15
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v16
; GISEL-NEXT: v_or_b32_e32 v1, v1, v16
-; GISEL-NEXT: v_lshlrev_b16_e32 v17, 13, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v16
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v17
; GISEL-NEXT: v_or_b32_e32 v1, v1, v17
-; GISEL-NEXT: v_lshlrev_b16_e32 v18, 14, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v17
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v18
; GISEL-NEXT: v_or_b32_e32 v1, v1, v18
-; GISEL-NEXT: v_lshlrev_b16_e32 v0, 15, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v18
-; GISEL-NEXT: v_or_b32_e32 v1, v1, v0
-; GISEL-NEXT: v_or_b32_e32 v0, v2, v0
-; GISEL-NEXT: v_and_b32_e32 v9, 0xffff, v0
+; GISEL-NEXT: v_and_b32_e32 v8, 0xffff, v0
; GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v9
-; GISEL-NEXT: v_or3_b32 v7, v1, v0, 1
-; GISEL-NEXT: v_or3_b32 v8, v9, v0, 0
+; GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v8
+; GISEL-NEXT: v_or3_b32 v6, v1, v0, 1
+; GISEL-NEXT: v_or3_b32 v7, v8, v0, 0
; GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v4
; GISEL-NEXT: v_or_b32_e32 v4, 0x80, v0
; GISEL-NEXT: v_mov_b32_e32 v0, 0x86
-; GISEL-NEXT: v_mov_b32_e32 v5, 0
-; GISEL-NEXT: v_cmp_ge_u16_sdwa s[4:5], v6, v0 src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-NEXT: v_cmp_ge_u16_sdwa s[4:5], v5, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[6:7]
; GISEL-NEXT: s_cbranch_execz .LBB6_3
; GISEL-NEXT: ; %bb.2: ; %fp-to-i-if-exp.large
; GISEL-NEXT: v_mov_b32_e32 v0, 0xffffff7a
-; GISEL-NEXT: v_add_u16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], v6, v[4:5]
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GISEL-NEXT: v_lshl_or_b32 v13, v9, 16, v9
-; GISEL-NEXT: v_sub_u32_e32 v2, 64, v6
-; GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v2, v[4:5]
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v13, 0
-; GISEL-NEXT: v_add_u32_e32 v11, 0xffffffc0, v6
-; GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v1, vcc
-; GISEL-NEXT: v_lshlrev_b64 v[4:5], v11, v[4:5]
-; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v15, v8, v[2:3]
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v9, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GISEL-NEXT: v_add_u16_sdwa v15, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v4
+; GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-NEXT: v_lshlrev_b64 v[2:3], v15, v[0:1]
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; GISEL-NEXT: v_lshl_or_b32 v14, v8, 16, v8
+; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v2, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v16, v14, 0
+; GISEL-NEXT: v_add_u32_e32 v10, 0xffffffc0, v15
+; GISEL-NEXT: v_sub_u32_e32 v4, 64, v15
+; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v3, vcc
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]
+; GISEL-NEXT: v_lshlrev_b64 v[10:11], v10, v[0:1]
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v17, v7, v[8:9]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v4, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
; GISEL-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v14, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v7, v[11:12]
-; GISEL-NEXT: v_mul_lo_u32 v9, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v6, v15, v13
-; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v14, v8, v[1:2]
-; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v15, v7, v[11:12]
-; GISEL-NEXT: v_addc_co_u32_e64 v3, s[8:9], v3, v9, s[8:9]
-; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v6, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v4, v8, v[3:4]
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v10, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v16, v6, 0
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v6, v[12:13]
+; GISEL-NEXT: v_mul_lo_u32 v12, v16, v14
+; GISEL-NEXT: v_mul_lo_u32 v10, v17, v14
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v16, v7, v[1:2]
+; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v17, v6, v[8:9]
+; GISEL-NEXT: v_addc_co_u32_e64 v3, s[8:9], v3, v12, s[8:9]
+; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v10, s[6:7]
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v4, v7, v[3:4]
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v5, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[4:5]
-; GISEL-NEXT: ; implicit-def: $vgpr6
-; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v7, v[11:12]
+; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v5, v6, v[8:9]
+; GISEL-NEXT: ; implicit-def: $vgpr5
; GISEL-NEXT: ; implicit-def: $vgpr4
-; GISEL-NEXT: ; implicit-def: $vgpr7
+; GISEL-NEXT: ; implicit-def: $vgpr6
; GISEL-NEXT: .LBB6_3: ; %Flow
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[12:13]
; GISEL-NEXT: ; %bb.4: ; %fp-to-i-if-exp.small
; GISEL-NEXT: v_mov_b32_e32 v0, 0x86
-; GISEL-NEXT: v_sub_u16_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GISEL-NEXT: v_sub_u16_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GISEL-NEXT: v_lshrrev_b16_e32 v0, v0, v4
-; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v7
+; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v6
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GISEL-NEXT: v_mul_i32_i24_e32 v0, v0, v7
+; GISEL-NEXT: v_mul_i32_i24_e32 v0, v0, v6
; GISEL-NEXT: v_mov_b32_e32 v3, v2
; GISEL-NEXT: ; %bb.5: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
index 8284bb5d9e99b..d0f0fec8363d9 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
@@ -6750,19 +6750,19 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -6844,15 +6844,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -6928,16 +6928,16 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB10_2: ; %atomicrmw.start
@@ -7014,12 +7014,12 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -7027,6 +7027,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -7103,15 +7104,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB10_2: ; %atomicrmw.start
@@ -8191,19 +8192,19 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -8285,15 +8286,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -8369,16 +8370,16 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB12_2: ; %atomicrmw.start
@@ -8455,12 +8456,12 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -8468,6 +8469,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -8544,15 +8546,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB12_2: ; %atomicrmw.start
@@ -9632,19 +9634,19 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -9726,15 +9728,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -9810,16 +9812,16 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB14_2: ; %atomicrmw.start
@@ -9896,12 +9898,12 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -9909,6 +9911,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -9985,15 +9988,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB14_2: ; %atomicrmw.start
@@ -10555,19 +10558,19 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -10649,15 +10652,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -10733,16 +10736,16 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB15_2: ; %atomicrmw.start
@@ -10819,12 +10822,12 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -10832,6 +10835,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -10908,15 +10912,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB15_2: ; %atomicrmw.start
@@ -11996,19 +12000,19 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -12090,15 +12094,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -12174,16 +12178,16 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB17_2: ; %atomicrmw.start
@@ -12260,12 +12264,12 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -12273,6 +12277,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -12349,15 +12354,15 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB17_2: ; %atomicrmw.start
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index c0aa29126ae4a..b95d23e109103 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -4037,19 +4037,19 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -4141,15 +4141,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB7_2:
@@ -4218,15 +4218,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB7_2:
@@ -4301,12 +4301,12 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_max_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -4314,7 +4314,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -4399,15 +4399,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -5314,19 +5314,19 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -5418,15 +5418,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1064-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB9_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB9_2:
@@ -5495,15 +5495,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB9_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB9_2:
@@ -5578,12 +5578,12 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_max_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5591,7 +5591,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -5676,15 +5676,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -6591,19 +6591,19 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -6695,15 +6695,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1064-DPP-NEXT: v_max_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB11_2:
@@ -6772,15 +6772,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmax_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB11_2:
@@ -6855,12 +6855,12 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_max_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -6868,7 +6868,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -6953,15 +6953,15 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index 053e4f619853b..84216564b66cf 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -4037,19 +4037,19 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -4141,15 +4141,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB7_2:
@@ -4218,15 +4218,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_min_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB7_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB7_2:
@@ -4301,12 +4301,12 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -4314,7 +4314,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -4399,15 +4399,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB7_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -5314,19 +5314,19 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -5418,15 +5418,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1064-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB9_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB9_2:
@@ -5495,15 +5495,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_min_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB9_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB9_2:
@@ -5578,12 +5578,12 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5591,7 +5591,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -5676,15 +5676,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -6591,19 +6591,19 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: v_max_f64 v[3:4], v[3:4], v[3:4]
; GFX9-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -6695,15 +6695,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1064-DPP-NEXT: v_min_f64 v[3:4], v[5:6], v[3:4]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1064-DPP-NEXT: .LBB11_2:
@@ -6772,15 +6772,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1032-DPP-NEXT: v_max_f64 v[5:6], v[5:6], v[5:6]
; GFX1032-DPP-NEXT: v_min_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB11_2
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_atomic_fmin_x2 v2, v[0:1], s[0:1]
; GFX1032-DPP-NEXT: .LBB11_2:
@@ -6855,12 +6855,12 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
; GFX1164-DPP-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -6868,7 +6868,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
-; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
@@ -6953,15 +6953,15 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB11_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
index 23515ffcfb139..04fbb5443ba22 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
@@ -7078,19 +7078,19 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -7172,15 +7172,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -7256,16 +7256,16 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB10_2: ; %atomicrmw.start
@@ -7342,12 +7342,12 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -7355,6 +7355,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -7431,15 +7432,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB10_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB10_2: ; %atomicrmw.start
@@ -8518,19 +8519,19 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -8612,15 +8613,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -8696,16 +8697,16 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB12_2: ; %atomicrmw.start
@@ -8782,12 +8783,12 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -8795,6 +8796,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -8871,15 +8873,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB12_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB12_2: ; %atomicrmw.start
@@ -9959,19 +9961,19 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -10053,15 +10055,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -10137,16 +10139,16 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB14_2: ; %atomicrmw.start
@@ -10223,12 +10225,12 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -10236,6 +10238,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -10312,15 +10315,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB14_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB14_2: ; %atomicrmw.start
@@ -10882,19 +10885,19 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -10976,15 +10979,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -11060,16 +11063,16 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB15_2: ; %atomicrmw.start
@@ -11146,12 +11149,12 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -11159,6 +11162,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -11235,15 +11239,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB15_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB15_2: ; %atomicrmw.start
@@ -12322,19 +12326,19 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: v_mov_b32_dpp v3, v5 row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-DPP-NEXT: v_add_f64 v[3:4], v[5:6], v[3:4]
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX9-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX9-DPP-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
; GFX9-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX9-DPP-NEXT: v_readlane_b32 s3, v4, 63
; GFX9-DPP-NEXT: v_readlane_b32 s2, v3, 63
; GFX9-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[2:3]
-; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-DPP-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX9-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_load_dwordx2 s[2:3], s[34:35], 0x24
+; GFX9-DPP-NEXT: v_mov_b32_e32 v0, 0
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], 0
; GFX9-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DPP-NEXT: global_load_dwordx2 v[11:12], v0, s[2:3]
@@ -12416,15 +12420,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1064-DPP-NEXT: v_add_f64 v[3:4], s[2:3], s[4:5]
; GFX1064-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1064-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v1, v4
-; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1064-DPP-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v0
; GFX1064-DPP-NEXT: v_mov_b32_e32 v0, v3
-; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1064-DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1064-DPP-NEXT: ; %bb.1:
; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
@@ -12500,16 +12504,16 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1032-DPP-NEXT: v_permlanex16_b32 v5, v3, 0, 0
; GFX1032-DPP-NEXT: v_add_f64 v[3:4], v[3:4], v[5:6]
; GFX1032-DPP-NEXT: s_mov_b32 exec_lo, s0
-; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-DPP-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX1032-DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-DPP-NEXT: v_mov_b32_e32 v1, v4
; GFX1032-DPP-NEXT: s_mov_b32 s2, 0
-; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1032-DPP-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1032-DPP-NEXT: ; %bb.1:
; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[34:35], 0x24
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: global_load_dwordx2 v[9:10], v2, s[0:1]
; GFX1032-DPP-NEXT: .LBB17_2: ; %atomicrmw.start
@@ -12586,12 +12590,12 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_permlane64_b32 v4, v2
; GFX1164-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
-; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v1, v3
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
+; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -12599,6 +12603,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1164-DPP-NEXT: ; %bb.1:
; GFX1164-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX1164-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
@@ -12675,15 +12680,15 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1132-DPP-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5]
; GFX1132-DPP-NEXT: s_mov_b32 exec_lo, s0
; GFX1132-DPP-NEXT: v_mbcnt_lo_u32_b32 v6, exec_lo, 0
-; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1132-DPP-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, v3
-; GFX1132-DPP-NEXT: v_mov_b32_e32 v0, v2
+; GFX1132-DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1132-DPP-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX1132-DPP-NEXT: s_mov_b32 s2, 0
; GFX1132-DPP-NEXT: s_mov_b32 s0, exec_lo
; GFX1132-DPP-NEXT: v_cmpx_eq_u32_e32 0, v6
; GFX1132-DPP-NEXT: s_cbranch_execz .LBB17_3
; GFX1132-DPP-NEXT: ; %bb.1:
; GFX1132-DPP-NEXT: s_load_b64 s[0:1], s[34:35], 0x24
+; GFX1132-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1132-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-DPP-NEXT: global_load_b64 v[8:9], v10, s[0:1]
; GFX1132-DPP-NEXT: .LBB17_2: ; %atomicrmw.start
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 76f204dd0c16a..fa733c2f1d77b 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -6,31 +6,31 @@ define void @main(i1 %arg) #0 {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-NEXT: v_writelane_b32 v6, s30, 0
-; CHECK-NEXT: v_writelane_b32 v6, s31, 1
-; CHECK-NEXT: v_writelane_b32 v6, s36, 2
-; CHECK-NEXT: v_writelane_b32 v6, s37, 3
-; CHECK-NEXT: v_writelane_b32 v6, s38, 4
-; CHECK-NEXT: v_writelane_b32 v6, s39, 5
-; CHECK-NEXT: v_writelane_b32 v6, s48, 6
-; CHECK-NEXT: v_writelane_b32 v6, s49, 7
-; CHECK-NEXT: v_writelane_b32 v6, s50, 8
-; CHECK-NEXT: v_writelane_b32 v6, s51, 9
-; CHECK-NEXT: v_writelane_b32 v6, s52, 10
-; CHECK-NEXT: v_writelane_b32 v6, s53, 11
-; CHECK-NEXT: v_writelane_b32 v6, s54, 12
-; CHECK-NEXT: v_writelane_b32 v6, s55, 13
-; CHECK-NEXT: v_writelane_b32 v6, s64, 14
-; CHECK-NEXT: v_writelane_b32 v6, s65, 15
-; CHECK-NEXT: v_writelane_b32 v6, s66, 16
-; CHECK-NEXT: v_writelane_b32 v6, s67, 17
-; CHECK-NEXT: v_writelane_b32 v6, s68, 18
+; CHECK-NEXT: v_writelane_b32 v5, s30, 0
+; CHECK-NEXT: v_writelane_b32 v5, s31, 1
+; CHECK-NEXT: v_writelane_b32 v5, s36, 2
+; CHECK-NEXT: v_writelane_b32 v5, s37, 3
+; CHECK-NEXT: v_writelane_b32 v5, s38, 4
+; CHECK-NEXT: v_writelane_b32 v5, s39, 5
+; CHECK-NEXT: v_writelane_b32 v5, s48, 6
+; CHECK-NEXT: v_writelane_b32 v5, s49, 7
+; CHECK-NEXT: v_writelane_b32 v5, s50, 8
+; CHECK-NEXT: v_writelane_b32 v5, s51, 9
+; CHECK-NEXT: v_writelane_b32 v5, s52, 10
+; CHECK-NEXT: v_writelane_b32 v5, s53, 11
+; CHECK-NEXT: v_writelane_b32 v5, s54, 12
+; CHECK-NEXT: v_writelane_b32 v5, s55, 13
+; CHECK-NEXT: v_writelane_b32 v5, s64, 14
+; CHECK-NEXT: v_writelane_b32 v5, s65, 15
+; CHECK-NEXT: v_writelane_b32 v5, s66, 16
+; CHECK-NEXT: v_writelane_b32 v5, s67, 17
+; CHECK-NEXT: v_writelane_b32 v5, s68, 18
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
-; CHECK-NEXT: v_writelane_b32 v6, s69, 19
+; CHECK-NEXT: v_writelane_b32 v5, s69, 19
; CHECK-NEXT: s_mov_b32 s68, 0
; CHECK-NEXT: s_mov_b32 s69, s4
; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
@@ -39,105 +39,107 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: ; kill: killed $sgpr8_sgpr9
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x130
-; CHECK-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
-; CHECK-NEXT: v_writelane_b32 v6, s70, 20
-; CHECK-NEXT: v_writelane_b32 v6, s71, 21
+; CHECK-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
+; CHECK-NEXT: v_writelane_b32 v5, s70, 20
+; CHECK-NEXT: v_writelane_b32 v5, s71, 21
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_mov_b32_e32 v2, 0
-; CHECK-NEXT: v_writelane_b32 v7, s8, 0
-; CHECK-NEXT: v_writelane_b32 v7, s9, 1
-; CHECK-NEXT: v_writelane_b32 v7, s10, 2
-; CHECK-NEXT: v_writelane_b32 v7, s11, 3
-; CHECK-NEXT: v_writelane_b32 v7, s12, 4
-; CHECK-NEXT: v_writelane_b32 v7, s13, 5
-; CHECK-NEXT: v_writelane_b32 v7, s14, 6
-; CHECK-NEXT: v_writelane_b32 v7, s15, 7
-; CHECK-NEXT: v_writelane_b32 v7, s16, 8
-; CHECK-NEXT: v_writelane_b32 v7, s17, 9
-; CHECK-NEXT: v_writelane_b32 v7, s18, 10
-; CHECK-NEXT: v_writelane_b32 v7, s19, 11
-; CHECK-NEXT: v_writelane_b32 v7, s20, 12
-; CHECK-NEXT: v_writelane_b32 v7, s21, 13
-; CHECK-NEXT: v_writelane_b32 v7, s22, 14
-; CHECK-NEXT: v_writelane_b32 v7, s23, 15
-; CHECK-NEXT: v_writelane_b32 v7, s52, 16
-; CHECK-NEXT: v_writelane_b32 v7, s53, 17
-; CHECK-NEXT: v_writelane_b32 v7, s54, 18
-; CHECK-NEXT: v_writelane_b32 v7, s55, 19
-; CHECK-NEXT: v_writelane_b32 v7, s56, 20
-; CHECK-NEXT: v_writelane_b32 v7, s57, 21
-; CHECK-NEXT: v_writelane_b32 v7, s58, 22
-; CHECK-NEXT: v_writelane_b32 v7, s59, 23
-; CHECK-NEXT: v_writelane_b32 v7, s60, 24
-; CHECK-NEXT: v_writelane_b32 v7, s61, 25
-; CHECK-NEXT: v_writelane_b32 v7, s62, 26
-; CHECK-NEXT: v_writelane_b32 v7, s63, 27
-; CHECK-NEXT: v_writelane_b32 v7, s64, 28
-; CHECK-NEXT: v_writelane_b32 v7, s65, 29
-; CHECK-NEXT: v_writelane_b32 v7, s66, 30
+; CHECK-NEXT: v_writelane_b32 v6, s8, 0
+; CHECK-NEXT: v_writelane_b32 v6, s9, 1
+; CHECK-NEXT: v_writelane_b32 v6, s10, 2
+; CHECK-NEXT: v_writelane_b32 v6, s11, 3
+; CHECK-NEXT: v_writelane_b32 v6, s12, 4
+; CHECK-NEXT: v_writelane_b32 v6, s13, 5
+; CHECK-NEXT: v_writelane_b32 v6, s14, 6
+; CHECK-NEXT: v_writelane_b32 v6, s15, 7
+; CHECK-NEXT: v_writelane_b32 v6, s16, 8
+; CHECK-NEXT: v_writelane_b32 v6, s17, 9
+; CHECK-NEXT: v_writelane_b32 v6, s18, 10
+; CHECK-NEXT: v_writelane_b32 v6, s19, 11
+; CHECK-NEXT: v_writelane_b32 v6, s20, 12
+; CHECK-NEXT: v_writelane_b32 v6, s21, 13
+; CHECK-NEXT: v_writelane_b32 v6, s22, 14
+; CHECK-NEXT: v_writelane_b32 v6, s23, 15
+; CHECK-NEXT: v_writelane_b32 v6, s52, 16
+; CHECK-NEXT: v_writelane_b32 v6, s53, 17
+; CHECK-NEXT: v_writelane_b32 v6, s54, 18
+; CHECK-NEXT: v_writelane_b32 v6, s55, 19
+; CHECK-NEXT: v_writelane_b32 v6, s56, 20
+; CHECK-NEXT: v_writelane_b32 v6, s57, 21
+; CHECK-NEXT: v_writelane_b32 v6, s58, 22
+; CHECK-NEXT: v_writelane_b32 v6, s59, 23
+; CHECK-NEXT: v_writelane_b32 v6, s60, 24
+; CHECK-NEXT: v_writelane_b32 v6, s61, 25
+; CHECK-NEXT: v_writelane_b32 v6, s62, 26
+; CHECK-NEXT: v_writelane_b32 v6, s63, 27
+; CHECK-NEXT: v_writelane_b32 v6, s64, 28
+; CHECK-NEXT: v_writelane_b32 v6, s65, 29
+; CHECK-NEXT: v_writelane_b32 v6, s66, 30
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x1f0
; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0
; CHECK-NEXT: s_mov_b32 s69, s68
; CHECK-NEXT: s_mov_b32 s70, s68
; CHECK-NEXT: s_mov_b32 s71, s68
-; CHECK-NEXT: v_writelane_b32 v7, s67, 31
+; CHECK-NEXT: v_writelane_b32 v6, s67, 31
; CHECK-NEXT: image_sample_lz v1, v[1:2], s[60:67], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s52, v7, 0
+; CHECK-NEXT: v_readlane_b32 s52, v6, 0
; CHECK-NEXT: v_mov_b32_e32 v3, v2
-; CHECK-NEXT: v_readlane_b32 s53, v7, 1
-; CHECK-NEXT: v_readlane_b32 s54, v7, 2
-; CHECK-NEXT: v_readlane_b32 s55, v7, 3
-; CHECK-NEXT: v_readlane_b32 s56, v7, 4
-; CHECK-NEXT: v_readlane_b32 s57, v7, 5
-; CHECK-NEXT: v_readlane_b32 s58, v7, 6
-; CHECK-NEXT: v_readlane_b32 s59, v7, 7
-; CHECK-NEXT: v_and_b32_e32 v5, 1, v0
-; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, v5
-; CHECK-NEXT: v_readlane_b32 s60, v7, 8
-; CHECK-NEXT: v_readlane_b32 s61, v7, 9
-; CHECK-NEXT: v_readlane_b32 s62, v7, 10
-; CHECK-NEXT: image_sample_lz v4, v[2:3], s[52:59], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s63, v7, 11
-; CHECK-NEXT: v_readlane_b32 s64, v7, 12
-; CHECK-NEXT: v_readlane_b32 s65, v7, 13
-; CHECK-NEXT: v_readlane_b32 s66, v7, 14
-; CHECK-NEXT: v_readlane_b32 s67, v7, 15
+; CHECK-NEXT: v_readlane_b32 s53, v6, 1
+; CHECK-NEXT: v_readlane_b32 s54, v6, 2
+; CHECK-NEXT: v_readlane_b32 s55, v6, 3
+; CHECK-NEXT: v_readlane_b32 s56, v6, 4
+; CHECK-NEXT: v_readlane_b32 s57, v6, 5
+; CHECK-NEXT: v_readlane_b32 s58, v6, 6
+; CHECK-NEXT: v_readlane_b32 s59, v6, 7
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, v0
+; CHECK-NEXT: v_readlane_b32 s60, v6, 8
+; CHECK-NEXT: v_readlane_b32 s61, v6, 9
+; CHECK-NEXT: v_readlane_b32 s62, v6, 10
+; CHECK-NEXT: image_sample_lz v2, v[2:3], s[52:59], s[68:71] dmask:0x1
+; CHECK-NEXT: v_readlane_b32 s63, v6, 11
+; CHECK-NEXT: v_readlane_b32 s64, v6, 12
+; CHECK-NEXT: v_readlane_b32 s65, v6, 13
+; CHECK-NEXT: v_readlane_b32 s66, v6, 14
+; CHECK-NEXT: v_readlane_b32 s67, v6, 15
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_mul_f32_e32 v0, v4, v1
+; CHECK-NEXT: v_mul_f32_e32 v3, v2, v1
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.1: ; %bb48
-; CHECK-NEXT: v_readlane_b32 s52, v7, 16
-; CHECK-NEXT: v_readlane_b32 s60, v7, 24
-; CHECK-NEXT: v_readlane_b32 s61, v7, 25
-; CHECK-NEXT: v_readlane_b32 s62, v7, 26
-; CHECK-NEXT: v_readlane_b32 s63, v7, 27
-; CHECK-NEXT: v_readlane_b32 s64, v7, 28
-; CHECK-NEXT: v_readlane_b32 s65, v7, 29
-; CHECK-NEXT: v_readlane_b32 s66, v7, 30
-; CHECK-NEXT: v_readlane_b32 s67, v7, 31
-; CHECK-NEXT: v_mov_b32_e32 v1, v2
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_readlane_b32 s52, v6, 16
+; CHECK-NEXT: v_mov_b32_e32 v2, v1
+; CHECK-NEXT: v_readlane_b32 s60, v6, 24
+; CHECK-NEXT: v_readlane_b32 s61, v6, 25
+; CHECK-NEXT: v_readlane_b32 s62, v6, 26
+; CHECK-NEXT: v_readlane_b32 s63, v6, 27
+; CHECK-NEXT: v_readlane_b32 s64, v6, 28
+; CHECK-NEXT: v_readlane_b32 s65, v6, 29
+; CHECK-NEXT: v_readlane_b32 s66, v6, 30
+; CHECK-NEXT: v_readlane_b32 s67, v6, 31
+; CHECK-NEXT: v_mov_b32_e32 v0, v1
; CHECK-NEXT: s_and_b64 vcc, exec, -1
-; CHECK-NEXT: v_readlane_b32 s53, v7, 17
-; CHECK-NEXT: v_readlane_b32 s54, v7, 18
-; CHECK-NEXT: v_readlane_b32 s55, v7, 19
-; CHECK-NEXT: image_sample_lz v3, v[2:3], s[60:67], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s56, v7, 20
-; CHECK-NEXT: v_readlane_b32 s57, v7, 21
-; CHECK-NEXT: v_readlane_b32 s58, v7, 22
-; CHECK-NEXT: v_readlane_b32 s59, v7, 23
+; CHECK-NEXT: v_readlane_b32 s53, v6, 17
+; CHECK-NEXT: v_readlane_b32 s54, v6, 18
+; CHECK-NEXT: v_readlane_b32 s55, v6, 19
+; CHECK-NEXT: image_sample_lz v2, v[1:2], s[60:67], s[68:71] dmask:0x1
+; CHECK-NEXT: v_readlane_b32 s56, v6, 20
+; CHECK-NEXT: v_readlane_b32 s57, v6, 21
+; CHECK-NEXT: v_readlane_b32 s58, v6, 22
+; CHECK-NEXT: v_readlane_b32 s59, v6, 23
; CHECK-NEXT: .LBB0_2: ; %bb50
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: image_sample_lz v4, v[1:2], s[16:23], s[28:31] dmask:0x1
+; CHECK-NEXT: image_sample_lz v4, v[0:1], s[16:23], s[28:31] dmask:0x1
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: image_sample_lz v1, v[1:2], s[44:51], s[68:71] dmask:0x1
+; CHECK-NEXT: image_sample_lz v0, v[0:1], s[44:51], s[68:71] dmask:0x1
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_sub_f32_e32 v1, v1, v4
-; CHECK-NEXT: v_mul_f32_e32 v1, v1, v0
-; CHECK-NEXT: v_mul_f32_e32 v1, v1, v3
+; CHECK-NEXT: v_sub_f32_e32 v0, v0, v4
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v3
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v2
; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB0_2
; CHECK-NEXT: .LBB0_3: ; %Flow14
@@ -152,50 +154,50 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: v_mov_b32_e32 v0, s16
-; CHECK-NEXT: v_readlane_b32 s44, v7, 16
+; CHECK-NEXT: v_readlane_b32 s44, v6, 16
; CHECK-NEXT: v_mov_b32_e32 v1, s17
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
-; CHECK-NEXT: v_readlane_b32 s45, v7, 17
-; CHECK-NEXT: v_readlane_b32 s46, v7, 18
-; CHECK-NEXT: v_readlane_b32 s47, v7, 19
-; CHECK-NEXT: v_readlane_b32 s48, v7, 20
-; CHECK-NEXT: v_readlane_b32 s49, v7, 21
-; CHECK-NEXT: v_readlane_b32 s50, v7, 22
-; CHECK-NEXT: v_readlane_b32 s51, v7, 23
-; CHECK-NEXT: v_readlane_b32 s52, v7, 24
-; CHECK-NEXT: v_readlane_b32 s53, v7, 25
-; CHECK-NEXT: v_readlane_b32 s54, v7, 26
-; CHECK-NEXT: v_readlane_b32 s55, v7, 27
-; CHECK-NEXT: v_readlane_b32 s56, v7, 28
-; CHECK-NEXT: v_readlane_b32 s57, v7, 29
-; CHECK-NEXT: v_readlane_b32 s58, v7, 30
-; CHECK-NEXT: v_readlane_b32 s59, v7, 31
+; CHECK-NEXT: v_readlane_b32 s45, v6, 17
+; CHECK-NEXT: v_readlane_b32 s46, v6, 18
+; CHECK-NEXT: v_readlane_b32 s47, v6, 19
+; CHECK-NEXT: v_readlane_b32 s48, v6, 20
+; CHECK-NEXT: v_readlane_b32 s49, v6, 21
+; CHECK-NEXT: v_readlane_b32 s50, v6, 22
+; CHECK-NEXT: v_readlane_b32 s51, v6, 23
+; CHECK-NEXT: v_readlane_b32 s52, v6, 24
+; CHECK-NEXT: v_readlane_b32 s53, v6, 25
+; CHECK-NEXT: v_readlane_b32 s54, v6, 26
+; CHECK-NEXT: v_readlane_b32 s55, v6, 27
+; CHECK-NEXT: v_readlane_b32 s56, v6, 28
+; CHECK-NEXT: v_readlane_b32 s57, v6, 29
+; CHECK-NEXT: v_readlane_b32 s58, v6, 30
+; CHECK-NEXT: v_readlane_b32 s59, v6, 31
; CHECK-NEXT: image_sample_lz v2, v[0:1], s[44:51], s[16:19] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s44, v7, 0
-; CHECK-NEXT: v_readlane_b32 s52, v7, 8
-; CHECK-NEXT: v_readlane_b32 s53, v7, 9
-; CHECK-NEXT: v_readlane_b32 s54, v7, 10
-; CHECK-NEXT: v_readlane_b32 s55, v7, 11
-; CHECK-NEXT: v_readlane_b32 s56, v7, 12
-; CHECK-NEXT: v_readlane_b32 s57, v7, 13
-; CHECK-NEXT: v_readlane_b32 s58, v7, 14
-; CHECK-NEXT: v_readlane_b32 s59, v7, 15
+; CHECK-NEXT: v_readlane_b32 s44, v6, 0
+; CHECK-NEXT: v_readlane_b32 s52, v6, 8
+; CHECK-NEXT: v_readlane_b32 s53, v6, 9
+; CHECK-NEXT: v_readlane_b32 s54, v6, 10
+; CHECK-NEXT: v_readlane_b32 s55, v6, 11
+; CHECK-NEXT: v_readlane_b32 s56, v6, 12
+; CHECK-NEXT: v_readlane_b32 s57, v6, 13
+; CHECK-NEXT: v_readlane_b32 s58, v6, 14
+; CHECK-NEXT: v_readlane_b32 s59, v6, 15
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v4, v3
-; CHECK-NEXT: v_readlane_b32 s45, v7, 1
-; CHECK-NEXT: v_readlane_b32 s46, v7, 2
-; CHECK-NEXT: v_readlane_b32 s47, v7, 3
+; CHECK-NEXT: v_readlane_b32 s45, v6, 1
+; CHECK-NEXT: v_readlane_b32 s46, v6, 2
+; CHECK-NEXT: v_readlane_b32 s47, v6, 3
; CHECK-NEXT: image_sample_lz v0, v[0:1], s[52:59], s[24:27] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s48, v7, 4
-; CHECK-NEXT: v_readlane_b32 s49, v7, 5
-; CHECK-NEXT: v_readlane_b32 s50, v7, 6
-; CHECK-NEXT: v_readlane_b32 s51, v7, 7
+; CHECK-NEXT: v_readlane_b32 s48, v6, 4
+; CHECK-NEXT: v_readlane_b32 s49, v6, 5
+; CHECK-NEXT: v_readlane_b32 s50, v6, 6
+; CHECK-NEXT: v_readlane_b32 s51, v6, 7
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx3 v[2:4], off, s[16:19], 0
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
-; CHECK-NEXT: ; implicit-def: $vgpr0
+; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: .LBB0_6: ; %Flow12
; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; CHECK-NEXT: s_cbranch_execz .LBB0_9
@@ -203,18 +205,18 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s20, s16
; CHECK-NEXT: s_mov_b32 s21, s16
-; CHECK-NEXT: v_mov_b32_e32 v1, s20
+; CHECK-NEXT: v_mov_b32_e32 v0, s20
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
-; CHECK-NEXT: v_mov_b32_e32 v2, s21
-; CHECK-NEXT: image_sample_lz v3, v[1:2], s[8:15], s[16:19] dmask:0x1
-; CHECK-NEXT: image_sample_lz v4, v[1:2], s[36:43], s[16:19] dmask:0x1
+; CHECK-NEXT: v_mov_b32_e32 v1, s21
+; CHECK-NEXT: image_sample_lz v2, v[0:1], s[8:15], s[16:19] dmask:0x1
+; CHECK-NEXT: image_sample_lz v4, v[0:1], s[36:43], s[16:19] dmask:0x1
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_and_b64 vcc, exec, 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_sub_f32_e32 v1, v4, v3
-; CHECK-NEXT: v_mul_f32_e32 v0, v1, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_sub_f32_e32 v0, v4, v2
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v3
; CHECK-NEXT: .LBB0_8: ; %bb33
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_f32_e32 v2, v1, v0
@@ -225,32 +227,32 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
-; CHECK-NEXT: v_readlane_b32 s71, v6, 21
-; CHECK-NEXT: v_readlane_b32 s70, v6, 20
-; CHECK-NEXT: v_readlane_b32 s69, v6, 19
-; CHECK-NEXT: v_readlane_b32 s68, v6, 18
-; CHECK-NEXT: v_readlane_b32 s67, v6, 17
-; CHECK-NEXT: v_readlane_b32 s66, v6, 16
-; CHECK-NEXT: v_readlane_b32 s65, v6, 15
-; CHECK-NEXT: v_readlane_b32 s64, v6, 14
-; CHECK-NEXT: v_readlane_b32 s55, v6, 13
-; CHECK-NEXT: v_readlane_b32 s54, v6, 12
-; CHECK-NEXT: v_readlane_b32 s53, v6, 11
-; CHECK-NEXT: v_readlane_b32 s52, v6, 10
+; CHECK-NEXT: v_readlane_b32 s71, v5, 21
+; CHECK-NEXT: v_readlane_b32 s70, v5, 20
+; CHECK-NEXT: v_readlane_b32 s69, v5, 19
+; CHECK-NEXT: v_readlane_b32 s68, v5, 18
+; CHECK-NEXT: v_readlane_b32 s67, v5, 17
+; CHECK-NEXT: v_readlane_b32 s66, v5, 16
+; CHECK-NEXT: v_readlane_b32 s65, v5, 15
+; CHECK-NEXT: v_readlane_b32 s64, v5, 14
+; CHECK-NEXT: v_readlane_b32 s55, v5, 13
+; CHECK-NEXT: v_readlane_b32 s54, v5, 12
+; CHECK-NEXT: v_readlane_b32 s53, v5, 11
+; CHECK-NEXT: v_readlane_b32 s52, v5, 10
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_readlane_b32 s51, v6, 9
-; CHECK-NEXT: v_readlane_b32 s50, v6, 8
-; CHECK-NEXT: v_readlane_b32 s49, v6, 7
-; CHECK-NEXT: v_readlane_b32 s48, v6, 6
-; CHECK-NEXT: v_readlane_b32 s39, v6, 5
-; CHECK-NEXT: v_readlane_b32 s38, v6, 4
-; CHECK-NEXT: v_readlane_b32 s37, v6, 3
-; CHECK-NEXT: v_readlane_b32 s36, v6, 2
-; CHECK-NEXT: v_readlane_b32 s31, v6, 1
-; CHECK-NEXT: v_readlane_b32 s30, v6, 0
+; CHECK-NEXT: v_readlane_b32 s51, v5, 9
+; CHECK-NEXT: v_readlane_b32 s50, v5, 8
+; CHECK-NEXT: v_readlane_b32 s49, v5, 7
+; CHECK-NEXT: v_readlane_b32 s48, v5, 6
+; CHECK-NEXT: v_readlane_b32 s39, v5, 5
+; CHECK-NEXT: v_readlane_b32 s38, v5, 4
+; CHECK-NEXT: v_readlane_b32 s37, v5, 3
+; CHECK-NEXT: v_readlane_b32 s36, v5, 2
+; CHECK-NEXT: v_readlane_b32 s31, v5, 1
+; CHECK-NEXT: v_readlane_b32 s30, v5, 0
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index c08b0304239fe..59f8adc9768a1 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -144,119 +144,120 @@ define float @sitofp_i128_to_f32(i128 %x) {
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; GISEL-NEXT: v_xor_b32_e32 v0, v6, v0
; GISEL-NEXT: v_xor_b32_e32 v1, v6, v1
-; GISEL-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v6
; GISEL-NEXT: v_xor_b32_e32 v2, v6, v2
-; GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_xor_b32_e32 v3, v6, v3
-; GISEL-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v5, v0
-; GISEL-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v4, v1
-; GISEL-NEXT: v_add_u32_e32 v5, 32, v5
-; GISEL-NEXT: v_ffbh_u32_e32 v7, v2
-; GISEL-NEXT: v_min_u32_e32 v4, v4, v5
-; GISEL-NEXT: v_ffbh_u32_e32 v5, v3
+; GISEL-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v6, vcc
+; GISEL-NEXT: v_xor_b32_e32 v7, v6, v3
+; GISEL-NEXT: v_subb_co_u32_e32 v0, vcc, v2, v6, vcc
+; GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v7, v6, vcc
+; GISEL-NEXT: v_ffbh_u32_e32 v6, v4
+; GISEL-NEXT: v_ffbh_u32_e32 v2, v5
+; GISEL-NEXT: v_add_u32_e32 v6, 32, v6
+; GISEL-NEXT: v_ffbh_u32_e32 v7, v0
+; GISEL-NEXT: v_min_u32_e32 v2, v2, v6
+; GISEL-NEXT: v_ffbh_u32_e32 v6, v1
; GISEL-NEXT: v_add_u32_e32 v7, 32, v7
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GISEL-NEXT: v_add_u32_e32 v4, 64, v4
-; GISEL-NEXT: v_min_u32_e32 v5, v5, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
-; GISEL-NEXT: v_sub_u32_e32 v7, 0x80, v5
-; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 24, v7
-; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v2, 64, v2
+; GISEL-NEXT: v_min_u32_e32 v6, v6, v7
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc
+; GISEL-NEXT: v_sub_u32_e32 v2, 0x80, v7
+; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 24, v2
+; GISEL-NEXT: ; implicit-def: $vgpr6
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GISEL-NEXT: ; %bb.2: ; %itofp-if-else
-; GISEL-NEXT: v_add_u32_e32 v2, 0xffffff98, v5
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v2, 0xffffff98, v7
+; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
-; GISEL-NEXT: ; implicit-def: $vgpr7
-; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v0, vcc
; GISEL-NEXT: ; implicit-def: $vgpr2
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: ; implicit-def: $vgpr0
; GISEL-NEXT: ; %bb.3: ; %Flow3
; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5]
-; GISEL-NEXT: v_sub_u32_e32 v8, 0x7f, v5
+; GISEL-NEXT: v_sub_u32_e32 v8, 0x7f, v7
; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execz .LBB0_13
; GISEL-NEXT: ; %bb.4: ; %NodeBlock
-; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 26, v7
+; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 26, v2
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GISEL-NEXT: s_cbranch_execz .LBB0_8
; GISEL-NEXT: ; %bb.5: ; %LeafBlock
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 26, v7
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 26, v2
; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc
; GISEL-NEXT: s_cbranch_execz .LBB0_7
; GISEL-NEXT: ; %bb.6: ; %itofp-sw-default
-; GISEL-NEXT: v_sub_u32_e32 v4, 0x66, v5
-; GISEL-NEXT: v_sub_u32_e32 v11, 64, v4
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v4, v[0:1]
-; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, v[2:3]
-; GISEL-NEXT: v_add_u32_e32 v13, 0xffffffc0, v4
+; GISEL-NEXT: v_sub_u32_e32 v6, 0x66, v7
+; GISEL-NEXT: v_sub_u32_e32 v11, 64, v6
+; GISEL-NEXT: v_lshrrev_b64 v[9:10], v6, v[4:5]
+; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v13, 0xffffffc0, v6
; GISEL-NEXT: v_or_b32_e32 v11, v9, v11
; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[2:3]
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
+; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[0:1]
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
+; GISEL-NEXT: v_add_u32_e32 v14, 26, v7
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_sub_u32_e32 v11, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v1, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v10, v5, vcc
; GISEL-NEXT: v_lshrrev_b64 v[9:10], v14, -1
; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
+; GISEL-NEXT: v_add_u32_e32 v7, 0xffffffda, v7
; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
; GISEL-NEXT: v_or_b32_e32 v16, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[11:12], v5, -1
+; GISEL-NEXT: v_lshrrev_b64 v[11:12], v7, -1
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v11, v15, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v10, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v11, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v0, v9, v0
+; GISEL-NEXT: v_and_b32_e32 v1, v10, v1
+; GISEL-NEXT: v_and_or_b32 v0, v7, v4, v0
+; GISEL-NEXT: v_and_or_b32 v1, v11, v5, v1
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v13, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v5, v13, v0
+; GISEL-NEXT: v_mov_b32_e32 v4, v5
+; GISEL-NEXT: v_mov_b32_e32 v5, v6
+; GISEL-NEXT: v_mov_b32_e32 v6, v7
+; GISEL-NEXT: v_mov_b32_e32 v7, v8
; GISEL-NEXT: .LBB0_7: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB0_8: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-bb
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; GISEL-NEXT: ; %bb.10: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
-; GISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GISEL-NEXT: v_bfe_u32 v0, v4, 2, 1
+; GISEL-NEXT: v_or_b32_e32 v0, v4, v0
; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0
-; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT: v_and_b32_e32 v2, 0x4000000, v0
-; GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], 2, v[0:1]
-; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
+; GISEL-NEXT: v_and_b32_e32 v4, 0x4000000, v0
+; GISEL-NEXT: v_mov_b32_e32 v5, 0
+; GISEL-NEXT: v_lshrrev_b64 v[6:7], 2, v[0:1]
+; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: ; %bb.11: ; %itofp-if-then20
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], 3, v[0:1]
-; GISEL-NEXT: v_mov_b32_e32 v8, v7
+; GISEL-NEXT: v_lshrrev_b64 v[6:7], 3, v[0:1]
+; GISEL-NEXT: v_mov_b32_e32 v8, v2
; GISEL-NEXT: ; %bb.12: ; %Flow
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: .LBB0_13: ; %Flow4
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
-; GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v6
+; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GISEL-NEXT: v_lshl_add_u32 v1, v8, 23, 1.0
-; GISEL-NEXT: v_and_b32_e32 v2, 0x7fffff, v4
+; GISEL-NEXT: v_and_b32_e32 v2, 0x7fffff, v6
; GISEL-NEXT: v_or3_b32 v4, v2, v0, v1
; GISEL-NEXT: .LBB0_14: ; %Flow5
; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
@@ -669,64 +670,64 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GISEL-NEXT: s_cbranch_execz .LBB2_14
; GISEL-NEXT: ; %bb.1: ; %itofp-if-end
-; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
-; GISEL-NEXT: v_xor_b32_e32 v0, v6, v4
-; GISEL-NEXT: v_xor_b32_e32 v1, v6, v5
-; GISEL-NEXT: v_xor_b32_e32 v4, v6, v2
-; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, v0, v6
-; GISEL-NEXT: v_xor_b32_e32 v5, v6, v3
-; GISEL-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v6, vcc
-; GISEL-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v1, v2
-; GISEL-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v0, v3
+; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v3
+; GISEL-NEXT: v_xor_b32_e32 v1, v0, v4
+; GISEL-NEXT: v_xor_b32_e32 v5, v0, v5
+; GISEL-NEXT: v_sub_co_u32_e32 v4, vcc, v1, v0
+; GISEL-NEXT: v_xor_b32_e32 v2, v0, v2
+; GISEL-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v0, vcc
+; GISEL-NEXT: v_xor_b32_e32 v7, v0, v3
+; GISEL-NEXT: v_subb_co_u32_e32 v6, vcc, v2, v0, vcc
+; GISEL-NEXT: v_ffbh_u32_e32 v1, v4
+; GISEL-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v0, vcc
+; GISEL-NEXT: v_ffbh_u32_e32 v0, v5
; GISEL-NEXT: v_add_u32_e32 v1, 32, v1
-; GISEL-NEXT: v_ffbh_u32_e32 v7, v4
+; GISEL-NEXT: v_ffbh_u32_e32 v2, v6
; GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GISEL-NEXT: v_ffbh_u32_e32 v1, v5
-; GISEL-NEXT: v_add_u32_e32 v7, 32, v7
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GISEL-NEXT: v_ffbh_u32_e32 v1, v7
+; GISEL-NEXT: v_add_u32_e32 v2, 32, v2
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GISEL-NEXT: v_add_u32_e32 v0, 64, v0
-; GISEL-NEXT: v_min_u32_e32 v1, v1, v7
+; GISEL-NEXT: v_min_u32_e32 v1, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v9, v1, v0, vcc
-; GISEL-NEXT: v_sub_u32_e32 v7, 0x80, v9
-; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 53, v7
+; GISEL-NEXT: v_sub_u32_e32 v2, 0x80, v9
+; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 53, v2
; GISEL-NEXT: ; implicit-def: $vgpr10
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GISEL-NEXT: ; %bb.2: ; %itofp-if-else
-; GISEL-NEXT: v_add_u32_e32 v4, 0xffffffb5, v9
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], v4, v[2:3]
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
+; GISEL-NEXT: v_add_u32_e32 v2, 0xffffffb5, v9
+; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[4:5]
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v1, vcc
-; GISEL-NEXT: ; implicit-def: $vgpr7
; GISEL-NEXT: ; implicit-def: $vgpr2
+; GISEL-NEXT: ; implicit-def: $vgpr4
; GISEL-NEXT: ; %bb.3: ; %Flow3
; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5]
; GISEL-NEXT: v_sub_u32_e32 v8, 0x7f, v9
; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execz .LBB2_13
; GISEL-NEXT: ; %bb.4: ; %NodeBlock
-; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 55, v7
+; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 55, v2
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GISEL-NEXT: s_cbranch_execz .LBB2_8
; GISEL-NEXT: ; %bb.5: ; %LeafBlock
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 55, v7
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 55, v2
; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc
; GISEL-NEXT: s_cbranch_execz .LBB2_7
; GISEL-NEXT: ; %bb.6: ; %itofp-sw-default
; GISEL-NEXT: v_sub_u32_e32 v14, 0x49, v9
; GISEL-NEXT: v_sub_u32_e32 v10, 64, v14
-; GISEL-NEXT: v_lshrrev_b64 v[0:1], v14, v[2:3]
-; GISEL-NEXT: v_lshlrev_b64 v[10:11], v10, v[4:5]
+; GISEL-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5]
+; GISEL-NEXT: v_lshlrev_b64 v[10:11], v10, v[6:7]
; GISEL-NEXT: v_add_u32_e32 v15, 0xffffffc0, v14
-; GISEL-NEXT: v_lshrrev_b64 v[12:13], v14, v[4:5]
+; GISEL-NEXT: v_lshrrev_b64 v[12:13], v14, v[6:7]
; GISEL-NEXT: v_or_b32_e32 v10, v0, v10
; GISEL-NEXT: v_or_b32_e32 v11, v1, v11
-; GISEL-NEXT: v_lshrrev_b64 v[0:1], v15, v[4:5]
+; GISEL-NEXT: v_lshrrev_b64 v[0:1], v15, v[6:7]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; GISEL-NEXT: v_add_u32_e32 v15, 55, v9
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
@@ -734,8 +735,8 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
; GISEL-NEXT: v_sub_u32_e32 v12, 64, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v14, v0, v2, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v10, v1, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v14, v0, v4, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v10, v1, v5, s[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v15, -1
; GISEL-NEXT: v_lshlrev_b64 v[12:13], v12, -1
; GISEL-NEXT: v_add_u32_e32 v9, -9, v9
@@ -750,54 +751,55 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v9, v9, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v12, v12, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v0, v0, v4
-; GISEL-NEXT: v_and_b32_e32 v1, v1, v5
-; GISEL-NEXT: v_and_or_b32 v0, v9, v2, v0
-; GISEL-NEXT: v_and_or_b32 v1, v12, v3, v1
+; GISEL-NEXT: v_and_b32_e32 v0, v0, v6
+; GISEL-NEXT: v_and_b32_e32 v1, v1, v7
+; GISEL-NEXT: v_and_or_b32 v0, v9, v4, v0
+; GISEL-NEXT: v_and_or_b32 v1, v12, v5, v1
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_or_b32_e32 v9, v14, v0
-; GISEL-NEXT: v_mov_b32_e32 v2, v9
-; GISEL-NEXT: v_mov_b32_e32 v3, v10
-; GISEL-NEXT: v_mov_b32_e32 v4, v11
-; GISEL-NEXT: v_mov_b32_e32 v5, v12
+; GISEL-NEXT: v_mov_b32_e32 v4, v9
+; GISEL-NEXT: v_mov_b32_e32 v5, v10
+; GISEL-NEXT: v_mov_b32_e32 v6, v11
+; GISEL-NEXT: v_mov_b32_e32 v7, v12
; GISEL-NEXT: .LBB2_7: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB2_8: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: s_cbranch_execz .LBB2_10
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-bb
-; GISEL-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[2:3]
-; GISEL-NEXT: v_lshrrev_b32_e32 v2, 31, v3
-; GISEL-NEXT: v_or_b32_e32 v2, v4, v2
-; GISEL-NEXT: v_mov_b32_e32 v5, v3
-; GISEL-NEXT: v_mov_b32_e32 v4, v2
-; GISEL-NEXT: v_mov_b32_e32 v3, v1
-; GISEL-NEXT: v_mov_b32_e32 v2, v0
+; GISEL-NEXT: v_lshlrev_b64 v[9:10], 1, v[4:5]
+; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
+; GISEL-NEXT: v_lshrrev_b32_e32 v1, 31, v5
+; GISEL-NEXT: v_or_b32_e32 v11, v0, v1
+; GISEL-NEXT: v_mov_b32_e32 v4, v9
+; GISEL-NEXT: v_mov_b32_e32 v5, v10
+; GISEL-NEXT: v_mov_b32_e32 v6, v11
+; GISEL-NEXT: v_mov_b32_e32 v7, v12
; GISEL-NEXT: .LBB2_10: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GISEL-NEXT: v_bfe_u32 v0, v2, 2, 1
-; GISEL-NEXT: v_or_b32_e32 v0, v2, v0
-; GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 1, v0
-; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[0:1], 2, v[2:3]
+; GISEL-NEXT: v_bfe_u32 v0, v4, 2, 1
+; GISEL-NEXT: v_or_b32_e32 v0, v4, v0
+; GISEL-NEXT: v_add_co_u32_e32 v4, vcc, 1, v0
+; GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GISEL-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
; GISEL-NEXT: v_mov_b32_e32 v9, 0
-; GISEL-NEXT: v_and_b32_e32 v10, 0x800000, v3
+; GISEL-NEXT: v_and_b32_e32 v10, 0x800000, v5
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
-; GISEL-NEXT: v_lshl_or_b32 v10, v4, 30, v1
+; GISEL-NEXT: v_lshl_or_b32 v10, v6, 30, v1
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: ; %bb.11: ; %itofp-if-then20
-; GISEL-NEXT: v_lshrrev_b64 v[0:1], 3, v[2:3]
-; GISEL-NEXT: v_mov_b32_e32 v8, v7
-; GISEL-NEXT: v_lshl_or_b32 v10, v4, 29, v1
+; GISEL-NEXT: v_lshrrev_b64 v[0:1], 3, v[4:5]
+; GISEL-NEXT: v_mov_b32_e32 v8, v2
+; GISEL-NEXT: v_lshl_or_b32 v10, v6, 29, v1
; GISEL-NEXT: ; %bb.12: ; %Flow
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: .LBB2_13: ; %Flow4
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
+; GISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v3
; GISEL-NEXT: v_mov_b32_e32 v2, 0x3ff00000
-; GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v6
+; GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1
; GISEL-NEXT: v_lshl_add_u32 v2, v8, 20, v2
; GISEL-NEXT: v_and_b32_e32 v3, 0xfffff, v10
; GISEL-NEXT: v_or3_b32 v1, v3, v1, v2
@@ -1233,119 +1235,120 @@ define half @sitofp_i128_to_f16(i128 %x) {
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; GISEL-NEXT: v_xor_b32_e32 v0, v6, v0
; GISEL-NEXT: v_xor_b32_e32 v1, v6, v1
-; GISEL-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v6
; GISEL-NEXT: v_xor_b32_e32 v2, v6, v2
-; GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_xor_b32_e32 v3, v6, v3
-; GISEL-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v5, v0
-; GISEL-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT: v_ffbh_u32_e32 v4, v1
-; GISEL-NEXT: v_add_u32_e32 v5, 32, v5
-; GISEL-NEXT: v_ffbh_u32_e32 v7, v2
-; GISEL-NEXT: v_min_u32_e32 v4, v4, v5
-; GISEL-NEXT: v_ffbh_u32_e32 v5, v3
+; GISEL-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v6, vcc
+; GISEL-NEXT: v_xor_b32_e32 v7, v6, v3
+; GISEL-NEXT: v_subb_co_u32_e32 v0, vcc, v2, v6, vcc
+; GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v7, v6, vcc
+; GISEL-NEXT: v_ffbh_u32_e32 v6, v4
+; GISEL-NEXT: v_ffbh_u32_e32 v2, v5
+; GISEL-NEXT: v_add_u32_e32 v6, 32, v6
+; GISEL-NEXT: v_ffbh_u32_e32 v7, v0
+; GISEL-NEXT: v_min_u32_e32 v2, v2, v6
+; GISEL-NEXT: v_ffbh_u32_e32 v6, v1
; GISEL-NEXT: v_add_u32_e32 v7, 32, v7
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GISEL-NEXT: v_add_u32_e32 v4, 64, v4
-; GISEL-NEXT: v_min_u32_e32 v5, v5, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
-; GISEL-NEXT: v_sub_u32_e32 v7, 0x80, v5
-; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 24, v7
-; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v2, 64, v2
+; GISEL-NEXT: v_min_u32_e32 v6, v6, v7
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc
+; GISEL-NEXT: v_sub_u32_e32 v2, 0x80, v7
+; GISEL-NEXT: v_cmp_ge_i32_e32 vcc, 24, v2
+; GISEL-NEXT: ; implicit-def: $vgpr6
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GISEL-NEXT: ; %bb.2: ; %itofp-if-else
-; GISEL-NEXT: v_add_u32_e32 v2, 0xffffff98, v5
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v2, 0xffffff98, v7
+; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
-; GISEL-NEXT: ; implicit-def: $vgpr7
-; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v0, vcc
; GISEL-NEXT: ; implicit-def: $vgpr2
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: ; implicit-def: $vgpr0
; GISEL-NEXT: ; %bb.3: ; %Flow3
; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5]
-; GISEL-NEXT: v_sub_u32_e32 v8, 0x7f, v5
+; GISEL-NEXT: v_sub_u32_e32 v8, 0x7f, v7
; GISEL-NEXT: s_xor_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execz .LBB4_13
; GISEL-NEXT: ; %bb.4: ; %NodeBlock
-; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 26, v7
+; GISEL-NEXT: v_cmp_le_i32_e32 vcc, 26, v2
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GISEL-NEXT: s_cbranch_execz .LBB4_8
; GISEL-NEXT: ; %bb.5: ; %LeafBlock
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 26, v7
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 26, v2
; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc
; GISEL-NEXT: s_cbranch_execz .LBB4_7
; GISEL-NEXT: ; %bb.6: ; %itofp-sw-default
-; GISEL-NEXT: v_sub_u32_e32 v4, 0x66, v5
-; GISEL-NEXT: v_sub_u32_e32 v11, 64, v4
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v4, v[0:1]
-; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, v[2:3]
-; GISEL-NEXT: v_add_u32_e32 v13, 0xffffffc0, v4
+; GISEL-NEXT: v_sub_u32_e32 v6, 0x66, v7
+; GISEL-NEXT: v_sub_u32_e32 v11, 64, v6
+; GISEL-NEXT: v_lshrrev_b64 v[9:10], v6, v[4:5]
+; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, v[0:1]
+; GISEL-NEXT: v_add_u32_e32 v13, 0xffffffc0, v6
; GISEL-NEXT: v_or_b32_e32 v11, v9, v11
; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[2:3]
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
+; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[0:1]
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
+; GISEL-NEXT: v_add_u32_e32 v14, 26, v7
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_sub_u32_e32 v11, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v1, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v10, v5, vcc
; GISEL-NEXT: v_lshrrev_b64 v[9:10], v14, -1
; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
+; GISEL-NEXT: v_add_u32_e32 v7, 0xffffffda, v7
; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
; GISEL-NEXT: v_or_b32_e32 v16, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[11:12], v5, -1
+; GISEL-NEXT: v_lshrrev_b64 v[11:12], v7, -1
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v11, v15, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v10, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v11, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v0, v9, v0
+; GISEL-NEXT: v_and_b32_e32 v1, v10, v1
+; GISEL-NEXT: v_and_or_b32 v0, v7, v4, v0
+; GISEL-NEXT: v_and_or_b32 v1, v11, v5, v1
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v13, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v5, v13, v0
+; GISEL-NEXT: v_mov_b32_e32 v4, v5
+; GISEL-NEXT: v_mov_b32_e32 v5, v6
+; GISEL-NEXT: v_mov_b32_e32 v6, v7
+; GISEL-NEXT: v_mov_b32_e32 v7, v8
; GISEL-NEXT: .LBB4_7: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB4_8: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-bb
-; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
; GISEL-NEXT: ; %bb.10: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
-; GISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GISEL-NEXT: v_bfe_u32 v0, v4, 2, 1
+; GISEL-NEXT: v_or_b32_e32 v0, v4, v0
; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0
-; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT: v_and_b32_e32 v2, 0x4000000, v0
-; GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], 2, v[0:1]
-; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
+; GISEL-NEXT: v_and_b32_e32 v4, 0x4000000, v0
+; GISEL-NEXT: v_mov_b32_e32 v5, 0
+; GISEL-NEXT: v_lshrrev_b64 v[6:7], 2, v[0:1]
+; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: ; %bb.11: ; %itofp-if-then20
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], 3, v[0:1]
-; GISEL-NEXT: v_mov_b32_e32 v8, v7
+; GISEL-NEXT: v_lshrrev_b64 v[6:7], 3, v[0:1]
+; GISEL-NEXT: v_mov_b32_e32 v8, v2
; GISEL-NEXT: ; %bb.12: ; %Flow
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: .LBB4_13: ; %Flow4
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
-; GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v6
+; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v3
+; GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0
; GISEL-NEXT: v_lshl_add_u32 v1, v8, 23, 1.0
-; GISEL-NEXT: v_and_b32_e32 v2, 0x7fffff, v4
+; GISEL-NEXT: v_and_b32_e32 v2, 0x7fffff, v6
; GISEL-NEXT: v_or3_b32 v0, v2, v0, v1
; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v0
; GISEL-NEXT: .LBB4_14: ; %Flow5
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index 4b658de512f81..dcd573234a312 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -62,7 +62,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b64 s[36:37], s[10:11]
; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7]
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: v_mov_b32_e32 v46, 0
+; CHECK-NEXT: v_mov_b32_e32 v42, 0
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v43, v0
; CHECK-NEXT: v_mov_b32_e32 v31, v40
@@ -92,7 +92,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: ds_write_b32 v46, v46 offset:15360
+; CHECK-NEXT: ds_write_b32 v42, v42 offset:15360
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v43
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 2, v43
@@ -121,14 +121,15 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_cbranch_execz .LBB0_25
; CHECK-NEXT: ; %bb.1: ; %.preheader5
; CHECK-NEXT: v_mul_lo_u32 v44, v41, 14
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: s_mov_b32 s5, 0
; CHECK-NEXT: v_add_nc_u32_e32 v45, 0x3c04, v44
; CHECK-NEXT: .LBB0_2: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_add_nc_u32_e32 v0, s5, v45
+; CHECK-NEXT: v_add_nc_u32_e32 v1, s5, v45
; CHECK-NEXT: s_add_i32 s5, s5, 1
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v42
-; CHECK-NEXT: ds_write_b8 v0, v46
+; CHECK-NEXT: ds_write_b8 v1, v0
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
; CHECK-NEXT: s_cbranch_execnz .LBB0_2
@@ -161,7 +162,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: ; %bb.6: ; %.preheader2
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: s_mov_b32 s68, 0
-; CHECK-NEXT: s_mov_b32 s69, s53
+; CHECK-NEXT: s_mov_b32 s80, s53
; CHECK-NEXT: s_branch .LBB0_8
; CHECK-NEXT: .LBB0_7: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
@@ -169,17 +170,18 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_add_nc_u32_e32 v57, 4, v57
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s4, v42
; CHECK-NEXT: v_mov_b32_e32 v58, s69
+; CHECK-NEXT: s_mov_b32 s80, s69
; CHECK-NEXT: s_or_b32 s68, vcc_lo, s68
; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s68
; CHECK-NEXT: s_cbranch_execz .LBB0_16
; CHECK-NEXT: .LBB0_8: ; Parent Loop BB0_5 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NEXT: v_add_nc_u32_e32 v58, s69, v45
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s80, v45
; CHECK-NEXT: s_mov_b32 s69, s4
-; CHECK-NEXT: ds_read_u8 v0, v58
+; CHECK-NEXT: ds_read_u8 v0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s5, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s80, s5
+; CHECK-NEXT: s_and_saveexec_b32 s81, s5
; CHECK-NEXT: s_cbranch_execz .LBB0_10
; CHECK-NEXT: ; %bb.9: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
@@ -201,11 +203,12 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v57
; CHECK-NEXT: .LBB0_10: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
-; CHECK-NEXT: ds_read_u8 v0, v58 offset:1
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s80, v45
+; CHECK-NEXT: ds_read_u8 v0, v0 offset:1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s80, s4
+; CHECK-NEXT: s_and_saveexec_b32 s81, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_12
; CHECK-NEXT: ; %bb.11: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
@@ -221,18 +224,19 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: v_add_nc_u32_e32 v59, 1, v57
+; CHECK-NEXT: v_add_nc_u32_e32 v58, 1, v57
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; CHECK-NEXT: ds_write_b32 v0, v59
+; CHECK-NEXT: ds_write_b32 v0, v58
; CHECK-NEXT: .LBB0_12: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
-; CHECK-NEXT: ds_read_u8 v0, v58 offset:2
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s80, v45
+; CHECK-NEXT: ds_read_u8 v0, v0 offset:2
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s80, s4
+; CHECK-NEXT: s_and_saveexec_b32 s81, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_14
; CHECK-NEXT: ; %bb.13: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
@@ -248,15 +252,16 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: v_add_nc_u32_e32 v59, 2, v57
+; CHECK-NEXT: v_add_nc_u32_e32 v58, 2, v57
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; CHECK-NEXT: ds_write_b32 v0, v59
+; CHECK-NEXT: ds_write_b32 v0, v58
; CHECK-NEXT: .LBB0_14: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
-; CHECK-NEXT: ds_read_u8 v0, v58 offset:3
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s80, v45
+; CHECK-NEXT: ds_read_u8 v0, v0 offset:3
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: s_and_saveexec_b32 s80, s4
@@ -817,7 +822,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_mov_b64 s[34:35], s[10:11]
; CHECK-NEXT: s_mov_b64 s[36:37], s[6:7]
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: v_mov_b32_e32 v43, 0
+; CHECK-NEXT: v_mov_b32_e32 v41, 0
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v42, v0
; CHECK-NEXT: v_mov_b32_e32 v31, v40
@@ -834,7 +839,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_mul_lo_u32 v44, v0, 14
+; CHECK-NEXT: v_mul_lo_u32 v43, v0, 14
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 1
; CHECK-NEXT: s_getpc_b64 s[16:17]
@@ -847,8 +852,8 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: ds_write_b32 v43, v43 offset:15360
-; CHECK-NEXT: v_add_nc_u32_e32 v45, 0x3c04, v44
+; CHECK-NEXT: ds_write_b32 v41, v41 offset:15360
+; CHECK-NEXT: v_add_nc_u32_e32 v44, 0x3c04, v43
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v42
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 2, v42
@@ -872,18 +877,19 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: v_mov_b32_e32 v1, 12
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v41, v0
+; CHECK-NEXT: v_mov_b32_e32 v45, 0
; CHECK-NEXT: v_lshlrev_b32_e32 v42, 10, v42
; CHECK-NEXT: s_mov_b32 s53, 0
; CHECK-NEXT: s_mov_b32 s52, 0
-; CHECK-NEXT: ds_write_b8 v44, v43 offset:15364
; CHECK-NEXT: v_add_nc_u32_e32 v46, -1, v41
+; CHECK-NEXT: ds_write_b8 v43, v45 offset:15364
; CHECK-NEXT: .LBB1_1: ; %.37
; CHECK-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NEXT: ; Child Loop BB1_3 Depth 2
; CHECK-NEXT: ; Child Loop BB1_8 Depth 2
; CHECK-NEXT: s_mov_b32 s4, s53
; CHECK-NEXT: s_lshl_b32 s6, s53, 5
-; CHECK-NEXT: v_add_nc_u32_e32 v0, s4, v45
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s4, v44
; CHECK-NEXT: s_add_i32 s53, s53, 1
; CHECK-NEXT: s_add_i32 s5, s4, 5
; CHECK-NEXT: v_or3_b32 v56, s6, v42, s53
@@ -900,7 +906,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: ; Parent Loop BB1_1 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NEXT: s_add_i32 s7, s5, 4
-; CHECK-NEXT: v_add_nc_u32_e32 v43, 1, v43
+; CHECK-NEXT: v_add_nc_u32_e32 v45, 1, v45
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s7, v41
; CHECK-NEXT: v_add_nc_u32_e32 v56, 4, v56
; CHECK-NEXT: v_mov_b32_e32 v57, s5
@@ -935,7 +941,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: .LBB1_8: ; %.103
; CHECK-NEXT: ; Parent Loop BB1_1 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NEXT: v_add_nc_u32_e32 v0, v44, v57
+; CHECK-NEXT: v_add_nc_u32_e32 v0, v43, v57
; CHECK-NEXT: ds_read_u8 v0, v0 offset:15364
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v47, v0 src0_sel:BYTE_0 src1_sel:DWORD
@@ -956,7 +962,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: v_add_nc_u32_e32 v43, 1, v43
+; CHECK-NEXT: v_add_nc_u32_e32 v45, 1, v45
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -972,7 +978,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: ; %bb.12: ; %.32
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s53, v46
-; CHECK-NEXT: v_cmp_lt_u32_e64 s4, 59, v43
+; CHECK-NEXT: v_cmp_lt_u32_e64 s4, 59, v45
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
; CHECK-NEXT: s_and_b32 s4, exec_lo, s4
; CHECK-NEXT: s_or_b32 s52, s4, s52
diff --git a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
index 053cf0e1c6906..2a279d263bc63 100644
--- a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+++ b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
@@ -12,6 +12,7 @@ define <2 x i32> @uniform_masked_load_ptr1_mask_v2i32(ptr addrspace(1) inreg noc
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB0_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
; GFX942-NEXT: .LBB0_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -37,6 +38,7 @@ define <4 x i32> @uniform_masked_load_ptr1_mask_v4i32(ptr addrspace(1) inreg noc
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB1_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-NEXT: .LBB1_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -62,6 +64,7 @@ define <4 x float> @uniform_masked_load_ptr1_mask_v4f32(ptr addrspace(1) inreg n
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB2_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-NEXT: .LBB2_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -91,9 +94,9 @@ define <8 x i32> @uniform_masked_load_ptr1_mask_v8i32(ptr addrspace(1) inreg noc
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB3_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
-; GFX942-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
-; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1]
; GFX942-NEXT: .LBB3_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -122,9 +125,9 @@ define <8 x float> @uniform_masked_load_ptr1_mask_v8f32(ptr addrspace(1) inreg n
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB4_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
-; GFX942-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
-; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1]
; GFX942-NEXT: .LBB4_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -149,6 +152,7 @@ define <8 x i16> @uniform_masked_load_ptr1_mask_v8i16(ptr addrspace(1) inreg noc
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB5_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-NEXT: .LBB5_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -174,6 +178,7 @@ define <8 x half> @uniform_masked_load_ptr1_mask_v8f16(ptr addrspace(1) inreg no
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB6_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-NEXT: .LBB6_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -199,6 +204,7 @@ define <8 x bfloat> @uniform_masked_load_ptr1_mask_v8bf16(ptr addrspace(1) inreg
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB7_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX942-NEXT: .LBB7_2:
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
@@ -236,7 +242,8 @@ define <16 x i8> @uniform_masked_load_ptr1_mask_v16i8(ptr addrspace(1) inreg noc
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB8_2
; GFX942-NEXT: ; %bb.1: ; %cond.load
-; GFX942-NEXT: global_load_dwordx4 v[16:19], v16, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-NEXT: global_load_dwordx4 v[16:19], v0, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_lshrrev_b32_e32 v15, 24, v19
; GFX942-NEXT: v_lshrrev_b32_e32 v14, 16, v19
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
index faf70f55876f7..62d02e7042510 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
@@ -8,33 +8,34 @@ define void @issue63986(i64 %0, i64 %idxprom, ptr inreg %ptr) {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshlrev_b64 v[4:5], 6, v[2:3]
-; CHECK-NEXT: v_mov_b32_e32 v6, s17
-; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s16, v4
-; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v6, v5, vcc
+; CHECK-NEXT: v_mov_b32_e32 v7, s17
+; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s16, v4
+; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v5, vcc
; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: .LBB0_1: ; %dynamic-memcpy-expansion-main-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v7, s5
-; CHECK-NEXT: v_mov_b32_e32 v6, s4
-; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[6:7]
-; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s4, v8
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: v_mov_b32_e32 v5, s5
+; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[4:5]
+; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, s4, v6
; CHECK-NEXT: s_add_u32 s4, s4, 16
; CHECK-NEXT: s_addc_u32 s5, s5, 0
; CHECK-NEXT: v_cmp_lt_u64_e64 s[6:7], s[4:5], 32
-; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v7, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v5, vcc
; CHECK-NEXT: s_and_b64 vcc, exec, s[6:7]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[10:13]
+; CHECK-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %dynamic-memcpy-expansion-residual-cond
; CHECK-NEXT: s_branch .LBB0_4
; CHECK-NEXT: ; %bb.3:
-; CHECK-NEXT: ; implicit-def: $vgpr6_vgpr7
+; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
; CHECK-NEXT: s_branch .LBB0_5
; CHECK-NEXT: .LBB0_4: ; %dynamic-memcpy-expansion-residual-cond.dynamic-memcpy-post-expansion_crit_edge
-; CHECK-NEXT: v_lshlrev_b64 v[6:7], 6, v[2:3]
-; CHECK-NEXT: s_cbranch_execnz .LBB0_8
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], 6, v[2:3]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_7
; CHECK-NEXT: .LBB0_5: ; %dynamic-memcpy-expansion-residual-body.preheader
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], 6, v[2:3]
; CHECK-NEXT: s_add_u32 s4, s16, 32
; CHECK-NEXT: s_addc_u32 s5, s17, 0
; CHECK-NEXT: v_mov_b32_e32 v3, s5
@@ -44,97 +45,95 @@ define void @issue63986(i64 %0, i64 %idxprom, ptr inreg %ptr) {
; CHECK-NEXT: ; %bb.6: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: s_add_u32 s6, 32, s4
; CHECK-NEXT: s_addc_u32 s7, 0, s5
-; CHECK-NEXT: v_mov_b32_e32 v6, s6
-; CHECK-NEXT: v_mov_b32_e32 v7, s7
-; CHECK-NEXT: flat_load_ubyte v10, v[6:7]
-; CHECK-NEXT: v_mov_b32_e32 v7, s5
-; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s4, v2
-; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v3, v7, vcc
+; CHECK-NEXT: v_mov_b32_e32 v9, s7
+; CHECK-NEXT: v_mov_b32_e32 v8, s6
+; CHECK-NEXT: flat_load_ubyte v10, v[8:9]
+; CHECK-NEXT: v_mov_b32_e32 v9, s5
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s4, v2
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v3, v9, vcc
; CHECK-NEXT: s_add_u32 s4, s4, 1
; CHECK-NEXT: s_addc_u32 s5, 0, s5
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: flat_store_byte v[6:7], v10
-; CHECK-NEXT: ; %bb.7:
-; CHECK-NEXT: v_mov_b32_e32 v7, v5
-; CHECK-NEXT: v_mov_b32_e32 v6, v4
-; CHECK-NEXT: .LBB0_8: ; %dynamic-memcpy-post-expansion
+; CHECK-NEXT: flat_store_byte v[8:9], v10
+; CHECK-NEXT: .LBB0_7: ; %dynamic-memcpy-post-expansion
; CHECK-NEXT: v_and_b32_e32 v2, 15, v0
; CHECK-NEXT: v_and_b32_e32 v0, -16, v0
-; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, v6, v0
+; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, v4, v0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
-; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v1, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v1, vcc
; CHECK-NEXT: v_cmp_ne_u64_e64 s[4:5], 0, v[0:1]
; CHECK-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[2:3]
-; CHECK-NEXT: v_mov_b32_e32 v6, s17
+; CHECK-NEXT: v_mov_b32_e32 v8, s17
; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, s16, v4
-; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; CHECK-NEXT: s_branch .LBB0_11
-; CHECK-NEXT: .LBB0_9: ; %Flow14
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
+; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
+; CHECK-NEXT: s_branch .LBB0_10
+; CHECK-NEXT: .LBB0_8: ; %Flow14
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
; CHECK-NEXT: s_or_b64 exec, exec, s[10:11]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
-; CHECK-NEXT: .LBB0_10: ; %Flow16
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
+; CHECK-NEXT: .LBB0_9: ; %Flow16
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
; CHECK-NEXT: s_andn2_b64 vcc, exec, s[8:9]
-; CHECK-NEXT: s_cbranch_vccz .LBB0_18
-; CHECK-NEXT: .LBB0_11: ; %while.cond
+; CHECK-NEXT: s_cbranch_vccz .LBB0_17
+; CHECK-NEXT: .LBB0_10: ; %while.cond
; CHECK-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NEXT: ; Child Loop BB0_13 Depth 2
-; CHECK-NEXT: ; Child Loop BB0_17 Depth 2
+; CHECK-NEXT: ; Child Loop BB0_12 Depth 2
+; CHECK-NEXT: ; Child Loop BB0_16 Depth 2
; CHECK-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
-; CHECK-NEXT: s_cbranch_execz .LBB0_14
-; CHECK-NEXT: ; %bb.12: ; %dynamic-memcpy-expansion-main-body2.preheader
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
+; CHECK-NEXT: s_cbranch_execz .LBB0_13
+; CHECK-NEXT: ; %bb.11: ; %dynamic-memcpy-expansion-main-body2.preheader
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
; CHECK-NEXT: s_mov_b64 s[10:11], 0
; CHECK-NEXT: s_mov_b64 s[12:13], 0
-; CHECK-NEXT: .LBB0_13: ; %dynamic-memcpy-expansion-main-body2
-; CHECK-NEXT: ; Parent Loop BB0_11 Depth=1
+; CHECK-NEXT: .LBB0_12: ; %dynamic-memcpy-expansion-main-body2
+; CHECK-NEXT: ; Parent Loop BB0_10 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NEXT: v_mov_b32_e32 v6, s10
-; CHECK-NEXT: v_mov_b32_e32 v7, s11
-; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[6:7]
-; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s10, v8
+; CHECK-NEXT: v_mov_b32_e32 v8, s10
+; CHECK-NEXT: v_mov_b32_e32 v9, s11
+; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
+; CHECK-NEXT: v_mov_b32_e32 v13, s11
+; CHECK-NEXT: v_add_co_u32_e32 v12, vcc, s10, v6
; CHECK-NEXT: s_add_u32 s10, s10, 16
-; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v7, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v13, vcc, v7, v13, vcc
; CHECK-NEXT: s_addc_u32 s11, s11, 0
; CHECK-NEXT: v_cmp_ge_u64_e32 vcc, s[10:11], v[0:1]
; CHECK-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[10:13]
+; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[12:13]
-; CHECK-NEXT: s_cbranch_execnz .LBB0_13
-; CHECK-NEXT: .LBB0_14: ; %Flow15
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
+; CHECK-NEXT: s_cbranch_execnz .LBB0_12
+; CHECK-NEXT: .LBB0_13: ; %Flow15
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
; CHECK-NEXT: s_or_b64 exec, exec, s[8:9]
; CHECK-NEXT: s_mov_b64 s[8:9], -1
-; CHECK-NEXT: s_cbranch_execz .LBB0_10
-; CHECK-NEXT: ; %bb.15: ; %dynamic-memcpy-expansion-residual-cond5
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
-; CHECK-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_9
-; CHECK-NEXT: ; %bb.16: ; %dynamic-memcpy-expansion-residual-body4.preheader
-; CHECK-NEXT: ; in Loop: Header=BB0_11 Depth=1
+; CHECK-NEXT: ; %bb.14: ; %dynamic-memcpy-expansion-residual-cond5
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
+; CHECK-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
+; CHECK-NEXT: s_cbranch_execz .LBB0_8
+; CHECK-NEXT: ; %bb.15: ; %dynamic-memcpy-expansion-residual-body4.preheader
+; CHECK-NEXT: ; in Loop: Header=BB0_10 Depth=1
; CHECK-NEXT: s_mov_b64 s[12:13], 0
; CHECK-NEXT: s_mov_b64 s[14:15], 0
-; CHECK-NEXT: .LBB0_17: ; %dynamic-memcpy-expansion-residual-body4
-; CHECK-NEXT: ; Parent Loop BB0_11 Depth=1
+; CHECK-NEXT: .LBB0_16: ; %dynamic-memcpy-expansion-residual-body4
+; CHECK-NEXT: ; Parent Loop BB0_10 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NEXT: v_mov_b32_e32 v10, s13
-; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s12, v0
-; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v10, vcc
-; CHECK-NEXT: flat_load_ubyte v11, v[6:7]
-; CHECK-NEXT: v_add_co_u32_e32 v6, vcc, s12, v4
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s12, v0
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v10, vcc
+; CHECK-NEXT: flat_load_ubyte v11, v[8:9]
+; CHECK-NEXT: v_add_co_u32_e32 v8, vcc, s12, v4
; CHECK-NEXT: s_add_u32 s12, s12, 1
; CHECK-NEXT: s_addc_u32 s13, s13, 0
; CHECK-NEXT: v_cmp_ge_u64_e64 s[8:9], s[12:13], v[2:3]
-; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v10, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v10, vcc
; CHECK-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: flat_store_byte v[6:7], v11
+; CHECK-NEXT: flat_store_byte v[8:9], v11
; CHECK-NEXT: s_andn2_b64 exec, exec, s[14:15]
-; CHECK-NEXT: s_cbranch_execnz .LBB0_17
-; CHECK-NEXT: s_branch .LBB0_9
-; CHECK-NEXT: .LBB0_18: ; %DummyReturnBlock
+; CHECK-NEXT: s_cbranch_execnz .LBB0_16
+; CHECK-NEXT: s_branch .LBB0_8
+; CHECK-NEXT: .LBB0_17: ; %DummyReturnBlock
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
index 990a986ffab75..d5285160061de 100644
--- a/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+++ b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
@@ -1779,10 +1779,10 @@ define void @memset_p1_varsz_align_4_set0(ptr addrspace(1) align 4 %dst, i64 %si
; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-SDAG-NEXT: s_cbranch_execz .LBB13_3
; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v5
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v5
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v5
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v5
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v8
; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0
; GFX942-SDAG-NEXT: .LBB13_2: ; %dynamic-memset-expansion-main-body
; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-second-cmp-cse.mir b/llvm/test/CodeGen/AMDGPU/preserve-second-cmp-cse.mir
new file mode 100644
index 0000000000000..92712f824c19b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/preserve-second-cmp-cse.mir
@@ -0,0 +1,66 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+wavefrontsize64 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: preserve_second_cmp_cse
+tracksRegLiveness: true
+legalized: true
+regBankSelected: true
+selected: true
+body: |
+ ; CHECK-LABEL: name: preserve_second_cmp_cse
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0, $sgpr0, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK killed [[V_CMP_GT_U32_e64_]], [[COPY2]], implicit-def dead $scc
+ ; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_GT_U32_e64_1]], $exec, implicit-def $scc
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $vgpr0, $sgpr0, $sgpr2_sgpr3
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = COPY $sgpr0
+ %2:sreg_64 = COPY $sgpr2_sgpr3
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ %3:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
+ %4:sreg_64 = SI_IF_BREAK killed %3:sreg_64, %2:sreg_64, implicit-def dead $scc
+ SI_LOOP %4:sreg_64, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ SI_END_CF %4:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ %5:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
+ %6:sreg_64 = S_AND_B64 %5:sreg_64, $exec, implicit-def $scc
+ S_BRANCH %bb.3
+
+ bb.3:
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
index 80b5536b7e160..b9206e95b5c01 100644
--- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
@@ -41,11 +41,11 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
; GFX9-NEXT: v_ffbh_u32_e32 v7, v23
; GFX9-NEXT: v_add_u32_e32 v7, 32, v7
-; GFX9-NEXT: v_ffbh_u32_e32 v8, v22
-; GFX9-NEXT: v_min_u32_e32 v7, v7, v8
+; GFX9-NEXT: v_ffbh_u32_e32 v9, v22
+; GFX9-NEXT: v_min_u32_e32 v7, v7, v9
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 64, v7
-; GFX9-NEXT: v_addc_co_u32_e64 v8, s[6:7], 0, 0, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_ffbh_u32_e32 v10, v3
; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
@@ -56,46 +56,46 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v10, 32, v10
; GFX9-NEXT: v_ffbh_u32_e32 v11, v1
; GFX9-NEXT: v_min_u32_e32 v10, v10, v11
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 64, v10
; GFX9-NEXT: v_addc_co_u32_e64 v11, s[6:7], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v6, v7
-; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v8, v11, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v9, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v9, v11, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, 0, v8, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v8, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[6:7]
+; GFX9-NEXT: v_or_b32_e32 v13, v7, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_mov_b32_e32 v21, v20
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
-; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
-; GFX9-NEXT: v_xor_b32_e32 v10, 0x7f, v6
-; GFX9-NEXT: v_or_b32_e32 v11, v7, v9
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX9-NEXT: v_xor_b32_e32 v8, 0x7f, v6
+; GFX9-NEXT: v_or_b32_e32 v12, v8, v10
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
-; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; GFX9-NEXT: v_cndmask_b32_e64 v13, v3, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v1, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v0, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v3, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v2, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v1, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v0, 0, s[4:5]
; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_6
; GFX9-NEXT: ; %bb.1: ; %udiv-bb1
; GFX9-NEXT: v_add_co_u32_e32 v24, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v7, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v10, vcc
; GFX9-NEXT: v_sub_u32_e32 v13, 0x7f, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, 0, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, 0, v11, vcc
; GFX9-NEXT: v_sub_u32_e32 v11, 64, v13
; GFX9-NEXT: v_or_b32_e32 v8, v25, v27
; GFX9-NEXT: v_or_b32_e32 v7, v24, v26
@@ -105,18 +105,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[0:1]
; GFX9-NEXT: v_or_b32_e32 v8, v10, v12
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v13
+; GFX9-NEXT: v_or_b32_e32 v10, v9, v11
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[8:9], v13, v[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v13
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v3, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v2, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v9, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v7, v3, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v6, v10, s[4:5]
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], v13, v[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v2, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, v7, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v10, 0
; GFX9-NEXT: v_mov_b32_e32 v11, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_5
@@ -131,49 +131,49 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_lshrrev_b64 v[10:11], v10, v[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v24
; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v15, v11, v1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v11, v1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc
; GFX9-NEXT: v_lshrrev_b64 v[10:11], v24, v[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v14, v12, v0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v11, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v15, 0, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v10, vcc
; GFX9-NEXT: v_add_co_u32_e32 v28, vcc, -1, v23
; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v22, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v30, vcc, -1, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v31, vcc, -1, v5, vcc
-; GFX9-NEXT: v_mov_b32_e32 v12, 0
-; GFX9-NEXT: v_mov_b32_e32 v13, 0
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v18, 0
; GFX9-NEXT: v_mov_b32_e32 v19, 0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mov_b32_e32 v17, 0
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: .LBB0_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshrrev_b32_e32 v32, 31, v15
-; GFX9-NEXT: v_lshlrev_b64 v[14:15], 1, v[14:15]
-; GFX9-NEXT: v_lshrrev_b32_e32 v33, 31, v7
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 31, v13
+; GFX9-NEXT: v_lshlrev_b64 v[12:13], 1, v[12:13]
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 31, v9
-; GFX9-NEXT: v_lshlrev_b64 v[16:17], 1, v[16:17]
+; GFX9-NEXT: v_lshlrev_b64 v[14:15], 1, v[14:15]
+; GFX9-NEXT: v_or_b32_e32 v10, v12, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v12, vcc, v28, v10
; GFX9-NEXT: v_or_b32_e32 v14, v14, v33
-; GFX9-NEXT: v_or3_b32 v6, v6, v10, v12
-; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, v28, v14
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v32
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v29, v15, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v30, v16, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v29, v13, vcc
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v31, v17, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v10, 31, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v18, v8
-; GFX9-NEXT: v_and_b32_e32 v18, v10, v23
-; GFX9-NEXT: v_or_b32_e32 v9, v19, v9
-; GFX9-NEXT: v_and_b32_e32 v19, v10, v22
-; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v14, v18
-; GFX9-NEXT: v_and_b32_e32 v32, v10, v4
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v19, vcc
-; GFX9-NEXT: v_and_b32_e32 v33, v10, v5
-; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v16, v32, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v17, v33, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v30, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 31, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v31, v15, vcc
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX9-NEXT: v_or3_b32 v8, v8, v32, v16
+; GFX9-NEXT: v_ashrrev_i32_e32 v32, 31, v12
+; GFX9-NEXT: v_and_b32_e32 v12, v32, v23
+; GFX9-NEXT: v_or_b32_e32 v6, v18, v6
+; GFX9-NEXT: v_and_b32_e32 v18, v32, v22
+; GFX9-NEXT: v_sub_co_u32_e32 v12, vcc, v10, v12
+; GFX9-NEXT: v_or_b32_e32 v7, v19, v7
+; GFX9-NEXT: v_and_b32_e32 v19, v32, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v13, vcc, v13, v18, vcc
+; GFX9-NEXT: v_and_b32_e32 v33, v32, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v14, v19, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v33, vcc
; GFX9-NEXT: v_add_co_u32_e32 v24, vcc, -1, v24
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
@@ -181,9 +181,11 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_or_b32_e32 v18, v24, v26
; GFX9-NEXT: v_or_b32_e32 v19, v25, v27
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
-; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX9-NEXT: v_and_b32_e32 v10, 1, v32
; GFX9-NEXT: v_mov_b32_e32 v19, v11
-; GFX9-NEXT: v_or3_b32 v7, v7, 0, v13
+; GFX9-NEXT: v_or3_b32 v9, v9, 0, v17
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mov_b32_e32 v17, 0
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v18, v10
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
@@ -192,36 +194,36 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: .LBB0_5: ; %Flow2
; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX9-NEXT: v_lshlrev_b64 v[12:13], 1, v[6:7]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[8:9]
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 31, v9
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v7
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v6
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 31, v7
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v12
+; GFX9-NEXT: v_or_b32_e32 v12, v11, v7
+; GFX9-NEXT: v_or_b32_e32 v13, v10, v6
; GFX9-NEXT: .LBB0_6: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
-; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v23, v10, 0
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
-; GFX9-NEXT: v_mul_lo_u32 v9, v11, v4
-; GFX9-NEXT: v_mul_lo_u32 v16, v10, v5
-; GFX9-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v22, v10, v[7:8]
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v4, 0
-; GFX9-NEXT: v_mul_lo_u32 v10, v12, v22
-; GFX9-NEXT: v_mul_lo_u32 v13, v13, v23
-; GFX9-NEXT: v_mov_b32_e32 v7, v14
-; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v23, v11, v[7:8]
-; GFX9-NEXT: v_add3_u32 v5, v5, v16, v9
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v23, v[4:5]
-; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v15, v8
-; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, 0, vcc
-; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v22, v11, v[8:9]
-; GFX9-NEXT: v_add3_u32 v5, v13, v5, v10
-; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v6
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v7, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v23, v13, 0
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
+; GFX9-NEXT: v_mul_lo_u32 v17, v13, v5
+; GFX9-NEXT: v_mul_lo_u32 v7, v12, v4
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v22, v13, v[15:16]
+; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v4, 0
+; GFX9-NEXT: v_mul_lo_u32 v13, v8, v22
+; GFX9-NEXT: v_mul_lo_u32 v9, v9, v23
+; GFX9-NEXT: v_mov_b32_e32 v15, v5
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v23, v12, v[15:16]
+; GFX9-NEXT: v_add3_u32 v11, v11, v17, v7
+; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v8, v23, v[10:11]
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e64 v6, s[4:5], 0, 0, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v22, v12, v[5:6]
+; GFX9-NEXT: v_add3_u32 v8, v9, v8, v13
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v14
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v20
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v21
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v20
@@ -1564,61 +1566,63 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_lshrrev_b64 v[12:13], v12, v[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v22
; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v17, v13, v1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v13, v1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v14, v12, v14, vcc
; GFX9-NEXT: v_lshrrev_b64 v[12:13], v22, v[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v16, v14, v0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v12, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v13, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v26, vcc, -1, v4
; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v7, vcc
-; GFX9-NEXT: v_mov_b32_e32 v14, 0
-; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: v_mov_b32_e32 v18, 0
+; GFX9-NEXT: v_mov_b32_e32 v19, 0
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v20, 0
; GFX9-NEXT: v_mov_b32_e32 v21, 0
; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: .LBB1_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshlrev_b64 v[30:31], 1, v[10:11]
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 31, v11
-; GFX9-NEXT: v_or_b32_e32 v10, v20, v30
-; GFX9-NEXT: v_lshrrev_b32_e32 v20, 31, v17
-; GFX9-NEXT: v_lshlrev_b64 v[16:17], 1, v[16:17]
-; GFX9-NEXT: v_or_b32_e32 v11, v21, v31
-; GFX9-NEXT: v_lshlrev_b64 v[18:19], 1, v[18:19]
-; GFX9-NEXT: v_lshrrev_b32_e32 v21, 31, v9
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v21
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v20
-; GFX9-NEXT: v_sub_co_u32_e32 v20, vcc, v26, v16
-; GFX9-NEXT: v_subb_co_u32_e32 v20, vcc, v27, v17, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v20, vcc, v28, v18, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v20, vcc, v29, v19, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v30, 31, v20
-; GFX9-NEXT: v_and_b32_e32 v20, v30, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 31, v9
; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
-; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v16, v20
-; GFX9-NEXT: v_and_b32_e32 v20, v30, v5
-; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v17, v20, vcc
-; GFX9-NEXT: v_or3_b32 v8, v8, v12, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 31, v11
+; GFX9-NEXT: v_or3_b32 v8, v8, v30, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 31, v15
+; GFX9-NEXT: v_lshlrev_b64 v[14:15], 1, v[14:15]
+; GFX9-NEXT: v_lshlrev_b64 v[16:17], 1, v[16:17]
+; GFX9-NEXT: v_or_b32_e32 v12, v14, v12
+; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v26, v12
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v20
+; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v27, v15, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v28, v16, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v29, v17, vcc
+; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-NEXT: v_ashrrev_i32_e32 v30, 31, v14
+; GFX9-NEXT: v_and_b32_e32 v14, v30, v4
+; GFX9-NEXT: v_or_b32_e32 v10, v18, v10
+; GFX9-NEXT: v_and_b32_e32 v18, v30, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v12, v14
+; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v18, vcc
; GFX9-NEXT: v_and_b32_e32 v12, v30, v6
-; GFX9-NEXT: v_and_b32_e32 v20, v30, v7
-; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v18, v12, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v19, v20, vcc
+; GFX9-NEXT: v_and_b32_e32 v18, v30, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v16, v12, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v17, v18, vcc
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, -1, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
-; GFX9-NEXT: v_or_b32_e32 v20, v22, v24
-; GFX9-NEXT: v_or_b32_e32 v21, v23, v25
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[20:21]
+; GFX9-NEXT: v_or_b32_e32 v11, v19, v11
+; GFX9-NEXT: v_or_b32_e32 v18, v22, v24
+; GFX9-NEXT: v_or_b32_e32 v19, v23, v25
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
; GFX9-NEXT: v_and_b32_e32 v12, 1, v30
-; GFX9-NEXT: v_mov_b32_e32 v21, v13
-; GFX9-NEXT: v_or3_b32 v9, v9, 0, v15
+; GFX9-NEXT: v_mov_b32_e32 v19, v13
+; GFX9-NEXT: v_or3_b32 v9, v9, 0, v21
+; GFX9-NEXT: v_mov_b32_e32 v20, 0
+; GFX9-NEXT: v_mov_b32_e32 v21, 0
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v20, v12
+; GFX9-NEXT: v_mov_b32_e32 v18, v12
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB1_3
; GFX9-NEXT: ; %bb.4: ; %Flow
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
index 40b6f0262f979..6073807f46530 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
@@ -161,13 +161,13 @@ define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(ptr addrspace(1) %out, p
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc
; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11]
; SI-NEXT: s_cbranch_execz .LBB3_2
; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
@@ -182,6 +182,7 @@ define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(ptr addrspace(1) %out, p
; SI-NEXT: s_mov_b32 s15, 0xf000
; SI-NEXT: s_mov_b32 s14, 0
; SI-NEXT: s_mov_b64 s[12:13], s[2:3]
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index b5474b8974b29..03c7c4fd55277 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -9750,27 +9750,27 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_add_u32 s40, s40, s11
; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
; GFX6-NEXT: s_addc_u32 s41, s41, 0
-; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, -1, v0
-; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v5, -1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], exec
; GFX6-NEXT: s_mov_b32 s6, 0
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: buffer_store_dword v1, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_writelane_b32 v1, s0, 0
-; GFX6-NEXT: v_writelane_b32 v1, s1, 1
-; GFX6-NEXT: v_writelane_b32 v1, s2, 2
-; GFX6-NEXT: v_writelane_b32 v1, s3, 3
+; GFX6-NEXT: v_writelane_b32 v0, s0, 0
+; GFX6-NEXT: v_writelane_b32 v0, s1, 1
+; GFX6-NEXT: v_writelane_b32 v0, s2, 2
+; GFX6-NEXT: v_writelane_b32 v0, s3, 3
; GFX6-NEXT: s_mov_b32 s8, 0x80400
-; GFX6-NEXT: buffer_store_dword v1, off, s[40:43], s8 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s8 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v1, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[4:5]
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
-; GFX6-NEXT: v_lshlrev_b32_e32 v5, 8, v0
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:240
+; GFX6-NEXT: v_lshlrev_b32_e32 v6, 8, v5
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:240
; GFX6-NEXT: s_mov_b32 s2, 0x86a00
; GFX6-NEXT: s_mov_b64 s[8:9], exec
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -9779,7 +9779,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:224
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:224
; GFX6-NEXT: s_mov_b32 s2, 0x86600
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9787,7 +9787,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:208
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:208
; GFX6-NEXT: s_mov_b32 s2, 0x86200
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9795,7 +9795,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:192
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:192
; GFX6-NEXT: s_mov_b32 s2, 0x85e00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9803,7 +9803,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:176
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:176
; GFX6-NEXT: s_mov_b32 s2, 0x85a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9811,7 +9811,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:160
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:160
; GFX6-NEXT: s_mov_b32 s2, 0x85600
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9819,7 +9819,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:144
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:144
; GFX6-NEXT: s_mov_b32 s2, 0x85200
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9827,7 +9827,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:128
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:128
; GFX6-NEXT: s_mov_b32 s2, 0x84e00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9835,7 +9835,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:112
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:112
; GFX6-NEXT: s_mov_b32 s2, 0x84a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9843,7 +9843,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:96
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:96
; GFX6-NEXT: s_mov_b32 s2, 0x84600
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9851,7 +9851,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:80
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:80
; GFX6-NEXT: s_mov_b32 s2, 0x84200
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9859,7 +9859,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64 offset:64
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64 offset:64
; GFX6-NEXT: s_mov_b32 s2, 0x83a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -9867,22 +9867,22 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[5:6], s[4:7], 0 addr64
-; GFX6-NEXT: buffer_load_dwordx4 v[7:10], v[5:6], s[4:7], 0 addr64 offset:16
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[6:7], s[4:7], 0 addr64
+; GFX6-NEXT: buffer_load_dwordx4 v[8:11], v[6:7], s[4:7], 0 addr64 offset:16
; GFX6-NEXT: s_mov_b32 s2, 0x83200
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dword v7, off, s[40:43], s2 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v10, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s2 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v10, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v11, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dwordx4 v[7:10], v[5:6], s[4:7], 0 addr64 offset:32
+; GFX6-NEXT: buffer_load_dwordx4 v[8:11], v[6:7], s[4:7], 0 addr64 offset:32
; GFX6-NEXT: s_mov_b32 s2, 0x83600
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dword v7, off, s[40:43], s2 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v10, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s2 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v10, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v11, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX6-NEXT: s_mov_b64 exec, 15
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
@@ -9897,19 +9897,19 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[8:9]
-; GFX6-NEXT: buffer_load_dwordx4 v[7:10], v[5:6], s[4:7], 0 addr64 offset:48
+; GFX6-NEXT: buffer_load_dwordx4 v[6:9], v[6:7], s[4:7], 0 addr64 offset:48
; GFX6-NEXT: s_mov_b32 s0, 0x83e00
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 13, v0
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 16, v4
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dword v7, off, s[40:43], s0 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v6, off, s[40:43], s0 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Spill
+; GFX6-NEXT: buffer_store_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(3)
-; GFX6-NEXT: v_mov_b32_e32 v7, 1
+; GFX6-NEXT: v_mov_b32_e32 v6, 1
; GFX6-NEXT: s_mov_b64 s[0:1], exec
-; GFX6-NEXT: buffer_store_dword v7, v4, s[40:43], 0 offen
+; GFX6-NEXT: buffer_store_dword v6, v4, s[40:43], 0 offen
; GFX6-NEXT: ;;#ASMSTART
; GFX6-NEXT: ; def s[4:11]
; GFX6-NEXT: ;;#ASMEND
@@ -10122,9 +10122,9 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_mov_b64 s[44:45], exec
; GFX6-NEXT: s_mov_b64 exec, 3
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x20c0
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x20c0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, v7, s[40:43], 0 offen ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v4, v6, s[40:43], 0 offen ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_readlane_b32 s34, v4, 0
; GFX6-NEXT: v_readlane_b32 s35, v4, 1
@@ -10180,192 +10180,196 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[4:5]
; GFX6-NEXT: s_mov_b32 s0, 0x86a00
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b64 s[38:39], s[2:3]
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 8, v5
+; GFX6-NEXT: v_mov_b32_e32 v5, 0
; GFX6-NEXT: s_mov_b32 s0, 0x86600
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:240
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:240
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x86200
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:224
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:224
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x85e00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:208
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:208
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x85a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:192
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:192
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x85600
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:176
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:176
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x85200
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:160
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:160
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x84e00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:144
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:144
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x84a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:128
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:128
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x84600
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:112
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:112
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x84200
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:96
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:96
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x83a00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:80
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:80
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x83e00
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:64
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:64
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x83600
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:48
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b32 s0, 0x83200
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:32
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
-; GFX6-NEXT: buffer_load_dword v10, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s0 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s0 offset:4 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s0 offset:8 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s0 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dwordx4 v[7:10], v[5:6], s[36:39], 0 addr64 offset:16
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], v[5:6], s[36:39], 0 addr64
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[36:39], 0 addr64 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[36:39], 0 addr64
; GFX6-NEXT: s_endpgm
;
; GFX9-FLATSCR-LABEL: test_limited_sgpr:
; GFX9-FLATSCR: ; %bb.0: ; %entry
; GFX9-FLATSCR-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x24
; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v5, 8, v0
+; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v5, -1, v0
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v0, 8, v5
; GFX9-FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:240
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:240
; GFX9-FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2070
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 1
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:224
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2060
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:208
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2050
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 16
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v5, s[38:39] offset:144
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:224
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:192
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2040
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:208
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:176
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2030
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[19:22], v5, s[38:39] offset:192
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[15:18], v5, s[38:39] offset:176
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:160
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:160
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2020
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2070
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v5, s[38:39] offset:128
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:112
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:144
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:128
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2010
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:112
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:96
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[15:18], v0, s[38:39] offset:96
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:80
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[11:14], v5, s[38:39] offset:32
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v5, s[38:39] offset:16
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(2)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:80
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:64
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[11:14], v0, s[38:39] offset:64
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:48
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39] offset:48
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[7:10], v0, s[38:39] offset:32
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:16
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2080
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2060
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[7:10], v5, s[38:39]
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 1
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v0, s[38:39]
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 16
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: v_lshl_add_u32 v4, v7, 13, v4
-; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX9-FLATSCR-NEXT: v_lshl_add_u32 v4, v0, 13, v4
+; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-FLATSCR-NEXT: scratch_store_dword v4, v6, off
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ; def s[0:7]
@@ -10395,26 +10399,26 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: ; use s[0:7],s[8:15],s[16:23],s[24:31],s[40:43],s[38:39]
; GFX9-FLATSCR-NEXT: ;;#ASMEND
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20d0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[15:18], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20e0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[19:22], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20f0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v11
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[7:10], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v12
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v13
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20f0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v15
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v16
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v17
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v18
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ;;#ASMEND
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[11:14], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20e0
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[19:22], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, v3
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20d0
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[15:18], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, v3
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, v2
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, v1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, v0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, v2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v0
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ;;#ASMEND
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
@@ -10430,57 +10434,58 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: .LBB1_2: ; %ret
; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[34:35]
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[19:22], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v4, 8, v5
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:112
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:96
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[19:22], s[36:37] offset:112
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[15:18], s[36:37] offset:96
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[15:18], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:80
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[15:18], s[36:37] offset:80
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[11:14], s[36:37] offset:64
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[11:14], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2080
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:64
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[11:14], s[36:37] offset:48
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[7:10], s[36:37] offset:32
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[5:8], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2070
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[5:8], s[36:37] offset:16
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37]
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2060
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:48
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[11:14], s[36:37] offset:32
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[11:14], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:240
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2050
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[11:14], s[36:37] offset:16
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[7:10], s[36:37]
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[6:9], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:224
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2040
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[6:9], s[36:37] offset:240
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[6:9], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:208
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2030
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[6:9], s[36:37] offset:224
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[6:9], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:192
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2020
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:176
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2070
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[6:9], s[36:37] offset:208
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[19:22], s[36:37] offset:192
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[15:18], s[36:37] offset:176
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(3)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:160
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:160
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2010
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:144
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:144
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37] offset:128
+; GFX9-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37] offset:128
; GFX9-FLATSCR-NEXT: s_endpgm
;
; GFX10-FLATSCR-LABEL: test_limited_sgpr:
@@ -10493,26 +10498,26 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v6, 1
; GFX10-FLATSCR-NEXT: s_mov_b32 s33, exec_lo
-; GFX10-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v5, 8, v0
+; GFX10-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v5, -1, v0
+; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v0, 8, v5
; GFX10-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-FLATSCR-NEXT: s_clause 0xf
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[35:38], v5, s[38:39] offset:240
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[31:34], v5, s[38:39] offset:224
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[27:30], v5, s[38:39] offset:208
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[23:26], v5, s[38:39] offset:192
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[19:22], v5, s[38:39] offset:176
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[15:18], v5, s[38:39] offset:160
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[11:14], v5, s[38:39] offset:144
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[7:10], v5, s[38:39] offset:128
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[63:66], v5, s[38:39] offset:112
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[59:62], v5, s[38:39] offset:96
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[55:58], v5, s[38:39] offset:80
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[51:54], v5, s[38:39] offset:64
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[47:50], v5, s[38:39] offset:48
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[43:46], v5, s[38:39] offset:32
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[39:42], v5, s[38:39] offset:16
-; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[38:39]
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[35:38], v0, s[38:39] offset:240
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[31:34], v0, s[38:39] offset:224
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[27:30], v0, s[38:39] offset:208
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[23:26], v0, s[38:39] offset:192
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[19:22], v0, s[38:39] offset:176
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[15:18], v0, s[38:39] offset:160
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[11:14], v0, s[38:39] offset:144
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[7:10], v0, s[38:39] offset:128
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[63:66], v0, s[38:39] offset:112
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[59:62], v0, s[38:39] offset:96
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[55:58], v0, s[38:39] offset:80
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[51:54], v0, s[38:39] offset:64
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[47:50], v0, s[38:39] offset:48
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[43:46], v0, s[38:39] offset:32
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[39:42], v0, s[38:39] offset:16
+; GFX10-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v0, s[38:39]
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX10-FLATSCR-NEXT: v_lshl_add_u32 v4, v0, 13, 16
; GFX10-FLATSCR-NEXT: scratch_store_dword v4, v6, off
@@ -10674,23 +10679,24 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: ;;#ASMEND
; GFX10-FLATSCR-NEXT: .LBB1_2: ; %ret
; GFX10-FLATSCR-NEXT: s_or_b32 exec_lo, exec_lo, s33
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[63:66], s[36:37] offset:112
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[59:62], s[36:37] offset:96
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[55:58], s[36:37] offset:80
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[51:54], s[36:37] offset:64
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[47:50], s[36:37] offset:48
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[43:46], s[36:37] offset:32
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[39:42], s[36:37] offset:16
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[36:37]
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[35:38], s[36:37] offset:240
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[31:34], s[36:37] offset:224
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[27:30], s[36:37] offset:208
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[23:26], s[36:37] offset:192
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[19:22], s[36:37] offset:176
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[15:18], s[36:37] offset:160
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[11:14], s[36:37] offset:144
-; GFX10-FLATSCR-NEXT: global_store_dwordx4 v5, v[7:10], s[36:37] offset:128
+; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v4, 8, v5
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[63:66], s[36:37] offset:112
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[59:62], s[36:37] offset:96
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[55:58], s[36:37] offset:80
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[51:54], s[36:37] offset:64
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[47:50], s[36:37] offset:48
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[43:46], s[36:37] offset:32
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[39:42], s[36:37] offset:16
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[0:3], s[36:37]
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[35:38], s[36:37] offset:240
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[31:34], s[36:37] offset:224
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[27:30], s[36:37] offset:208
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[23:26], s[36:37] offset:192
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[19:22], s[36:37] offset:176
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[15:18], s[36:37] offset:160
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[11:14], s[36:37] offset:144
+; GFX10-FLATSCR-NEXT: global_store_dwordx4 v4, v[7:10], s[36:37] offset:128
; GFX10-FLATSCR-NEXT: s_endpgm
entry:
%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index 802de8037cf6b..de65e547dcf68 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -32,7 +32,6 @@ define void @needs_align16_default_stack_align(i32 %idx) #0 {
; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN: ; ScratchSize: 144
%alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr addrspace(5) %gep0, align 16
@@ -71,7 +70,6 @@ define void @needs_align16_stack_align4(i32 %idx) #2 {
; GCN-NEXT: s_mov_b32 s34, s5
; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN: ; ScratchSize: 160
%alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr addrspace(5) %gep0, align 16
@@ -111,7 +109,6 @@ define void @needs_align32(i32 %idx) #0 {
; GCN-NEXT: s_mov_b32 s34, s5
; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN: ; ScratchSize: 192
%alloca.align16 = alloca [8 x <4 x i32>], align 32, addrspace(5)
%gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr addrspace(5) %gep0, align 32
@@ -138,7 +135,6 @@ define void @force_realign4(i32 %idx) #1 {
; GCN-NEXT: s_mov_b32 s34, s5
; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN: ; ScratchSize: 52
%alloca.align16 = alloca [8 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [8 x i32], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx
store volatile i32 3, ptr addrspace(5) %gep0, align 4
@@ -366,11 +362,11 @@ define i32 @needs_align1024_stack_args_used_inside_loop(ptr addrspace(5) nocaptu
; GCN-NEXT: s_cbranch_execz .LBB10_4
; GCN-NEXT: .LBB10_2: ; %loop_body
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen
+; GCN-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen
+; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s10, v0
-; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s10, v2
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT: s_cbranch_execz .LBB10_1
; GCN-NEXT: ; %bb.3: ; %loop_end
diff --git a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
index 485d7d3e75b62..a807619c7ae0d 100644
--- a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
+++ b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
@@ -27,7 +27,7 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: v_mov_b32_e32 v47, s5
; CHECK-NEXT: s_mov_b32 s5, s4
; CHECK-NEXT: s_addc_u32 s51, s35, 0
-; CHECK-NEXT: v_pk_mov_b32 v[62:63], s[4:5], s[4:5] op_sel:[0,1]
+; CHECK-NEXT: v_pk_mov_b32 v[60:61], s[4:5], s[4:5] op_sel:[0,1]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, G at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, G at gotpcrel32@hi+12
@@ -47,14 +47,14 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: s_mov_b32 s52, s15
; CHECK-NEXT: s_mov_b64 s[36:37], s[10:11]
; CHECK-NEXT: v_mov_b32_e32 v40, v0
-; CHECK-NEXT: v_mov_b32_e32 v60, s66
-; CHECK-NEXT: v_mov_b32_e32 v61, s67
-; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[62:63]
+; CHECK-NEXT: v_mov_b32_e32 v58, s66
+; CHECK-NEXT: v_mov_b32_e32 v59, s67
+; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[60:61]
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
-; CHECK-NEXT: flat_load_dwordx2 a[32:33], v[56:57]
-; CHECK-NEXT: v_mov_b32_e32 v58, 0
-; CHECK-NEXT: v_mov_b32_e32 v59, 0x3ff00000
+; CHECK-NEXT: flat_load_dwordx2 v[62:63], v[56:57]
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x3ff00000
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[8:9], s[50:51]
@@ -63,8 +63,8 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: s_mov_b32 s13, s52
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_mov_b32_e32 v31, v40
-; CHECK-NEXT: flat_store_dwordx2 v[44:45], v[58:59]
-; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[62:63]
+; CHECK-NEXT: flat_store_dwordx2 v[44:45], v[0:1]
+; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[60:61]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
@@ -72,12 +72,13 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s67
; CHECK-NEXT: v_mov_b32_e32 v0, s68
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 0, v42
-; CHECK-NEXT: flat_store_dwordx2 v[56:57], a[32:33]
+; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[62:63]
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[60:61]
+; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[58:59]
; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
-; CHECK-NEXT: buffer_store_dword v58, v0, s[0:3], 0 offen
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 0, v42
+; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll
index 1ad335a5a2d13..26d4305ca5a4d 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll
@@ -302,68 +302,69 @@ define amdgpu_kernel void @multi_vcond_loop(ptr addrspace(1) noalias nocapture %
; SI-LABEL: multi_vcond_loop:
; SI: ; %bb.0: ; %bb
; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v7, 0
+; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, 0
-; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
-; SI-NEXT: buffer_load_dword v0, v[6:7], s[8:11], 0 addr64
+; SI-NEXT: buffer_load_dword v1, v[1:2], s[8:11], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_lt_i32_e32 vcc, 0, v0
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1
; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT: s_cbranch_execz .LBB5_5
; SI-NEXT: ; %bb.1: ; %bb10.preheader
-; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v6
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s5
-; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v6
-; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NEXT: v_mov_b32_e32 v7, s3
-; SI-NEXT: v_add_i32_e32 v6, vcc, s2, v6
-; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v4, s1
+; SI-NEXT: v_mov_b32_e32 v6, s5
+; SI-NEXT: v_mov_b32_e32 v8, s3
+; SI-NEXT: s_mov_b64 s[6:7], 0
; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s9, s10
-; SI-NEXT: ; implicit-def: $sgpr4_sgpr5
-; SI-NEXT: s_mov_b64 s[6:7], 0
+; SI-NEXT: ; implicit-def: $sgpr12_sgpr13
+; SI-NEXT: v_add_i32_e32 v3, vcc, s0, v0
+; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; SI-NEXT: v_add_i32_e32 v5, vcc, s4, v0
+; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; SI-NEXT: v_add_i32_e32 v7, vcc, s2, v0
+; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: .LBB5_2: ; %bb10
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, v[6:7], s[8:11], 0 addr64
-; SI-NEXT: buffer_load_dword v9, v[4:5], s[8:11], 0 addr64
+; SI-NEXT: buffer_load_dword v0, v[7:8], s[8:11], 0 addr64
+; SI-NEXT: buffer_load_dword v9, v[5:6], s[8:11], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], -1, v9
-; SI-NEXT: s_and_b64 s[12:13], vcc, s[0:1]
-; SI-NEXT: s_or_b64 s[4:5], s[4:5], exec
-; SI-NEXT: s_and_saveexec_b64 s[0:1], s[12:13]
+; SI-NEXT: s_and_b64 s[4:5], vcc, s[0:1]
+; SI-NEXT: s_or_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_and_saveexec_b64 s[0:1], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB5_4
; SI-NEXT: ; %bb.3: ; %bb20
; SI-NEXT: ; in Loop: Header=BB5_2 Depth=1
-; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; SI-NEXT: s_add_u32 s6, s6, 1
-; SI-NEXT: v_add_i32_e32 v4, vcc, 4, v4
-; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NEXT: v_add_i32_e32 v6, vcc, 4, v6
-; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; SI-NEXT: buffer_store_dword v8, v[2:3], s[8:11], 0 addr64
-; SI-NEXT: s_addc_u32 s7, s7, 0
-; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v2
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
-; SI-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
+; SI-NEXT: v_add_i32_e32 v0, vcc, v9, v0
+; SI-NEXT: s_add_u32 s2, s2, 1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 4, v5
+; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; SI-NEXT: v_add_i32_e32 v7, vcc, 4, v7
+; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; SI-NEXT: buffer_store_dword v0, v[3:4], s[8:11], 0 addr64
+; SI-NEXT: s_addc_u32 s3, s3, 0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 4, v3
+; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[1:2]
+; SI-NEXT: s_andn2_b64 s[4:5], s[12:13], exec
; SI-NEXT: s_and_b64 s[12:13], vcc, exec
-; SI-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
+; SI-NEXT: s_or_b64 s[12:13], s[4:5], s[12:13]
; SI-NEXT: .LBB5_4: ; %Flow
; SI-NEXT: ; in Loop: Header=BB5_2 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[0:1]
-; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
-; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
-; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
+; SI-NEXT: s_and_b64 s[0:1], exec, s[12:13]
+; SI-NEXT: s_or_b64 s[6:7], s[0:1], s[6:7]
+; SI-NEXT: s_andn2_b64 exec, exec, s[6:7]
; SI-NEXT: s_cbranch_execnz .LBB5_2
; SI-NEXT: .LBB5_5: ; %bb26
; SI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
index 20789232b1f25..e6364baaf6dd3 100644
--- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
@@ -10,31 +10,32 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX942-NEXT: v_mov_b32_e32 v2, 8
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dword v3, v1, s[0:1]
+; GFX942-NEXT: global_load_dword v1, v1, s[0:1]
; GFX942-NEXT: s_mov_b32 s4, 0xff0000
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_sdwa v4, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX942-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_or_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX942-NEXT: v_and_or_b32 v3, v3, s4, v4
+; GFX942-NEXT: v_or_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX942-NEXT: v_and_or_b32 v1, v1, s4, v2
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB0_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX942-NEXT: global_load_dword v0, v0, s[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v1, 8
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_sdwa v2, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX942-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX942-NEXT: v_and_or_b32 v3, v0, s4, v2
+; GFX942-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX942-NEXT: v_and_or_b32 v1, v0, s4, v1
; GFX942-NEXT: .LBB0_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX942-NEXT: global_store_byte_d16_hi v1, v3, s[6:7] offset:2
-; GFX942-NEXT: global_store_short v1, v3, s[6:7]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-NEXT: global_store_byte_d16_hi v0, v1, s[6:7] offset:2
+; GFX942-NEXT: global_store_short v0, v1, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -62,17 +63,17 @@ define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dword v2, v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dword v1, v1, s[0:1]
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB1_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX942-NEXT: global_load_dword v2, v0, s[2:3]
+; GFX942-NEXT: global_load_dword v1, v0, s[2:3]
; GFX942-NEXT: .LBB1_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dword v1, v2, s[6:7]
+; GFX942-NEXT: global_store_dword v0, v1, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -98,10 +99,9 @@ define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
@@ -113,8 +113,9 @@ define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT: .LBB2_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX942-NEXT: global_store_byte v3, v1, s[6:7] offset:4
-; GFX942-NEXT: global_store_dword v3, v0, s[6:7]
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: global_store_byte v2, v1, s[6:7] offset:4
+; GFX942-NEXT: global_store_dword v2, v0, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -143,7 +144,6 @@ define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB3_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -151,8 +151,9 @@ define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[2:3]
; GFX942-NEXT: .LBB3_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[6:7]
+; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -181,7 +182,6 @@ define amdgpu_kernel void @v16i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB4_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -189,8 +189,9 @@ define amdgpu_kernel void @v16i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[2:3]
; GFX942-NEXT: .LBB4_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -220,7 +221,6 @@ define amdgpu_kernel void @v32i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx4 v[6:9], v1, s[0:1] offset:16
; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB5_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -229,10 +229,11 @@ define amdgpu_kernel void @v32i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[2:3]
; GFX942-NEXT: .LBB5_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(1)
-; GFX942-NEXT: global_store_dwordx4 v1, v[6:9], s[6:7] offset:16
+; GFX942-NEXT: global_store_dwordx4 v0, v[6:9], s[6:7] offset:16
; GFX942-NEXT: s_waitcnt vmcnt(1)
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -276,7 +277,6 @@ define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: global_load_dwordx4 v[42:45], v1, s[0:1] offset:32
; GFX942-NEXT: global_load_dwordx4 v[38:41], v1, s[0:1] offset:16
; GFX942-NEXT: global_load_dwordx4 v[34:37], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB6_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -299,30 +299,31 @@ define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: global_load_dwordx4 v[34:37], v0, s[2:3]
; GFX942-NEXT: .LBB6_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7] offset:112
+; GFX942-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7] offset:112
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[58:61], s[6:7] offset:96
+; GFX942-NEXT: global_store_dwordx4 v0, v[58:61], s[6:7] offset:96
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[54:57], s[6:7] offset:80
+; GFX942-NEXT: global_store_dwordx4 v0, v[54:57], s[6:7] offset:80
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[50:53], s[6:7] offset:64
+; GFX942-NEXT: global_store_dwordx4 v0, v[50:53], s[6:7] offset:64
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[46:49], s[6:7] offset:48
+; GFX942-NEXT: global_store_dwordx4 v0, v[46:49], s[6:7] offset:48
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[42:45], s[6:7] offset:32
+; GFX942-NEXT: global_store_dwordx4 v0, v[42:45], s[6:7] offset:32
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[38:41], s[6:7] offset:16
+; GFX942-NEXT: global_store_dwordx4 v0, v[38:41], s[6:7] offset:16
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[34:37], s[6:7]
-; GFX942-NEXT: global_store_dwordx4 v1, v[30:33], s[6:7] offset:240
-; GFX942-NEXT: global_store_dwordx4 v1, v[26:29], s[6:7] offset:224
-; GFX942-NEXT: global_store_dwordx4 v1, v[22:25], s[6:7] offset:208
-; GFX942-NEXT: global_store_dwordx4 v1, v[18:21], s[6:7] offset:192
-; GFX942-NEXT: global_store_dwordx4 v1, v[14:17], s[6:7] offset:176
-; GFX942-NEXT: global_store_dwordx4 v1, v[10:13], s[6:7] offset:160
-; GFX942-NEXT: global_store_dwordx4 v1, v[6:9], s[6:7] offset:144
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7] offset:128
+; GFX942-NEXT: global_store_dwordx4 v0, v[34:37], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[30:33], s[6:7] offset:240
+; GFX942-NEXT: global_store_dwordx4 v0, v[26:29], s[6:7] offset:224
+; GFX942-NEXT: global_store_dwordx4 v0, v[22:25], s[6:7] offset:208
+; GFX942-NEXT: global_store_dwordx4 v0, v[18:21], s[6:7] offset:192
+; GFX942-NEXT: global_store_dwordx4 v0, v[14:17], s[6:7] offset:176
+; GFX942-NEXT: global_store_dwordx4 v0, v[10:13], s[6:7] offset:160
+; GFX942-NEXT: global_store_dwordx4 v0, v[6:9], s[6:7] offset:144
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7] offset:128
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -626,14 +627,13 @@ define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspac
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[4:5], v1, s[8:9]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[4:5]
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB11_4
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX942-NEXT: global_load_dwordx2 v[2:3], v2, s[10:11]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[10:11]
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB11_3
@@ -644,8 +644,9 @@ define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspac
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: .LBB11_4: ; %bb.3
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[14:15]
+; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[14:15]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -727,62 +728,64 @@ define amdgpu_kernel void @v8i8_multiuse_multiblock(ptr addrspace(1) %src1, ptr
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[8:9]
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
-; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX942-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX942-NEXT: s_cbranch_execz .LBB13_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: s_movk_i32 s6, 0xff00
-; GFX942-NEXT: v_mov_b32_e32 v5, 8
-; GFX942-NEXT: v_and_b32_sdwa v6, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX942-NEXT: v_mov_b32_e32 v4, 8
+; GFX942-NEXT: s_waitcnt vmcnt(0)
+; GFX942-NEXT: v_and_b32_sdwa v5, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX942-NEXT: s_mov_b32 s6, 0x6070504
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v2
-; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v0
-; GFX942-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX942-NEXT: v_perm_b32 v7, v0, v0, s6
+; GFX942-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
+; GFX942-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX942-NEXT: v_perm_b32 v6, v0, v0, s6
; GFX942-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX942-NEXT: s_and_b64 s[6:7], vcc, exec
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX942-NEXT: v_or_b32_sdwa v6, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: global_store_dword v3, v0, s[12:13]
-; GFX942-NEXT: global_store_dword v3, v7, s[12:13] offset:8
-; GFX942-NEXT: global_store_dword v3, v6, s[12:13] offset:16
-; GFX942-NEXT: global_store_dword v3, v4, s[12:13] offset:24
+; GFX942-NEXT: v_or_b32_sdwa v5, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: global_store_dword v1, v0, s[12:13]
+; GFX942-NEXT: global_store_dword v1, v6, s[12:13] offset:8
+; GFX942-NEXT: global_store_dword v1, v5, s[12:13] offset:16
+; GFX942-NEXT: global_store_dword v1, v3, s[12:13] offset:24
; GFX942-NEXT: .LBB13_2: ; %Flow
; GFX942-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX942-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX942-NEXT: s_cbranch_execz .LBB13_4
; GFX942-NEXT: ; %bb.3: ; %bb.2
-; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v1
-; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
+; GFX942-NEXT: s_waitcnt vmcnt(0)
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v2
+; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v2
; GFX942-NEXT: v_and_b32_e32 v5, 0xffffff00, v0
; GFX942-NEXT: s_mov_b32 s2, 0xc0c0001
; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_or_b32_sdwa v5, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_perm_b32 v2, 0, v2, s2
+; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT: v_perm_b32 v6, 0, v0, s2
; GFX942-NEXT: s_mov_b32 s3, 0xffff0000
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX942-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX942-NEXT: v_and_or_b32 v7, v0, s3, v6
; GFX942-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX942-NEXT: global_store_dword v2, v3, s[14:15]
-; GFX942-NEXT: global_store_dword v2, v4, s[14:15] offset:8
-; GFX942-NEXT: global_store_dword v2, v7, s[14:15] offset:16
-; GFX942-NEXT: global_store_dword v2, v1, s[14:15] offset:24
+; GFX942-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX942-NEXT: global_store_dword v1, v3, s[14:15]
+; GFX942-NEXT: global_store_dword v1, v4, s[14:15] offset:8
+; GFX942-NEXT: global_store_dword v1, v7, s[14:15] offset:16
+; GFX942-NEXT: global_store_dword v1, v2, s[14:15] offset:24
; GFX942-NEXT: .LBB13_4: ; %bb.3
; GFX942-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX942-NEXT: s_movk_i32 s3, 0xff00
; GFX942-NEXT: v_mov_b32_e32 v4, 8
; GFX942-NEXT: s_movk_i32 s2, 0xff
+; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_and_b32_sdwa v2, v0, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX942-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX942-NEXT: v_or_b32_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -868,7 +871,6 @@ define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[8:9]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB14_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -877,14 +879,15 @@ define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: .LBB14_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[14:15], 0x0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_mfma_i32_16x16x32_i8 v[2:5], v[2:3], v[2:3], v[4:7] cbsz:1 abid:2 blgp:3
+; GFX942-NEXT: v_mfma_i32_16x16x32_i8 v[0:3], v[2:3], v[2:3], v[4:7] cbsz:1 abid:2 blgp:3
; GFX942-NEXT: s_nop 6
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[12:13]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[12:13]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -914,19 +917,19 @@ define amdgpu_kernel void @v8i8_mfma_half(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: s_load_dwordx8 s[36:43], s[4:5], 0x24
; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX942-NEXT: v_mov_b32_e32 v32, 0
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx2 v[34:35], v1, s[36:37]
+; GFX942-NEXT: global_load_dwordx2 v[32:33], v1, s[36:37]
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB15_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX942-NEXT: global_load_dwordx2 v[34:35], v0, s[38:39]
+; GFX942-NEXT: global_load_dwordx2 v[32:33], v0, s[38:39]
; GFX942-NEXT: .LBB15_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_load_dwordx16 s[16:31], s[42:43], 0x0
; GFX942-NEXT: s_load_dwordx16 s[0:15], s[42:43], 0x40
+; GFX942-NEXT: v_mov_b32_e32 v34, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v0, s16
; GFX942-NEXT: v_mov_b32_e32 v1, s17
@@ -962,17 +965,17 @@ define amdgpu_kernel void @v8i8_mfma_half(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: v_mov_b32_e32 v31, s15
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_mfma_f32_32x32x4_2b_f16 v[0:31], v[34:35], v[34:35], v[0:31] cbsz:1 abid:2 blgp:3
+; GFX942-NEXT: v_mfma_f32_32x32x4_2b_f16 v[0:31], v[32:33], v[32:33], v[0:31] cbsz:1 abid:2 blgp:3
; GFX942-NEXT: s_nop 15
; GFX942-NEXT: s_nop 2
-; GFX942-NEXT: global_store_dwordx4 v32, v[28:31], s[40:41] offset:112
-; GFX942-NEXT: global_store_dwordx4 v32, v[24:27], s[40:41] offset:96
-; GFX942-NEXT: global_store_dwordx4 v32, v[20:23], s[40:41] offset:80
-; GFX942-NEXT: global_store_dwordx4 v32, v[16:19], s[40:41] offset:64
-; GFX942-NEXT: global_store_dwordx4 v32, v[12:15], s[40:41] offset:48
-; GFX942-NEXT: global_store_dwordx4 v32, v[8:11], s[40:41] offset:32
-; GFX942-NEXT: global_store_dwordx4 v32, v[4:7], s[40:41] offset:16
-; GFX942-NEXT: global_store_dwordx4 v32, v[0:3], s[40:41]
+; GFX942-NEXT: global_store_dwordx4 v34, v[28:31], s[40:41] offset:112
+; GFX942-NEXT: global_store_dwordx4 v34, v[24:27], s[40:41] offset:96
+; GFX942-NEXT: global_store_dwordx4 v34, v[20:23], s[40:41] offset:80
+; GFX942-NEXT: global_store_dwordx4 v34, v[16:19], s[40:41] offset:64
+; GFX942-NEXT: global_store_dwordx4 v34, v[12:15], s[40:41] offset:48
+; GFX942-NEXT: global_store_dwordx4 v34, v[8:11], s[40:41] offset:32
+; GFX942-NEXT: global_store_dwordx4 v34, v[4:7], s[40:41] offset:16
+; GFX942-NEXT: global_store_dwordx4 v34, v[0:3], s[40:41]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1002,10 +1005,9 @@ define amdgpu_kernel void @v8i8_intrinsic(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB16_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
@@ -1014,9 +1016,10 @@ define amdgpu_kernel void @v8i8_intrinsic(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX942-NEXT: .LBB16_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[0:1], v[0:1]
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[6:7]
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
index a8c2531117f42..ae0949e94bef2 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
@@ -73,21 +73,25 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: s_mov_b32 s8, s33
; CHECK-NEXT: s_mov_b32 s33, s32
; CHECK-NEXT: s_addk_i32 s32, 0x600
-; CHECK-NEXT: v_mov_b32_e32 v4, 0
-; CHECK-NEXT: v_mov_b32_e32 v0, 1
-; CHECK-NEXT: v_mov_b32_e32 v1, 2
-; CHECK-NEXT: v_mov_b32_e32 v2, 3
-; CHECK-NEXT: v_mov_b32_e32 v3, 4
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33
-; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:12
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:16
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 1
+; CHECK-NEXT: v_mov_b32_e32 v2, 2
+; CHECK-NEXT: v_mov_b32_e32 v3, 3
+; CHECK-NEXT: v_mov_b32_e32 v4, 4
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:16
; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1:
+; CHECK-NEXT: v_mov_b32_e32 v0, 1
+; CHECK-NEXT: v_mov_b32_e32 v1, 2
+; CHECK-NEXT: v_mov_b32_e32 v2, 3
+; CHECK-NEXT: v_mov_b32_e32 v3, 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:12
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
index 34530f2f632e2..09c1e1b12d416 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
@@ -14,21 +14,25 @@ define dso_local i32 @check_boundaries() #0 {
; CHECK-NEXT: s_mov_b32 s8, s33
; CHECK-NEXT: s_mov_b32 s33, s32
; CHECK-NEXT: s_addk_i32 s32, 0x600
-; CHECK-NEXT: v_mov_b32_e32 v4, 0
-; CHECK-NEXT: v_mov_b32_e32 v0, 1
-; CHECK-NEXT: v_mov_b32_e32 v1, 2
-; CHECK-NEXT: v_mov_b32_e32 v2, 3
-; CHECK-NEXT: v_mov_b32_e32 v3, 4
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33
-; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
-; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:12
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:16
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 1
+; CHECK-NEXT: v_mov_b32_e32 v2, 2
+; CHECK-NEXT: v_mov_b32_e32 v3, 3
+; CHECK-NEXT: v_mov_b32_e32 v4, 4
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:8
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:12
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:16
; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1:
+; CHECK-NEXT: v_mov_b32_e32 v0, 1
+; CHECK-NEXT: v_mov_b32_e32 v1, 2
+; CHECK-NEXT: v_mov_b32_e32 v2, 3
+; CHECK-NEXT: v_mov_b32_e32 v3, 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:12
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