[llvm] [DAGCombiner] Teach `reduceLoadWidth` to look past `ISD:FREEZE` (PR #189317)

[Henry Jiang via llvm-commits]

mustartt wrote:

> > If its identical to the IR freeze, then `zext(freeze(load)) -> freeze(zextload)` in #175022 also invalid per the semantics of freeze. But since we are in the machine land, this is accepted? That's what I'm trying to answer.
> 
> I don't think your failing alive2 link is representative of what a zextload entails. The alive link uses an i32 as the source value, but the zextload only needs to freeze the low byte; the low i8 is the only maybe-undef component that needs freezing

Thanks, I see now that something like this verifies. This answers my question.
```
----------------------------------------
define i32 @src(ptr %p) {
#0:
  %byte = load i8, ptr %p, align 1
  %ext = zext i8 %byte to i32
  %fr = freeze i32 %ext
  %r = and i32 %fr, 255
  ret i32 %r
}
=>
define i32 @tgt(ptr %p) {
#0:
  %byte = load i8, ptr %p, align 1
  %fr = freeze i8 %byte
  %r = zext i8 %fr to i32
  ret i32 %r
}
Transformation seems to be correct!
```

https://github.com/llvm/llvm-project/pull/189317