[llvm] AMDGPU/GlobalISel: Add SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (PR #187679)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 07:48:39 PDT 2026
================
@@ -1437,16 +1437,23 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS1, _, S64}, {{UniInVcc}, {None, Vgpr64, Vgpr64}}})
.Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}});
- addRulesForGOpcs({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN, G_FFLOOR, G_FCEIL,
- G_FEXP2, G_FLOG2},
- Standard)
+ addRulesForGOpcs({G_INTRINSIC_ROUNDEVEN, G_FEXP2, G_FLOG2}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
+ addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16}})
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anjenner wrote:
They are listed on https://docs.amd.com/v/u/en-US/rdna35_instruction_set_architecture too. I've added them to the rule and added tests too.
https://github.com/llvm/llvm-project/pull/187679
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