[llvm] AMDGPU/GlobalISel: Add SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (PR #187679)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 06:08:18 PDT 2026
https://github.com/anjenner updated https://github.com/llvm/llvm-project/pull/187679
>From 18f198bf5b219a0eafe8855672c2420789f23710 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Fri, 20 Mar 2026 07:33:35 -0400
Subject: [PATCH 1/3] AMDGPU/GlobalISel: Add SALUFloat variants of
G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL.
---
.../Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 77802f5f4349a..a0e387b23dd24 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1520,9 +1520,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS1, _, S64}, {{UniInVcc}, {None, Vgpr64, Vgpr64}}})
.Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}});
- addRulesForGOpcs({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN, G_FFLOOR, G_FCEIL,
- G_FEXP2, G_FLOG2},
- Standard)
+ addRulesForGOpcs({G_INTRINSIC_ROUNDEVEN, G_FEXP2, G_FLOG2}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
@@ -1530,6 +1528,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S64, {{UniInVgprS64}, {Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
+ addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Div(S16, {{Vgpr16}, {Vgpr16}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32}})
+ .Uni(S32, {{Sgpr32}, {Sgpr32}}, hasSALUFloat)
+ .Div(S32, {{Vgpr32}, {Vgpr32}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64}})
+ .Div(S64, {{Vgpr64}, {Vgpr64}});
+
using namespace Intrinsic;
addRulesForIOpcs({returnaddress}).Any({{UniP0}, {{SgprP0}, {}}});
>From 57c50e851485639cf418da83e52c1f1af753801e Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 28 Apr 2026 12:52:07 -0400
Subject: [PATCH 2/3] Add testcases.
---
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 35 ++++++++++++-------
.../GlobalISel/regbankselect-ffloor.mir | 35 ++++++++++++-------
.../regbankselect-intrinsic-trunc.mir | 35 ++++++++++++-------
3 files changed, 69 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 920eb0f9d5df3..26d97a5ad8bb3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: fceil_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: fceil_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
+ ; FIJI-LABEL: name: fceil_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s32) = G_FCEIL [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FCEIL %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: fceil_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ ; FIJI-LABEL: name: fceil_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ ; GFX12-LABEL: name: fceil_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index bff455e7b2a85..da2ec94089a30 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: ffloor_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: ffloor_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
+ ; FIJI-LABEL: name: ffloor_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s32) = G_FFLOOR [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FFLOOR %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ffloor_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
+ ; FIJI-LABEL: name: ffloor_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
+ ; GFX12-LABEL: name: ffloor_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FFLOOR %0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 6318297cc1133..4923665919340 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: intrinsic_trunc_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: intrinsic_trunc_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; FIJI-LABEL: name: intrinsic_trunc_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: intrinsic_trunc_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; FIJI-LABEL: name: intrinsic_trunc_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX12-LABEL: name: intrinsic_trunc_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
>From c96e94ac7636972cfe204590cfc14d91e2060f82 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Wed, 29 Apr 2026 09:15:17 -0400
Subject: [PATCH 3/3] Handle s16 SALUFloat variants. Add tests for s16 and s64,
uniform and divergent.
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 1 +
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 93 +++++++++++++++++++
.../GlobalISel/regbankselect-ffloor.mir | 93 +++++++++++++++++++
.../regbankselect-intrinsic-trunc.mir | 93 +++++++++++++++++++
4 files changed, 280 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index a0e387b23dd24..704d4ca2b5adb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1530,6 +1530,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Uni(S16, {{Sgpr16}, {Sgpr16}}, hasSALUFloat)
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
.Uni(S32, {{Sgpr32}, {Sgpr32}}, hasSALUFloat)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 26d97a5ad8bb3..12617e6873b98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
...
+
+---
+name: fceil_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: fceil_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s16) = G_FCEIL [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FCEIL %1
+...
+
+---
+name: fceil_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: fceil_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
+ ; GFX12-LABEL: name: fceil_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FCEIL %1
+...
+
+---
+name: fceil_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: fceil_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_FCEIL %0
+...
+
+---
+name: fceil_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: fceil_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
+ ; GFX12-LABEL: name: fceil_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_FCEIL %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index da2ec94089a30..f89727648aafc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FFLOOR %0
...
+
+---
+name: ffloor_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: ffloor_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s16) = G_FFLOOR [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FFLOOR %1
+...
+
+---
+name: ffloor_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: ffloor_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
+ ; GFX12-LABEL: name: ffloor_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FFLOOR %1
+...
+
+---
+name: ffloor_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: ffloor_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_FFLOOR %0
+...
+
+---
+name: ffloor_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: ffloor_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
+ ; GFX12-LABEL: name: ffloor_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_FFLOOR %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 4923665919340..1f878bd44f6ad 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
+
+---
+name: intrinsic_trunc_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: intrinsic_trunc_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC_TRUNC %1
+...
+
+---
+name: intrinsic_trunc_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: intrinsic_trunc_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC_TRUNC %1
+...
+
+---
+name: intrinsic_trunc_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: intrinsic_trunc_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_INTRINSIC_TRUNC %0
+...
+
+---
+name: intrinsic_trunc_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: intrinsic_trunc_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_INTRINSIC_TRUNC %0
+...
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