[llvm] [AArch64] Simplify codegen for LRINT. (PR #194342)

[Paul Walker via llvm-commits]

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@@ -5181,12 +5184,9 @@ SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
       *DAG.getContext(), Src.getValueType().getVectorElementType());
 
   // Round the floating-point value into a floating-point register with the
-  // current rounding mode.
+  // current rounding mode and convert to an integer.
   SDValue FOp = DAG.getNode(ISD::FRINT, DL, CastVT, Src);
-
-  // Truncate the rounded floating point to an integer.
-  return DAG.getNode(ISD::FP_TO_SINT_SAT, DL, VT, FOp,
-                     DAG.getValueType(VT.getVectorElementType()));
+  return DAG.getFreeze(DAG.getNode(ISD::FP_TO_SINT, DL, VT, FOp));
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paulwalker-arm wrote:

The LangReg  says:

```If the rounded value is too large to be stored in the result type, the return value is a non-deterministic value (equivalent to freeze poison)```

Perhaps the use of "equivalent to freeze..." changes things here? but I don't know if that's actually how the intrinsic is implemented.  I did not spot any explicit freezing for existing ISD::LRINT lowering paths (common or target specific). If there's a nuance here then  presumably that means at least `SelectionDAGLegalize::ExpandNode` is broken?



https://github.com/llvm/llvm-project/pull/194342