[llvm] [AArch64] Simplify codegen for LRINT. (PR #194342)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 03:58:43 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Sander de Smalen (sdesmalen-arm)
<details>
<summary>Changes</summary>
We don't need to use FP_TO_SINT_SAT, because according to the LangRef floating point values that don't fit the integer domain return a non-deterministic (freeze(poison)) value. The saturation code is quite verbose, so freezing the result seems like a better approach.
This was also discussed here:
https://github.com/llvm/llvm-project/pull/89035#discussion_r1595859634
We could even optimise away the freeze when we know that the operands to AArch64ISD::FCVTZS_MERGE_PASSTHRU are not poison.
---
Patch is 295.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194342.diff
6 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+2-5)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll (+262-578)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll (+445-1130)
- (modified) llvm/test/CodeGen/AArch64/sve-llrint.ll (+318-1279)
- (modified) llvm/test/CodeGen/AArch64/sve-lrint.ll (+318-1279)
- (modified) llvm/test/CodeGen/AArch64/vector-lrint.ll (+76-192)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2b08a89566de9..9571889b07836 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5184,12 +5184,9 @@ SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
*DAG.getContext(), Src.getValueType().getVectorElementType());
// Round the floating-point value into a floating-point register with the
- // current rounding mode.
+ // current rounding mode and convert to an integer.
SDValue FOp = DAG.getNode(ISD::FRINT, DL, CastVT, Src);
-
- // Truncate the rounded floating point to an integer.
- return DAG.getNode(ISD::FP_TO_SINT_SAT, DL, VT, FOp,
- DAG.getValueType(VT.getVectorElementType()));
+ return DAG.getFreeze(DAG.getNode(ISD::FP_TO_SINT, DL, VT, FOp));
}
SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
index 9372f2a82a795..26171a91939c3 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
@@ -34,17 +34,14 @@ define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: mov h2, v0.h[3]
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: fcvtzs x8, h1
-; CHECK-NEXT: fcvtzs x10, h2
-; CHECK-NEXT: fcvtzs x11, h3
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], x11
-; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
ret <4 x i64> %a
@@ -56,29 +53,23 @@ define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: frintx v0.4h, v0.4h
+; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: mov h3, v0.h[2]
-; CHECK-NEXT: mov h4, v0.h[1]
-; CHECK-NEXT: mov h5, v0.h[3]
-; CHECK-NEXT: fcvtzs x8, h0
-; CHECK-NEXT: mov h2, v1.h[2]
-; CHECK-NEXT: mov h6, v1.h[3]
-; CHECK-NEXT: mov h7, v1.h[1]
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: fcvtzs x11, h3
-; CHECK-NEXT: fcvtzs x12, h4
-; CHECK-NEXT: fcvtzs x13, h5
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fcvtzs x9, h2
-; CHECK-NEXT: fcvtzs x14, h6
-; CHECK-NEXT: fcvtzs x15, h7
-; CHECK-NEXT: fmov d2, x10
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: mov v0.d[1], x12
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: mov v1.d[1], x13
-; CHECK-NEXT: mov v2.d[1], x15
-; CHECK-NEXT: mov v3.d[1], x14
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
ret <8 x i64> %a
@@ -88,56 +79,43 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: frintx v1.4h, v1.4h
+; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx v2.4h, v2.4h
; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h4, v1.h[2]
-; CHECK-NEXT: mov h6, v0.h[1]
-; CHECK-NEXT: fcvtzs x8, h1
-; CHECK-NEXT: mov h16, v0.h[3]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: mov h7, v1.h[1]
-; CHECK-NEXT: mov h1, v1.h[3]
-; CHECK-NEXT: mov h0, v2.h[3]
-; CHECK-NEXT: mov h17, v2.h[2]
-; CHECK-NEXT: fcvtzs x12, h5
-; CHECK-NEXT: mov h5, v3.h[2]
-; CHECK-NEXT: fcvtzs x11, h2
-; CHECK-NEXT: mov h18, v3.h[3]
-; CHECK-NEXT: fcvtzs x14, h3
-; CHECK-NEXT: mov h3, v3.h[1]
-; CHECK-NEXT: mov h19, v2.h[1]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: fcvtzs x15, h0
-; CHECK-NEXT: fcvtzs x8, h17
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtzs x9, h5
-; CHECK-NEXT: fcvtzs x16, h7
-; CHECK-NEXT: fcvtzs x17, h16
-; CHECK-NEXT: fmov d6, x11
-; CHECK-NEXT: fcvtzs x11, h18
-; CHECK-NEXT: fcvtzs x18, h3
-; CHECK-NEXT: fmov d2, x14
-; CHECK-NEXT: fcvtzs x14, h19
-; CHECK-NEXT: fcvtzs x0, h1
-; CHECK-NEXT: fmov d5, x10
-; CHECK-NEXT: fmov d1, x12
-; CHECK-NEXT: fmov d7, x8
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: mov v0.d[1], x13
-; CHECK-NEXT: mov v4.d[1], x16
-; CHECK-NEXT: mov v2.d[1], x18
-; CHECK-NEXT: mov v1.d[1], x17
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: mov v6.d[1], x14
-; CHECK-NEXT: mov v3.d[1], x11
-; CHECK-NEXT: mov v7.d[1], x15
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z4, z1
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z1.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z6, z3
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z5, z4
+; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: movprfx z7, z6
+; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
ret <16 x i64> %a
@@ -147,128 +125,58 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #272
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: frintx v5.4h, v0.4h
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v17.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: frintx v1.4h, v1.4h
+; CHECK-NEXT: ext v4.16b, v3.16b, v3.16b, #8
+; CHECK-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov x9, #24 // =0x18
+; CHECK-NEXT: frintx v3.4h, v3.4h
+; CHECK-NEXT: ext v6.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: frintx v2.4h, v2.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: mov h6, v5.h[3]
+; CHECK-NEXT: ext v7.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: mov h7, v5.h[2]
-; CHECK-NEXT: mov h16, v5.h[1]
+; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx v4.4h, v4.4h
-; CHECK-NEXT: fcvtzs x12, h5
-; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: frintx v17.4h, v17.4h
-; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: fcvtzs x9, h6
-; CHECK-NEXT: mov h6, v0.h[3]
-; CHECK-NEXT: fcvtzs x10, h7
-; CHECK-NEXT: mov h7, v0.h[2]
-; CHECK-NEXT: fcvtzs x11, h16
-; CHECK-NEXT: mov h16, v0.h[1]
-; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: mov h6, v4.h[3]
-; CHECK-NEXT: stp x10, x9, [sp, #48]
-; CHECK-NEXT: fcvtzs x9, h7
-; CHECK-NEXT: mov h7, v4.h[2]
-; CHECK-NEXT: fcvtzs x10, h16
-; CHECK-NEXT: mov h16, v4.h[1]
-; CHECK-NEXT: stp x12, x11, [sp, #32]
-; CHECK-NEXT: fcvtzs x11, h0
-; CHECK-NEXT: frintx v0.4h, v5.4h
-; CHECK-NEXT: mov h5, v17.h[3]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: mov h6, v17.h[2]
-; CHECK-NEXT: stp x9, x13, [sp, #16]
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h7, v17.h[1]
-; CHECK-NEXT: fcvtzs x9, h16
-; CHECK-NEXT: stp x11, x10, [sp]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h4, v0.h[3]
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: stp x13, x12, [sp, #80]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h6, v0.h[1]
-; CHECK-NEXT: stp x10, x9, [sp, #64]
-; CHECK-NEXT: fcvtzs x9, h17
-; CHECK-NEXT: mov h7, v1.h[3]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v1.h[2]
-; CHECK-NEXT: stp x12, x11, [sp, #144]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v1.h[1]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: stp x9, x13, [sp, #128]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h0, v2.h[3]
-; CHECK-NEXT: stp x11, x10, [sp, #208]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v2.h[2]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v2.h[1]
-; CHECK-NEXT: stp x9, x12, [sp, #192]
-; CHECK-NEXT: fcvtzs x9, h1
-; CHECK-NEXT: fcvtzs x12, h0
-; CHECK-NEXT: mov h0, v3.h[3]
-; CHECK-NEXT: mov h1, v3.h[2]
-; CHECK-NEXT: stp x10, x13, [sp, #112]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v3.h[1]
-; CHECK-NEXT: fcvtzs x13, h5
-; CHECK-NEXT: stp x9, x11, [sp, #96]
-; CHECK-NEXT: fcvtzs x9, h2
-; CHECK-NEXT: fcvtzs x11, h0
-; CHECK-NEXT: stp x10, x12, [sp, #176]
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: fcvtzs x12, h4
-; CHECK-NEXT: stp x9, x13, [sp, #160]
-; CHECK-NEXT: fcvtzs x9, h3
-; CHECK-NEXT: stp x10, x11, [sp, #240]
-; CHECK-NEXT: add x10, sp, #64
-; CHECK-NEXT: stp x9, x12, [sp, #224]
-; CHECK-NEXT: add x9, sp, #32
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #224
-; CHECK-NEXT: add x10, sp, #128
-; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #160
-; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-NEXT: add x10, sp, #96
-; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #192
-; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-NEXT: mov x10, #24 // =0x18
-; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-NEXT: frintx v5.4h, v5.4h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: frintx v6.4h, v6.4h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: frintx v7.4h, v7.4h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: uunpklo z5.s, z5.h
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpklo z6.s, z6.h
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpklo z7.s, z7.h
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: uunpklo z6.d, z6.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
-; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
-; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #28 // =0x1c
-; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: mov x9, #20 // =0x14
+; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
-; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
-; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
ret <32 x i64> %a
@@ -304,17 +212,13 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s1, v0.s[2]
-; CHECK-NEXT: mov s2, v0.s[3]
-; CHECK-NEXT: mov s3, v0.s[1]
-; CHECK-NEXT: fcvtzs x9, s0
-; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], x11
-; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
ret <4 x i64> %a
@@ -326,28 +230,20 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s2, v1.s[2]
-; CHECK-NEXT: mov s3, v0.s[2]
-; CHECK-NEXT: mov s4, v0.s[1]
-; CHECK-NEXT: mov s5, v1.s[3]
-; CHECK-NEXT: mov s6, v1.s[1]
-; CHECK-NEXT: mov s7, v0.s[3]
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fcvtzs x12, s4
-; CHECK-NEXT: fcvtzs x13, s5
-; CHECK-NEXT: fcvtzs x14, s6
-; CHECK-NEXT: fcvtzs x15, s7
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d2, x10
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: mov v0.d[1], x12
-; CHECK-NEXT: mov v2.d[1], x14
-; CHECK-NEXT: mov v1.d[1], x15
-; CHECK-NEXT: mov v3.d[1], x13
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
ret <8 x i64> %a
@@ -357,54 +253,37 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: frintx v3.4s, v3.4s
-; CHECK-NEXT: frintx v2.4s, v2.4s
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s4, v3.s[2]
-; CHECK-NEXT: mov s5, v2.s[2]
-; CHECK-NEXT: mov s6, v2.s[1]
-; CHECK-NEXT: mov s7, v1.s[2]
-; CHECK-NEXT: fcvtzs x8, s3
-; CHECK-NEXT: mov s16, v0.s[2]
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: mov s17, v1.s[3]
-; CHECK-NEXT: mov s18, v0.s[1]
-; CHECK-NEXT: mov s19, v3.s[3]
-; CHECK-NEXT: fcvtzs x14, s1
-; CHECK-NEXT: mov s1, v1.s[1]
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: fcvtzs x11, s5
-; CHECK-NEXT: mov s5, v0.s[3]
-; CHECK-NEXT: mov s3, v3.s[1]
-; CHECK-NEXT: mov s2, v2.s[3]
-; CHECK-NEXT: fcvtzs x12, s6
-; CHECK-NEXT: fcvtzs x13, s7
-; CHECK-NEXT: fcvtzs x15, s16
-; CHECK-NEXT: fmov d6, x8
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcvtzs x9, s17
-; CHECK-NEXT: fcvtzs x16, s5
-; CHECK-NEXT: fcvtzs x17, s18
-; CHECK-NEXT: fmov d7, x10
-; CHECK-NEXT: fmov d5, x11
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcvtzs x11, s19
-; CHECK-NEXT: fcvtzs x18, s3
-; CHECK-NEXT: fcvtzs x0, s2
-; CHECK-NEXT: fmov d3, x13
-; CHECK-NEXT: fmov d1, x15
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d2, x14
-; CHECK-NEXT: mov v4.d[1], x12
-; CHECK-NEXT: mov v3.d[1], x9
-; CHECK-NEXT: mov v7.d[1], x11
-; CHECK-NEXT: mov v0.d[1], x17
-; CHECK-NEXT: mov v1.d[1], x16
-; CHECK-NEXT: mov v2.d[1], x10
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: mov v6.d[1], x18
+; CHECK-NEXT: frintx v3.4s, v3.4s
+; CHECK-NEXT: frintx v2.4s, v2.4s
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpklo z4.d, z2.s
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z6, z3
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: movprfx z7, z6
+; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-NEXT: movprfx z5, z4
+; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
+; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
ret <16 x i64> %a
@@ -414,124 +293,46 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #272
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: frintx v1.4s, v1.4s
+; CHECK-NEXT: frintx v7.4s, v7.4s
+; C...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194342
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