[llvm] [RISCV] Improve getInterleavedMemoryOpCost for interleave groups with tail gaps. (PR #192074)
Mel Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 03:37:11 PDT 2026
https://github.com/Mel-Chen updated https://github.com/llvm/llvm-project/pull/192074
>From a82aded90e98668b519eb7d8ed46e6f2c2c9f917 Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen at sifive.com>
Date: Tue, 14 Apr 2026 07:33:17 -0700
Subject: [PATCH 1/3] strided seg store
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 28 ++++++++++++++++++
.../RISCV/tail-folding-interleave.ll | 29 +++++++------------
2 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index d465b4d4caebd..cb3dbcbce60fc 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1143,6 +1143,34 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
return InstructionCost::getInvalid();
auto *FVTy = cast<FixedVectorType>(VecTy);
+ // When gaps are only at the tail, for interleaved load, we can emit a wide
+ // masked load and shufflevectors. For interleaved store, we can emit
+ // shufflevectors and a wide masked store. The interleaved memory access pass
+ // will lower them into vlsseg/vssseg intrinsics.
+ if (UseMaskForGaps) {
+ unsigned NumOfFields = Indices.size();
+ bool IsTailGapOnly = NumOfFields > 1 && (NumOfFields == Indices.back() + 1);
+ if (IsTailGapOnly &&
+ NumOfFields <= TLI->getMaxSupportedInterleaveFactor()) {
+ std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(FVTy);
+ if (LT.second.isVector() &&
+ FVTy->getElementCount().isKnownMultipleOf(Factor)) {
+ auto *SubVecTy = VectorType::get(
+ FVTy->getElementType(),
+ FVTy->getElementCount().divideCoefficientBy(Factor));
+ if (TLI->isLegalInterleavedAccessType(SubVecTy, NumOfFields, Alignment,
+ AddressSpace, DL)) {
+ // The cost is proportional to the total number of element accesses.
+ InstructionCost MemOpCost =
+ getMemoryOpCost(Opcode, FVTy->getElementType(), Alignment, 0,
+ CostKind, {TTI::OK_AnyValue, TTI::OP_None});
+ unsigned NumAccesses = getEstimatedVLFor(FVTy);
+ return NumAccesses * MemOpCost;
+ }
+ }
+ }
+ }
+
InstructionCost MemCost =
getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace, CostKind);
unsigned VF = FVTy->getNumElements() / Factor;
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
index 28e4941bbfa45..2091cddc10bde 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
@@ -493,30 +493,23 @@ define void @store_factor_4_with_tail_gap(i32 %n, ptr noalias %a) {
;
; NO-VP-LABEL: @store_factor_4_with_tail_gap(
; NO-VP-NEXT: entry:
-; NO-VP-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
-; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i32 [[TMP0]], 2
-; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N:%.*]], [[TMP1]]
+; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N:%.*]], 8
; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; NO-VP: vector.ph:
-; NO-VP-NEXT: [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
-; NO-VP-NEXT: [[TMP9:%.*]] = shl nuw i32 [[TMP2]], 2
-; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], [[TMP9]]
+; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 8
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
-; NO-VP-NEXT: [[TMP7:%.*]] = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()
-; NO-VP-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP9]], i64 0
-; NO-VP-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT2]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]
; NO-VP: vector.body:
; NO-VP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[VEC_IND4:%.*]] = phi <vscale x 4 x i32> [ [[TMP7]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT5:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i32], ptr [[A:%.*]], <vscale x 4 x i32> [[VEC_IND4]], i32 0
-; NO-VP-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[VEC_IND4]], <vscale x 4 x ptr> align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true))
-; NO-VP-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], <vscale x 4 x i32> [[VEC_IND4]], i32 1
-; NO-VP-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[VEC_IND4]], <vscale x 4 x ptr> align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true))
-; NO-VP-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], <vscale x 4 x i32> [[VEC_IND4]], i32 2
-; NO-VP-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[VEC_IND4]], <vscale x 4 x ptr> align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true))
-; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP9]]
-; NO-VP-NEXT: [[VEC_IND_NEXT5]] = add nuw nsw <vscale x 4 x i32> [[VEC_IND4]], [[BROADCAST_SPLAT3]]
+; NO-VP-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; NO-VP-NEXT: [[TMP0:%.*]] = getelementptr inbounds [4 x i32], ptr [[A:%.*]], i32 [[INDEX]], i32 0
+; NO-VP-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC_IND]], <8 x i32> [[VEC_IND]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; NO-VP-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC_IND]], <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; NO-VP-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> [[TMP2]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; NO-VP-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <32 x i32> [[TMP3]], <32 x i32> poison, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
+; NO-VP-NEXT: call void @llvm.masked.store.v32i32.p0(<32 x i32> [[INTERLEAVED_VEC]], ptr align 4 [[TMP0]], <32 x i1> <i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>)
+; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; NO-VP-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <8 x i32> [[VEC_IND]], splat (i32 8)
; NO-VP-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; NO-VP: middle.block:
>From 709c77d89eeb102f69a927d293077495a8771675 Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen at sifive.com>
Date: Wed, 22 Apr 2026 01:04:19 -0700
Subject: [PATCH 2/3] Replace scalar access cost with basic cost
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index cb3dbcbce60fc..ff1aeca966185 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1161,11 +1161,8 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
if (TLI->isLegalInterleavedAccessType(SubVecTy, NumOfFields, Alignment,
AddressSpace, DL)) {
// The cost is proportional to the total number of element accesses.
- InstructionCost MemOpCost =
- getMemoryOpCost(Opcode, FVTy->getElementType(), Alignment, 0,
- CostKind, {TTI::OK_AnyValue, TTI::OP_None});
unsigned NumAccesses = getEstimatedVLFor(FVTy);
- return NumAccesses * MemOpCost;
+ return NumAccesses * TTI::TCC_Basic;
}
}
}
>From 6663051b79839c258ed3a303f63563e9381f9dbb Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen at sifive.com>
Date: Mon, 27 Apr 2026 03:23:39 -0700
Subject: [PATCH 3/3] Add assertion for Indices
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index ff1aeca966185..2d0d387e2ad43 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1148,6 +1148,9 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
// shufflevectors and a wide masked store. The interleaved memory access pass
// will lower them into vlsseg/vssseg intrinsics.
if (UseMaskForGaps) {
+ assert(llvm::is_sorted(Indices) && "Indices must be sorted");
+ assert(llvm::adjacent_find(Indices) == Indices.end() &&
+ "Indices should not contain duplicate elements");
unsigned NumOfFields = Indices.size();
bool IsTailGapOnly = NumOfFields > 1 && (NumOfFields == Indices.back() + 1);
if (IsTailGapOnly &&
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