[llvm] [AArch64][SelectionDAG][SVE] Fold following extend(icmp) patterns (PR #192052)

[Ricardo Jesus via llvm-commits]

================
@@ -1086,17 +2044,66 @@ define void @icmp_sge_v16i16(ptr %a) {
 }
 
 define void @icmp_sgt_v8i32(ptr %a) {
-; CHECK-LABEL: icmp_sgt_v8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x0]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    cmpgt p1.s, p0/z, z0.s, #-8
-; CHECK-NEXT:    cmpgt p2.s, p0/z, z1.s, #-8
-; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    ret
+; CHECK-SVE-LABEL: icmp_sgt_v8i32:
+; CHECK-SVE:       // %bb.0:
+; CHECK-SVE-NEXT:    ldp q0, q1, [x0]
+; CHECK-SVE-NEXT:    ptrue p0.s, vl4
+; CHECK-SVE-NEXT:    cmpgt p1.s, p0/z, z0.s, #-8
+; CHECK-SVE-NEXT:    cmpgt p2.s, p0/z, z1.s, #-8
+; CHECK-SVE-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-SVE-NEXT:    mov z1.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-SVE-NEXT:    stp q0, q1, [x0]
+; CHECK-SVE-NEXT:    ret
 ;
+; CHECK-SME-LABEL: icmp_sgt_v8i32:
+; CHECK-SME:       // %bb.0:
+; CHECK-SME-NEXT:    mov z0.s, #-8 // =0xfffffffffffffff8
----------------
rj-jesus wrote:

Replacing one compare instruction with one vector instruction seems reasonable. However, replacing one compare with two vector instructions is more dubious. It may be preferable under certain conditions on some targets, but I don't think it's universally preferable. It's likely not very useful here (https://godbolt.org/z/E3qGajae5), and may lead to issues due to higher register usage and code size.

https://github.com/llvm/llvm-project/pull/192052