[llvm] [LoopFusion][NFC] UTC gen some tests (PR #193755)
Madhur Amilkanthwar via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 23 06:57:40 PDT 2026
https://github.com/madhur13490 created https://github.com/llvm/llvm-project/pull/193755
Some variables need rename as UTC normalizes IR value names. Also, remove dead variable `%M` and `%N` from `double_loop_nest_inner_guard.ll`
>From e884f3f883d2e7feafc56a80b38dfebb05329827 Mon Sep 17 00:00:00 2001
From: Madhur Amilkanthwar <madhura at nvidia.com>
Date: Wed, 22 Apr 2026 21:51:27 -0700
Subject: [PATCH] [LoopFusion][NFC] UTC gen some tests
Some variables need rename as UTC normalizes IR value names.
---
.../double_loop_nest_inner_guard.ll | 85 +++++++------
.../triple_loop_nest_inner_guard.ll | 117 ++++++++++--------
2 files changed, 116 insertions(+), 86 deletions(-)
diff --git a/llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll b/llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
index f6eab83b5d154..2b7b3f7c87410 100644
--- a/llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
+++ b/llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes=loop-fusion < %s 2>&1 | FileCheck %s
; Verify that LoopFusion can fuse two double-loop nests with guarded inner
@@ -7,42 +8,54 @@
@b = common global [10 x [10 x i32]] zeroinitializer
@c = common global [10 x [10 x i32]] zeroinitializer
-; CHECK-LABEL: @double_loop_nest_inner_guard
-; CHECK: br i1 %{{.*}}, label %[[OUTER_PH:outer1.ph]], label %[[FUNC_EXIT:func_exit]]
-
-; CHECK: [[OUTER_PH]]:
-; CHECK: br label %[[OUTER_BODY_INNER_GUARD:outer1.body.inner.guard]]
-
-; CHECK: [[OUTER_BODY_INNER_GUARD]]:
-; CHECK: br i1 %{{.*}}, label %[[INNER_PH:inner1.ph]], label %[[OUTER_LATCH:outer2.latch]]
-
-; CHECK: [[INNER_PH]]:
-; CHECK-NEXT: br label %[[INNER_BODY:inner1.body]]
-
-; CHECK: [[INNER_BODY]]:
-; First loop body.
-; CHECK: load
-; CHECK: add
-; CHECK: store
-; Second loop body.
-; CHECK: load
-; CHECK: mul
-; CHECK: store
-; CHECK: br i1 %{{.*}}, label %[[INNER_EXIT:inner2.exit]], label %[[INNER_BODY:inner1.body]]
-
-; CHECK: [[INNER_EXIT]]:
-; CHECK-NEXT: br label %[[OUTER_LATCH:outer2.latch]]
-
-; CHECK: [[OUTER_LATCH]]:
-; CHECK: br i1 %{{.*}}, label %[[OUTER_EXIT:outer2.exit]], label %[[OUTER_BODY_INNER_GUARD]]
-
-; CHECK: [[OUTER_EXIT]]:
-; CHECK-NEXT: br label %[[FUNC_EXIT:func_exit]]
-
-; CHECK: [[FUNC_EXIT]]:
-; CHECK-NEXT: ret
-
-define i32 @double_loop_nest_inner_guard(i32 %m, i32 %n, i32 %M, i32 %N) {
+define i32 @double_loop_nest_inner_guard(i32 %m, i32 %n) {
+; CHECK-LABEL: define i32 @double_loop_nest_inner_guard(
+; CHECK-SAME: i32 [[M:%.*]], i32 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[M]], 0
+; CHECK-NEXT: br i1 [[CMP63]], label %[[OUTER1_PH:.*]], label %[[FUNC_EXIT:.*]]
+; CHECK: [[OUTER1_PH]]:
+; CHECK-NEXT: [[CMP261:%.*]] = icmp sgt i32 [[N]], 0
+; CHECK-NEXT: [[WIDE_TRIP_COUNT76:%.*]] = zext i32 [[M]] to i64
+; CHECK-NEXT: [[WIDE_TRIP_COUNT72:%.*]] = zext i32 [[N]] to i64
+; CHECK-NEXT: br label %[[OUTER1_BODY_INNER_GUARD:.*]]
+; CHECK: [[OUTER1_BODY_INNER_GUARD]]:
+; CHECK-NEXT: [[IV74:%.*]] = phi i64 [ 0, %[[OUTER1_PH]] ], [ [[IV_NEXT75:%.*]], %[[OUTER2_LATCH:.*]] ]
+; CHECK-NEXT: [[IV66:%.*]] = phi i64 [ [[IV_NEXT67:%.*]], %[[OUTER2_LATCH]] ], [ 0, %[[OUTER1_PH]] ]
+; CHECK-NEXT: br i1 [[CMP261]], label %[[INNER1_PH:.*]], label %[[OUTER2_LATCH]]
+; CHECK: [[INNER1_PH]]:
+; CHECK-NEXT: br label %[[INNER1_BODY:.*]]
+; CHECK: [[INNER1_BODY]]:
+; CHECK-NEXT: [[IV70:%.*]] = phi i64 [ [[IV_NEXT71:%.*]], %[[INNER1_BODY]] ], [ 0, %[[INNER1_PH]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[INNER1_BODY]] ], [ 0, %[[INNER1_PH]] ]
+; CHECK-NEXT: [[IDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr @a, i64 0, i64 [[IV74]], i64 [[IV70]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[IDX6]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 2
+; CHECK-NEXT: [[IDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr @b, i64 0, i64 [[IV74]], i64 [[IV70]]
+; CHECK-NEXT: store i32 [[ADD]], ptr [[IDX10]], align 4
+; CHECK-NEXT: [[IV_NEXT71]] = add nuw nsw i64 [[IV70]], 1
+; CHECK-NEXT: [[EXITCOND73:%.*]] = icmp eq i64 [[IV_NEXT71]], [[WIDE_TRIP_COUNT72]]
+; CHECK-NEXT: [[IDX27:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr @a, i64 0, i64 [[IV66]], i64 [[IV]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[IDX27]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP1]], 1
+; CHECK-NEXT: [[IDX31:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr @c, i64 0, i64 [[IV66]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[MUL]], ptr [[IDX31]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT72]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[INNER2_EXIT:.*]], label %[[INNER1_BODY]]
+; CHECK: [[INNER2_EXIT]]:
+; CHECK-NEXT: br label %[[OUTER2_LATCH]]
+; CHECK: [[OUTER2_LATCH]]:
+; CHECK-NEXT: [[IV_NEXT75]] = add nuw nsw i64 [[IV74]], 1
+; CHECK-NEXT: [[EXITCOND77:%.*]] = icmp eq i64 [[IV_NEXT75]], [[WIDE_TRIP_COUNT76]]
+; CHECK-NEXT: [[IV_NEXT67]] = add nuw nsw i64 [[IV66]], 1
+; CHECK-NEXT: [[EXITCOND69:%.*]] = icmp eq i64 [[IV_NEXT67]], [[WIDE_TRIP_COUNT76]]
+; CHECK-NEXT: br i1 [[EXITCOND69]], label %[[OUTER2_EXIT:.*]], label %[[OUTER1_BODY_INNER_GUARD]]
+; CHECK: [[OUTER2_EXIT]]:
+; CHECK-NEXT: br label %[[FUNC_EXIT]]
+; CHECK: [[FUNC_EXIT]]:
+; CHECK-NEXT: ret i32 undef
+;
entry:
%cmp63 = icmp sgt i32 %m, 0
br i1 %cmp63, label %outer1.ph, label %func_exit
diff --git a/llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll b/llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
index 2ad211685aa47..8d558a96009d3 100644
--- a/llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
+++ b/llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes=loop-fusion < %s 2>&1 | FileCheck %s
; Verify that LoopFusion can fuse two triple-loop nests with guarded inner
@@ -7,64 +8,80 @@
@b = common global [10 x [10 x [10 x i32]]] zeroinitializer
@c = common global [10 x [10 x [10 x i32]]] zeroinitializer
-; CHECK-LABEL: @triple_loop_nest_inner_guard
-; CHECK: br i1 %{{.*}}, label %[[OUTER_PH:outer1.ph]], label %[[FUNC_EXIT:func_exit]]
-
-; CHECK: [[OUTER_PH]]:
-; CHECK: br label %[[OUTER_BODY_MIDDLE_GUARD:outer1.body.middle1.guard]]
-
-; CHECK: [[OUTER_BODY_MIDDLE_GUARD]]:
-; CHECK: br i1 %{{.*}}, label %[[MIDDLE_PH:middle1.ph]], label %[[OUTER_LATCH:outer2.latch]]
-
-; CHECK: [[MIDDLE_PH]]:
-; CHECK-NEXT: br label %[[MIDDLE_BODY_INNER_GUARD:middle1.body.inner1.guard]]
-
-; CHECK: [[MIDDLE_BODY_INNER_GUARD]]:
-; CHECK: br i1 %{{.*}}, label %[[INNER_PH:inner1.ph]], label %[[MIDDLE_LATCH:middle2.latch]]
-
-; CHECK: [[INNER_PH]]:
-; CHECK-NEXT: br label %[[INNER_BODY:inner1.body]]
-
-; CHECK: [[INNER_BODY]]:
-; First loop body.
-; CHECK: load
-; CHECK: add
-; CHECK: store
-; Second loop body.
-; CHECK: load
-; CHECK: mul
-; CHECK: store
-; CHECK: br i1 %{{.*}}, label %[[INNER_EXIT:inner2.exit]], label %[[INNER_BODY:inner1.body]]
-
-; CHECK: [[INNER_EXIT]]:
-; CHECK-NEXT: br label %[[MIDDLE_LATCH:middle2.latch]]
-
-; CHECK: [[MIDDLE_LATCH]]:
-; CHECK: br i1 %{{.*}}, label %[[MIDDLE_EXIT:middle2.exit]], label %[[MIDDLE_BODY_INNER_GUARD]]
-
-; CHECK: [[MIDDLE_EXIT]]:
-; CHECK-NEXT: br label %[[OUTER_LATCH:outer2.latch]]
-
-; CHECK: [[OUTER_LATCH]]:
-; CHECK: br i1 %{{.*}}, label %[[OUTER_EXIT:outer2.exit]], label %[[OUTER_BODY_MIDDLE_GUARD]]
-
-; CHECK: [[OUTER_EXIT]]:
-; CHECK-NEXT: br label %[[FUNC_EXIT:func_exit]]
-
-; CHECK: [[FUNC_EXIT]]:
-; CHECK-NEXT: ret
-
-define i32 @triple_loop_nest_inner_guard(i32 %m, i32 %n, i32 %M, i32 %N) {
+define i32 @triple_loop_nest_inner_guard(i32 %m, i32 %n, i32 %mm, i32 %nn) {
+; CHECK-LABEL: define i32 @triple_loop_nest_inner_guard(
+; CHECK-SAME: i32 [[M:%.*]], i32 [[N:%.*]], i32 [[MM:%.*]], i32 [[NN:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CMP101:%.*]] = icmp sgt i32 [[M]], 0
+; CHECK-NEXT: br i1 [[CMP101]], label %[[OUTER1_PH:.*]], label %[[FUNC_EXIT:.*]]
+; CHECK: [[OUTER1_PH]]:
+; CHECK-NEXT: [[CMP298:%.*]] = icmp sgt i32 [[N]], 0
+; CHECK-NEXT: [[CMP696:%.*]] = icmp sgt i32 [[MM]], 0
+; CHECK-NEXT: [[WIDE_TRIP_COUNT122:%.*]] = zext i32 [[M]] to i64
+; CHECK-NEXT: [[WIDE_TRIP_COUNT118:%.*]] = zext i32 [[N]] to i64
+; CHECK-NEXT: [[WIDE_TRIP_COUNT114:%.*]] = zext i32 [[MM]] to i64
+; CHECK-NEXT: br label %[[OUTER1_BODY_MIDDLE1_GUARD:.*]]
+; CHECK: [[OUTER1_BODY_MIDDLE1_GUARD]]:
+; CHECK-NEXT: [[IV120:%.*]] = phi i64 [ 0, %[[OUTER1_PH]] ], [ [[IV_NEXT121:%.*]], %[[OUTER2_LATCH:.*]] ]
+; CHECK-NEXT: [[IV108:%.*]] = phi i64 [ [[IV_NEXT109:%.*]], %[[OUTER2_LATCH]] ], [ 0, %[[OUTER1_PH]] ]
+; CHECK-NEXT: br i1 [[CMP298]], label %[[MIDDLE1_PH:.*]], label %[[OUTER2_LATCH]]
+; CHECK: [[MIDDLE1_PH]]:
+; CHECK-NEXT: br label %[[MIDDLE1_BODY_INNER1_GUARD:.*]]
+; CHECK: [[MIDDLE1_BODY_INNER1_GUARD]]:
+; CHECK-NEXT: [[IV116:%.*]] = phi i64 [ [[IV_NEXT117:%.*]], %[[MIDDLE2_LATCH:.*]] ], [ 0, %[[MIDDLE1_PH]] ]
+; CHECK-NEXT: [[IV104:%.*]] = phi i64 [ [[IV_NEXT105:%.*]], %[[MIDDLE2_LATCH]] ], [ 0, %[[MIDDLE1_PH]] ]
+; CHECK-NEXT: br i1 [[CMP696]], label %[[INNER1_PH:.*]], label %[[MIDDLE2_LATCH]]
+; CHECK: [[INNER1_PH]]:
+; CHECK-NEXT: br label %[[INNER1_BODY:.*]]
+; CHECK: [[INNER1_BODY]]:
+; CHECK-NEXT: [[IV112:%.*]] = phi i64 [ [[IV_NEXT113:%.*]], %[[INNER1_BODY]] ], [ 0, %[[INNER1_PH]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[INNER1_BODY]] ], [ 0, %[[INNER1_PH]] ]
+; CHECK-NEXT: [[IDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr @a, i64 0, i64 [[IV120]], i64 [[IV116]], i64 [[IV112]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[IDX12]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 2
+; CHECK-NEXT: [[IDX18:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr @b, i64 0, i64 [[IV120]], i64 [[IV116]], i64 [[IV112]]
+; CHECK-NEXT: store i32 [[ADD]], ptr [[IDX18]], align 4
+; CHECK-NEXT: [[IV_NEXT113]] = add nuw nsw i64 [[IV112]], 1
+; CHECK-NEXT: [[EXITCOND115:%.*]] = icmp eq i64 [[IV_NEXT113]], [[WIDE_TRIP_COUNT114]]
+; CHECK-NEXT: [[IDX45:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr @a, i64 0, i64 [[IV108]], i64 [[IV104]], i64 [[IV]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[IDX45]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[TMP1]], 1
+; CHECK-NEXT: [[IDX51:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr @c, i64 0, i64 [[IV108]], i64 [[IV104]], i64 [[IV]]
+; CHECK-NEXT: store i32 [[MUL]], ptr [[IDX51]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT114]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[INNER2_EXIT:.*]], label %[[INNER1_BODY]]
+; CHECK: [[INNER2_EXIT]]:
+; CHECK-NEXT: br label %[[MIDDLE2_LATCH]]
+; CHECK: [[MIDDLE2_LATCH]]:
+; CHECK-NEXT: [[IV_NEXT117]] = add nuw nsw i64 [[IV116]], 1
+; CHECK-NEXT: [[EXITCOND119:%.*]] = icmp eq i64 [[IV_NEXT117]], [[WIDE_TRIP_COUNT118]]
+; CHECK-NEXT: [[IV_NEXT105]] = add nuw nsw i64 [[IV104]], 1
+; CHECK-NEXT: [[EXITCOND107:%.*]] = icmp eq i64 [[IV_NEXT105]], [[WIDE_TRIP_COUNT118]]
+; CHECK-NEXT: br i1 [[EXITCOND107]], label %[[MIDDLE2_EXIT:.*]], label %[[MIDDLE1_BODY_INNER1_GUARD]]
+; CHECK: [[MIDDLE2_EXIT]]:
+; CHECK-NEXT: br label %[[OUTER2_LATCH]]
+; CHECK: [[OUTER2_LATCH]]:
+; CHECK-NEXT: [[IV_NEXT121]] = add nuw nsw i64 [[IV120]], 1
+; CHECK-NEXT: [[EXITCOND123:%.*]] = icmp eq i64 [[IV_NEXT121]], [[WIDE_TRIP_COUNT122]]
+; CHECK-NEXT: [[IV_NEXT109]] = add nuw nsw i64 [[IV108]], 1
+; CHECK-NEXT: [[EXITCOND111:%.*]] = icmp eq i64 [[IV_NEXT109]], [[WIDE_TRIP_COUNT122]]
+; CHECK-NEXT: br i1 [[EXITCOND111]], label %[[OUTER2_EXIT:.*]], label %[[OUTER1_BODY_MIDDLE1_GUARD]]
+; CHECK: [[OUTER2_EXIT]]:
+; CHECK-NEXT: br label %[[FUNC_EXIT]]
+; CHECK: [[FUNC_EXIT]]:
+; CHECK-NEXT: ret i32 undef
+;
entry:
%cmp101 = icmp sgt i32 %m, 0
br i1 %cmp101, label %outer1.ph, label %func_exit
outer1.ph:
%cmp298 = icmp sgt i32 %n, 0
- %cmp696 = icmp sgt i32 %M, 0
+ %cmp696 = icmp sgt i32 %mm, 0
%wide.trip.count122 = zext i32 %m to i64
%wide.trip.count118 = zext i32 %n to i64
- %wide.trip.count114 = zext i32 %M to i64
+ %wide.trip.count114 = zext i32 %mm to i64
br label %outer1.body.middle1.guard
outer1.body.middle1.guard:
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