[llvm] [SPIR-V] Fix half precision OpConstant for log10/exp10 lowering (PR #193730)
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Thu Apr 23 05:54:35 PDT 2026
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index a3dd4b27e..2a6ddddce 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -3876,9 +3876,9 @@ bool SPIRVInstructionSelector::selectExp10(Register ResVReg,
// SPIR-V validation when the type is narrower than 32 bits (e.g. half).
APFloat ConstVal(3.3219280948873623);
bool LosesInfo;
- ConstVal.convert(getZeroFP(GR.getTypeForSPIRVType(SpirvScalarType))
- .getSemantics(),
- APFloat::rmNearestTiesToEven, &LosesInfo);
+ ConstVal.convert(
+ getZeroFP(GR.getTypeForSPIRVType(SpirvScalarType)).getSemantics(),
+ APFloat::rmNearestTiesToEven, &LosesInfo);
Register ConstReg =
GR.buildConstantFP(ConstVal, MIRBuilder, SpirvScalarType);
Register ArgReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
@@ -6380,11 +6380,10 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
// validation when the type is narrower than 32 bits (e.g. half).
APFloat ScaleVal(0.30103);
bool LosesInfo;
- ScaleVal.convert(getZeroFP(GR.getTypeForSPIRVType(SpirvScalarType))
- .getSemantics(),
- APFloat::rmNearestTiesToEven, &LosesInfo);
- Register ScaleReg =
- GR.buildConstantFP(ScaleVal, MIRBuilder, SpirvScalarType);
+ ScaleVal.convert(
+ getZeroFP(GR.getTypeForSPIRVType(SpirvScalarType)).getSemantics(),
+ APFloat::rmNearestTiesToEven, &LosesInfo);
+ Register ScaleReg = GR.buildConstantFP(ScaleVal, MIRBuilder, SpirvScalarType);
// Multiply log2(x) by 0.30103 to get log10(x) result.
auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector
``````````
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https://github.com/llvm/llvm-project/pull/193730
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