[llvm] [LoongArch] Introduce LASX instruction patterns for vector sign/zero extensions (PR #193727)
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llvm-commits at lists.llvm.org
Thu Apr 23 05:32:03 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: lrzlin
<details>
<summary>Changes</summary>
This patch introduces LASX only legalization and instruction patterns for vector sign and zero extension operations, which is basically copy from the https://github.com/llvm/llvm-project/pull/160810 with some minor change (e.g. deleted unused tablegen pattern).
---
Full diff: https://github.com/llvm/llvm-project/pull/193727.diff
4 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+9)
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+60-5)
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll (+227)
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll (+228)
``````````diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 446d27805fb35..fcf2f70c6eaee 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -467,6 +467,15 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FMAXNUM, VT, Legal);
}
setOperationAction(ISD::FP_ROUND, MVT::v4f32, Custom);
+ for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16}) {
+ setOperationAction(ISD::SIGN_EXTEND, VT, Legal);
+ setOperationAction(ISD::ZERO_EXTEND, VT, Legal);
+ }
+ for (MVT VT :
+ {MVT::v2i64, MVT::v4i32, MVT::v4i64, MVT::v8i16, MVT::v8i32}) {
+ setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
+ setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
+ }
}
// Set DAG combine for LA32 and LA64.
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index b807b5927585b..8402f569bd94f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1768,7 +1768,7 @@ def : Pat<(vector_insert v4f64:$xd, FPR64:$fj, uimm2:$imm),
def : Pat<(v8f32 (scalar_to_vector FPR32:$fj)),
(SUBREG_TO_REG FPR32:$fj, sub_32)>;
def : Pat<(v4f64 (scalar_to_vector FPR64:$fj)),
- (SUBREG_TO_REG FPR64:$fj, sub_64)>;
+ (SUBREG_TO_REG FPR64:$fj, sub_64)>;
// XVPICKVE2GR_W[U]
def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32),
@@ -2177,6 +2177,61 @@ def : Pat<(int_loongarch_lasx_insert_128_hi_d (v4f64 LASX256:$src), (v2f64 LSX12
(XVPERMI_Q LASX256:$src, (INSERT_SUBREG (IMPLICIT_DEF), LSX128:$lo, sub_128), 2)>;
def : Pat<(int_loongarch_lasx_insert_128_hi (v4i64 LASX256:$src), (v2i64 LSX128:$lo)),
(XVPERMI_Q LASX256:$src, (INSERT_SUBREG (IMPLICIT_DEF), LSX128:$lo, sub_128), 2)>;
+
+// Sign extensions
+def : Pat<(v4i64 (sext v4i32:$vj)),
+ (v4i64 (VEXT2XV_D_W (SUBREG_TO_REG v4i32:$vj, sub_128)))>;
+def : Pat<(v8i32 (sext v8i16:$vj)),
+ (v8i32 (VEXT2XV_W_H (SUBREG_TO_REG v8i16:$vj, sub_128)))>;
+def : Pat<(v16i16 (sext v16i8:$vj)),
+ (v16i16 (VEXT2XV_H_B (SUBREG_TO_REG v16i8:$vj, sub_128)))>;
+
+def : Pat<(v2i64 (sext_invec v16i8:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_D_B (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v2i64 (sext_invec v8i16:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_D_H (SUBREG_TO_REG v8i16:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v2i64 (sext_invec v4i32:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_D_W (SUBREG_TO_REG v4i32:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v4i32 (sext_invec v16i8:$vj)),
+ (v4i32 (EXTRACT_SUBREG (VEXT2XV_W_B (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v4i32 (sext_invec v8i16:$vj)),
+ (v4i32 (EXTRACT_SUBREG (VEXT2XV_W_H (SUBREG_TO_REG v8i16:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v8i16 (sext_invec v16i8:$vj)),
+ (v8i16 (EXTRACT_SUBREG (VEXT2XV_H_B (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+
+// Zero extensions
+def : Pat<(v4i64 (zext v4i32:$vj)),
+ (v4i64 (VEXT2XV_DU_WU (SUBREG_TO_REG v4i32:$vj, sub_128)))>;
+def : Pat<(v8i32 (zext v8i16:$vj)),
+ (v8i32 (VEXT2XV_WU_HU (SUBREG_TO_REG v8i16:$vj, sub_128)))>;
+def : Pat<(v16i16 (zext v16i8:$vj)),
+ (v16i16 (VEXT2XV_HU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)))>;
+
+def : Pat<(v2i64 (zext_invec v16i8:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_DU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v2i64 (zext_invec v8i16:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_DU_HU (SUBREG_TO_REG v8i16:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v2i64 (zext_invec v4i32:$vj)),
+ (v2i64 (EXTRACT_SUBREG (VEXT2XV_DU_WU (SUBREG_TO_REG v4i32:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v4i32 (zext_invec v16i8:$vj)),
+ (v4i32 (EXTRACT_SUBREG (VEXT2XV_WU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v4i32 (zext_invec v8i16:$vj)),
+ (v4i32 (EXTRACT_SUBREG (VEXT2XV_WU_HU (SUBREG_TO_REG v8i16:$vj, sub_128)),
+ sub_128))>;
+def : Pat<(v8i16 (zext_invec v16i8:$vj)),
+ (v8i16 (EXTRACT_SUBREG (VEXT2XV_HU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)),
+ sub_128))>;
+
} // Predicates = [HasExtLASX]
/// Intrinsic pattern
@@ -2477,13 +2532,13 @@ foreach Inst = ["XVFRECIPE_D", "XVFRSQRTE_D"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v4f64 LASX256:$xj)),
(!cast<LAInst>(Inst) LASX256:$xj)>;
-def : Pat<(loongarch_vfrecipe v8f32:$src),
+def : Pat<(loongarch_vfrecipe v8f32:$src),
(XVFRECIPE_S v8f32:$src)>;
-def : Pat<(loongarch_vfrecipe v4f64:$src),
+def : Pat<(loongarch_vfrecipe v4f64:$src),
(XVFRECIPE_D v4f64:$src)>;
-def : Pat<(loongarch_vfrsqrte v8f32:$src),
+def : Pat<(loongarch_vfrsqrte v8f32:$src),
(XVFRSQRTE_S v8f32:$src)>;
-def : Pat<(loongarch_vfrsqrte v4f64:$src),
+def : Pat<(loongarch_vfrsqrte v4f64:$src),
(XVFRSQRTE_D v4f64:$src)>;
}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
new file mode 100644
index 0000000000000..906ff8f79f178
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
@@ -0,0 +1,227 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64
+
+define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i8_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.h $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.d.b $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i8>, ptr %ptr
+ %B = sext <2 x i8> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i8_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.w.b $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = sext <4 x i8> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_8i8_to_8i16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.h.b $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_8i8_to_8i16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.h.b $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = sext <8 x i8> %A to <8 x i16>
+ store <8 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i16_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.d.h $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i16>, ptr %ptr
+ %B = sext <2 x i16> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_4i16_to_4i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.w.h $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_4i16_to_4i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.w.h $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = sext <4 x i16> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_sext_2i32_to_2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.d.w $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_sext_2i32_to_2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.d.w $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <2 x i32>, ptr %ptr
+ %B = sext <2 x i32> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i16>
+ store <16 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.w.h $xr1, $xr1
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 32
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i32>
+ store <16 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.w.h $xr1, $xr1
+; CHECK-NEXT: xvpermi.q $xr2, $xr1, 1
+; CHECK-NEXT: vext2xv.d.w $xr2, $xr2
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr3, $xr0, 1
+; CHECK-NEXT: vext2xv.d.w $xr3, $xr3
+; CHECK-NEXT: vext2xv.d.w $xr1, $xr1
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 64
+; CHECK-NEXT: xvst $xr3, $a1, 32
+; CHECK-NEXT: xvst $xr2, $a1, 96
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i64>
+ store <16 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i16_to_8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i16_to_8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.d.w $xr1, $xr1
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 32
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i32_to_4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i32>, ptr %ptr
+ %B = sext <4 x i32> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
new file mode 100644
index 0000000000000..b48bfc25b7c41
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
@@ -0,0 +1,228 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64
+
+
+define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_2i8_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.h $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i8>, ptr %ptr
+ %B = zext <2 x i8> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_4i8_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.wu.bu $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = zext <4 x i8> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_zext_8i8_to_8i16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.hu.bu $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_8i8_to_8i16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.hu.bu $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = zext <8 x i8> %A to <8 x i16>
+ store <8 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_2i16_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a0, $a0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.du.hu $xr0, $xr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i16>, ptr %ptr
+ %B = zext <2 x i16> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_zext_4i16_to_4i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.wu.hu $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_4i16_to_4i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.wu.hu $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = zext <4 x i16> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
+; LA32-LABEL: load_zext_2i32_to_2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vext2xv.du.wu $xr0, $xr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_2i32_to_2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vext2xv.du.wu $xr0, $xr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %A = load <2 x i32>, ptr %ptr
+ %B = zext <2 x i32> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i16>
+ store <16 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.wu.hu $xr1, $xr1
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 32
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i32>
+ store <16 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.wu.hu $xr1, $xr1
+; CHECK-NEXT: xvpermi.q $xr2, $xr1, 1
+; CHECK-NEXT: vext2xv.du.wu $xr2, $xr2
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr3, $xr0, 1
+; CHECK-NEXT: vext2xv.du.wu $xr3, $xr3
+; CHECK-NEXT: vext2xv.du.wu $xr1, $xr1
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 64
+; CHECK-NEXT: xvst $xr3, $a1, 32
+; CHECK-NEXT: xvst $xr2, $a1, 96
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i64>
+ store <16 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i16_to_8i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_8i16_to_8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = zext <8 x i16> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i16_to_8i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_8i16_to_8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vext2xv.du.wu $xr1, $xr1
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr1, $a1, 32
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = zext <8 x i16> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i32_to_4i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_4i32_to_4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i32>, ptr %ptr
+ %B = zext <4 x i32> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/193727
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