[llvm] [RISCV] Add bf16 tests for interleave and deinterleave (PR #193720)
Boyao Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 23 04:45:11 PDT 2026
https://github.com/BoyaoWang430 created https://github.com/llvm/llvm-project/pull/193720
Add missing bf16 tests for interleave and deinterleave
>From 0aff393752647b992341cf8dd6df467004630852 Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Thu, 23 Apr 2026 19:43:53 +0800
Subject: [PATCH] [RISCV] Add bf16 tests for interleave and deinterleave
---
.../fixed-vectors-shuffle-deinterleave2.ll | 230 ++++-
.../fixed-vectors-shuffle-zipeven-zipodd.ll | 40 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 214 +++-
.../RISCV/rvv/vector-interleave-fixed.ll | 969 ++++++++++++++++--
4 files changed, 1331 insertions(+), 122 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 175693318500b..b26e18deb5a4a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+zvl256b \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,V
-; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zvfh,+zvl256b \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zvfh,+zvfbfmin,+zvl256b \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZVE32F
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-xrivosvizip \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+zvl256b,+experimental-xrivosvizip \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZIP
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-zvzip \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+zvl256b,+experimental-zvzip \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZVZIP
@@ -173,6 +173,52 @@ entry:
ret void
}
+define void @vnsrl_0_bfloat(ptr %in, ptr %out) {
+;
+;
+;
+; V-LABEL: vnsrl_0_bfloat:
+; V: # %bb.0: # %entry
+; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vnsrl.wi v8, v8, 0
+; V-NEXT: vse16.v v8, (a1)
+; V-NEXT: ret
+;
+; ZVE32F-LABEL: vnsrl_0_bfloat:
+; ZVE32F: # %bb.0: # %entry
+; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVE32F-NEXT: vle16.v v8, (a0)
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
+; ZVE32F-NEXT: vse16.v v8, (a1)
+; ZVE32F-NEXT: ret
+;
+; ZIP-LABEL: vnsrl_0_bfloat:
+; ZIP: # %bb.0: # %entry
+; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZIP-NEXT: vse16.v v8, (a1)
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_bfloat:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
+entry:
+ %0 = load <8 x bfloat>, ptr %in, align 2
+ %shuffle.i5 = shufflevector <8 x bfloat> %0, <8 x bfloat> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ store <4 x bfloat> %shuffle.i5, ptr %out, align 2
+ ret void
+}
+
define void @vnsrl_16_half(ptr %in, ptr %out) {
; V-LABEL: vnsrl_16_half:
; V: # %bb.0: # %entry
@@ -216,6 +262,52 @@ entry:
ret void
}
+define void @vnsrl_16_bfloat(ptr %in, ptr %out) {
+;
+;
+;
+; V-LABEL: vnsrl_16_bfloat:
+; V: # %bb.0: # %entry
+; V-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vnsrl.wi v8, v8, 16
+; V-NEXT: vse16.v v8, (a1)
+; V-NEXT: ret
+;
+; ZVE32F-LABEL: vnsrl_16_bfloat:
+; ZVE32F: # %bb.0: # %entry
+; ZVE32F-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVE32F-NEXT: vle16.v v8, (a0)
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vnsrl.wi v8, v8, 16
+; ZVE32F-NEXT: vse16.v v8, (a1)
+; ZVE32F-NEXT: ret
+;
+; ZIP-LABEL: vnsrl_16_bfloat:
+; ZIP: # %bb.0: # %entry
+; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZIP-NEXT: vse16.v v8, (a1)
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_bfloat:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
+entry:
+ %0 = load <8 x bfloat>, ptr %in, align 2
+ %shuffle.i5 = shufflevector <8 x bfloat> %0, <8 x bfloat> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ store <4 x bfloat> %shuffle.i5, ptr %out, align 2
+ ret void
+}
+
define void @vnsrl_0_i32(ptr %in, ptr %out) {
; V-LABEL: vnsrl_0_i32:
; V: # %bb.0: # %entry
@@ -634,8 +726,8 @@ define void @vnsrl_0_i8_undef_negative(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: lui a0, %hi(.LCPI17_0)
-; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; CHECK-NEXT: lui a0, %hi(.LCPI19_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI19_0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -1205,6 +1297,69 @@ entry:
ret void
}
+define void @vnsrl_0_bfloat_two_source(ptr %in0, ptr %in1, ptr %out) {
+;
+;
+;
+; V-LABEL: vnsrl_0_bfloat_two_source:
+; V: # %bb.0: # %entry
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vle16.v v8, (a1)
+; V-NEXT: vle16.v v9, (a0)
+; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; V-NEXT: vnsrl.wi v8, v8, 0
+; V-NEXT: vnsrl.wi v9, v9, 0
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vslideup.vi v9, v8, 2
+; V-NEXT: vse16.v v9, (a2)
+; V-NEXT: ret
+;
+; ZVE32F-LABEL: vnsrl_0_bfloat_two_source:
+; ZVE32F: # %bb.0: # %entry
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vle16.v v8, (a1)
+; ZVE32F-NEXT: vle16.v v9, (a0)
+; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
+; ZVE32F-NEXT: vnsrl.wi v9, v9, 0
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vslideup.vi v9, v8, 2
+; ZVE32F-NEXT: vse16.v v9, (a2)
+; ZVE32F-NEXT: ret
+;
+; ZIP-LABEL: vnsrl_0_bfloat_two_source:
+; ZIP: # %bb.0: # %entry
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vle16.v v8, (a1)
+; ZIP-NEXT: vle16.v v9, (a0)
+; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vslideup.vi v9, v8, 2
+; ZIP-NEXT: vse16.v v9, (a2)
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_bfloat_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
+entry:
+ %0 = load <4 x bfloat>, ptr %in0, align 2
+ %1 = load <4 x bfloat>, ptr %in1, align 2
+ %shuffle.i5 = shufflevector <4 x bfloat> %0, <4 x bfloat> %1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ store <4 x bfloat> %shuffle.i5, ptr %out, align 2
+ ret void
+}
+
define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; V-LABEL: vnsrl_16_half_two_source:
; V: # %bb.0: # %entry
@@ -1265,6 +1420,69 @@ entry:
ret void
}
+define void @vnsrl_16_bfloat_two_source(ptr %in0, ptr %in1, ptr %out) {
+;
+;
+;
+; V-LABEL: vnsrl_16_bfloat_two_source:
+; V: # %bb.0: # %entry
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vle16.v v8, (a1)
+; V-NEXT: vle16.v v9, (a0)
+; V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; V-NEXT: vnsrl.wi v8, v8, 16
+; V-NEXT: vnsrl.wi v9, v9, 16
+; V-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; V-NEXT: vslideup.vi v9, v8, 2
+; V-NEXT: vse16.v v9, (a2)
+; V-NEXT: ret
+;
+; ZVE32F-LABEL: vnsrl_16_bfloat_two_source:
+; ZVE32F: # %bb.0: # %entry
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vle16.v v8, (a1)
+; ZVE32F-NEXT: vle16.v v9, (a0)
+; ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVE32F-NEXT: vnsrl.wi v8, v8, 16
+; ZVE32F-NEXT: vnsrl.wi v9, v9, 16
+; ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVE32F-NEXT: vslideup.vi v9, v8, 2
+; ZVE32F-NEXT: vse16.v v9, (a2)
+; ZVE32F-NEXT: ret
+;
+; ZIP-LABEL: vnsrl_16_bfloat_two_source:
+; ZIP: # %bb.0: # %entry
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vle16.v v8, (a1)
+; ZIP-NEXT: vle16.v v9, (a0)
+; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZIP-NEXT: vslideup.vi v9, v8, 2
+; ZIP-NEXT: vse16.v v9, (a2)
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_bfloat_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
+entry:
+ %0 = load <4 x bfloat>, ptr %in0, align 2
+ %1 = load <4 x bfloat>, ptr %in1, align 2
+ %shuffle.i5 = shufflevector <4 x bfloat> %0, <4 x bfloat> %1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ store <4 x bfloat> %shuffle.i5, ptr %out, align 2
+ ret void
+}
+
define void @vnsrl_0_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; V-LABEL: vnsrl_0_i32_two_source:
; V: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
index d284047bde483..5542a9a1dc98f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV64
define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: zipeven_v4i32:
@@ -112,6 +112,34 @@ entry:
ret <4 x half> %c
}
+define <4 x bfloat> @zipeven_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
+;
+;
+; CHECK-LABEL: zipeven_v4bf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
+; CHECK-NEXT: ret
+;
+; ZIP-LABEL: zipeven_v4bf16:
+; ZIP: # %bb.0: # %entry
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
+; ZIP-NEXT: vmv1r.v v8, v10
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4bf16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vpaire.vv v10, v8, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
+entry:
+ %c = shufflevector <4 x bfloat> %a, <4 x bfloat> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ ret <4 x bfloat> %c
+}
+
define <4 x float> @zipeven_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: zipeven_v4f32:
; CHECK: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index fefeed7f34b1a..6a854309f6265 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV32
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV64
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV64
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -469,6 +469,18 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec
ret {<2 x half>, <2 x half>} %retval
}
+define {<2 x bfloat>, <2 x bfloat>} @vector_deinterleave_v2bf16_v4bf16(<4 x bfloat> %vec) {
+; CHECK-LABEL: vector_deinterleave_v2bf16_v4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vnsrl.wi v9, v8, 16
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+%retval = call {<2 x bfloat>, <2 x bfloat>} @llvm.vector.deinterleave2.v4bf16(<4 x bfloat> %vec)
+ret {<2 x bfloat>, <2 x bfloat>} %retval
+}
+
define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
; CHECK: # %bb.0:
@@ -481,6 +493,18 @@ define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec
ret {<4 x half>, <4 x half>} %retval
}
+define {<4 x bfloat>, <4 x bfloat>} @vector_deinterleave_v4bf16_v8bf16(<8 x bfloat> %vec) {
+; CHECK-LABEL: vector_deinterleave_v4bf16_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vnsrl.wi v9, v8, 16
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+%retval = call {<4 x bfloat>, <4 x bfloat>} @llvm.vector.deinterleave2.v8bf16(<8 x bfloat> %vec)
+ret {<4 x bfloat>, <4 x bfloat>} %retval
+}
+
define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK: # %bb.0:
@@ -506,6 +530,19 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %v
ret {<8 x half>, <8 x half>} %retval
}
+define {<8 x bfloat>, <8 x bfloat>} @vector_deinterleave_v8bf16_v16bf16(<16 x bfloat> %vec) {
+; CHECK-LABEL: vector_deinterleave_v8bf16_v16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vnsrl.wi v11, v8, 16
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vmv.v.v v9, v11
+; CHECK-NEXT: ret
+%retval = call {<8 x bfloat>, <8 x bfloat>} @llvm.vector.deinterleave2.v16bf16(<16 x bfloat> %vec)
+ret {<8 x bfloat>, <8 x bfloat>} %retval
+}
+
define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
; CHECK: # %bb.0:
@@ -733,6 +770,45 @@ define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @vector_dein
ret {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} %res
}
+define {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} @vector_deinterleave5_v10bf16_v2bf16(<10 x bfloat> %v) {
+; CHECK-LABEL: vector_deinterleave5_v10bf16_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v8, 6
+; CHECK-NEXT: vslidedown.vi v13, v8, 4
+; CHECK-NEXT: vslidedown.vi v14, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 8
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v13, v12, a0
+; CHECK-NEXT: vslideup.vx v8, v14, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v13, a1
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vmv1r.v v9, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vlseg5e16.v v8, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %res = call {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} @llvm.vector.deinterleave5.v10bf16(<10 x bfloat> %v)
+ ret {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} %res
+}
+
define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @vector_deinterleave6_v12f16_v2f16(<12 x half> %v) {
; CHECK-LABEL: vector_deinterleave6_v12f16_v2f16:
; CHECK: # %bb.0:
@@ -774,6 +850,47 @@ define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>}
ret {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} %res
}
+define {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} @vector_deinterleave6_v12bf16_v2bf16(<12 x bfloat> %v) {
+; CHECK-LABEL: vector_deinterleave6_v12bf16_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v14, v8, 6
+; CHECK-NEXT: vslidedown.vi v15, v8, 4
+; CHECK-NEXT: vslidedown.vi v16, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 10
+; CHECK-NEXT: vslidedown.vi v12, v8, 8
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v15, v14, a0
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: vslideup.vx v12, v10, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v15, a1
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vs2r.v v8, (a0)
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vlseg6e16.v v8, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %res = call {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} @llvm.vector.deinterleave6.v12bf16(<12 x bfloat> %v)
+ ret {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} %res
+}
+
define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @vector_deinterleave7_v7f16_v1f16(<7 x half> %v) {
; CHECK-LABEL: vector_deinterleave7_v7f16_v1f16:
; CHECK: # %bb.0:
@@ -818,6 +935,50 @@ define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>,
ret {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} %res
}
+define {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} @vector_deinterleave7_v7bf16_v1bf16(<7 x bfloat> %v) {
+; CHECK-LABEL: vector_deinterleave7_v7bf16_v1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v9, v8, 3
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v13, v8, 5
+; CHECK-NEXT: vslidedown.vi v14, v8, 6
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v9, a0
+; CHECK-NEXT: vslideup.vx v10, v12, a0
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v11, a1
+; CHECK-NEXT: vslidedown.vi v11, v8, 4
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v13, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v14, a1
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs2r.v v10, (a0)
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vlseg7e16.v v8, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %res = call {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} @llvm.vector.deinterleave7.v7bf16(<7 x bfloat> %v)
+ ret {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} %res
+}
+
define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @vector_deinterleave8_v8f16_v1f16(<8 x half> %v) {
; CHECK-LABEL: vector_deinterleave8_v8f16_v1f16:
; CHECK: # %bb.0:
@@ -862,6 +1023,51 @@ define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>,
%res = call {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @llvm.vector.deinterleave8.v8f16(<8 x half> %v)
ret {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} %res
}
+
+define {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} @vector_deinterleave8_v8bf16_v1bf16(<8 x bfloat> %v) {
+; CHECK-LABEL: vector_deinterleave8_v8bf16_v1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 7
+; CHECK-NEXT: vslidedown.vi v11, v8, 6
+; CHECK-NEXT: vslidedown.vi v12, v8, 5
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vslidedown.vi v9, v8, 4
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v10, a0
+; CHECK-NEXT: vslideup.vx v9, v12, a0
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v11, a1
+; CHECK-NEXT: vslidedown.vi v10, v8, 3
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v10, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v11, a1
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs2r.v v8, (a0)
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vlseg8e16.v v8, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %res = call {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} @llvm.vector.deinterleave8.v8bf16(<8 x bfloat> %v)
+ ret {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>} %res
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index cd47128c776c1..e20ffea90a868 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
; Integers
@@ -1094,6 +1094,45 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
ret <4 x half> %res
}
+define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
+;
+;
+;
+; CHECK-LABEL: vector_interleave_v4bf16_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave_v4bf16_v2bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave_v4bf16_v2bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
+; ZIP-NEXT: vmv1r.v v8, v10
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vwsll.vi v10, v9, 16
+; ZVZIP-NEXT: vwaddu.wv v10, v10, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
+ %res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
+ ret <4 x bfloat> %res
+}
+
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
@@ -1130,6 +1169,45 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
ret <8 x half> %res
}
+define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
+;
+;
+;
+; CHECK-LABEL: vector_interleave_v8bf16_v4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave_v8bf16_v4bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave_v8bf16_v4bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
+; ZIP-NEXT: vmv.v.v v8, v10
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwsll.vi v10, v9, 16
+; ZVZIP-NEXT: vwaddu.wv v10, v10, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
+ %res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
+ ret <8 x bfloat> %res
+}
+
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
@@ -1208,6 +1286,49 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
}
+define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
+;
+;
+;
+; CHECK-LABEL: vector_interleave_v16bf16_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave_v16bf16_v8bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave_v16bf16_v8bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZIP-NEXT: vmv1r.v v12, v9
+; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
+; ZIP-NEXT: vmv.v.v v8, v10
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwsll.vi v8, v10, 16
+; ZVZIP-NEXT: vwaddu.wv v8, v8, v11
+; ZVZIP-NEXT: ret
+ %res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
+ ret <16 x bfloat> %res
+}
+
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
@@ -1671,8 +1792,11 @@ define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b
ret <10 x half> %res
}
-define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f) nounwind {
-; CHECK-LABEL: vector_interleave6_v12f16_v2f16:
+define <10 x bfloat> @vector_interleave5_v10bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e) nounwind {
+;
+;
+;
+; CHECK-LABEL: vector_interleave5_v10bf16_v2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a0, vlenb
@@ -1684,20 +1808,17 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vsseg6e16.v v8, (a0)
+; CHECK-NEXT: vsseg5e16.v v8, (a0)
+; CHECK-NEXT: add a4, a3, a1
; CHECK-NEXT: vle16.v v9, (a2)
-; CHECK-NEXT: add a2, a3, a1
-; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v13, (a1)
+; CHECK-NEXT: add a1, a4, a1
+; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v12, v11, 2
; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: vslideup.vi v10, v13, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
@@ -1708,7 +1829,7 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; ZVBB-LABEL: vector_interleave6_v12f16_v2f16:
+; ZVBB-LABEL: vector_interleave5_v10bf16_v2bf16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: csrr a0, vlenb
@@ -1720,20 +1841,17 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vsseg6e16.v v8, (a0)
+; ZVBB-NEXT: vsseg5e16.v v8, (a0)
+; ZVBB-NEXT: add a4, a3, a1
; ZVBB-NEXT: vle16.v v9, (a2)
-; ZVBB-NEXT: add a2, a3, a1
-; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: vle16.v v12, (a3)
-; ZVBB-NEXT: add a1, a2, a1
-; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: vle16.v v13, (a1)
+; ZVBB-NEXT: add a1, a4, a1
+; ZVBB-NEXT: vle16.v v10, (a1)
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v12, v11, 2
; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: vslideup.vi v10, v13, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 4
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
@@ -1744,7 +1862,7 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave6_v12f16_v2f16:
+; ZIP-LABEL: vector_interleave5_v10bf16_v2bf16:
; ZIP: # %bb.0:
; ZIP-NEXT: addi sp, sp, -16
; ZIP-NEXT: csrr a0, vlenb
@@ -1756,20 +1874,17 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZIP-NEXT: add a2, a0, a1
; ZIP-NEXT: add a3, a2, a1
; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZIP-NEXT: vsseg5e16.v v8, (a0)
+; ZIP-NEXT: add a4, a3, a1
; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: add a2, a2, a1
+; ZIP-NEXT: vle16.v v11, (a4)
; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v10, (a2)
; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
+; ZIP-NEXT: add a1, a4, a1
+; ZIP-NEXT: vle16.v v10, (a1)
; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZIP-NEXT: vslideup.vi v12, v11, 2
; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vslideup.vi v10, v13, 2
; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZIP-NEXT: vslideup.vi v8, v12, 4
; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
@@ -1780,7 +1895,7 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
;
-; ZVZIP-LABEL: vector_interleave6_v12f16_v2f16:
+; ZVZIP-LABEL: vector_interleave5_v10bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
; ZVZIP-NEXT: csrr a0, vlenb
@@ -1792,20 +1907,17 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: add a2, a0, a1
; ZVZIP-NEXT: add a3, a2, a1
; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-NEXT: add a4, a3, a1
; ZVZIP-NEXT: vle16.v v9, (a2)
-; ZVZIP-NEXT: add a2, a3, a1
-; ZVZIP-NEXT: vle16.v v11, (a2)
-; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vle16.v v11, (a4)
; ZVZIP-NEXT: vle16.v v12, (a3)
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vle16.v v10, (a2)
; ZVZIP-NEXT: vle16.v v8, (a0)
-; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: add a1, a4, a1
+; ZVZIP-NEXT: vle16.v v10, (a1)
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vslideup.vi v12, v11, 2
; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: vslideup.vi v10, v13, 2
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
@@ -1815,12 +1927,12 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
- %res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)
- ret <12 x half> %res
+ %res = call <10 x bfloat> @llvm.vector.interleave5.v10bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e)
+ ret <10 x bfloat> %res
}
-define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g) nounwind {
-; CHECK-LABEL: vector_interleave7_v7f16_v1f16:
+define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f) nounwind {
+; CHECK-LABEL: vector_interleave6_v12f16_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a0, vlenb
@@ -1831,36 +1943,32 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vsseg7e16.v v8, (a0)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: add a4, a4, a1
-; CHECK-NEXT: vle16.v v10, (a2)
-; CHECK-NEXT: add a2, a4, a1
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsseg6e16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: add a2, a3, a1
; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: vle16.v v12, (a4)
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v13, (a1)
-; CHECK-NEXT: vle16.v v14, (a3)
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v12, v11, 1
-; CHECK-NEXT: vslideup.vi v8, v10, 1
-; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v12, v13, 2
-; CHECK-NEXT: vslideup.vi v8, v14, 2
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vslideup.vi v12, v11, 2
+; CHECK-NEXT: vslideup.vi v8, v9, 2
+; CHECK-NEXT: vslideup.vi v10, v13, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; ZVBB-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVBB-LABEL: vector_interleave6_v12f16_v2f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: csrr a0, vlenb
@@ -1871,36 +1979,32 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vsseg7e16.v v8, (a0)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: add a4, a4, a1
-; ZVBB-NEXT: vle16.v v10, (a2)
-; ZVBB-NEXT: add a2, a4, a1
-; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vsseg6e16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: add a2, a3, a1
; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: vle16.v v12, (a4)
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vle16.v v13, (a1)
-; ZVBB-NEXT: vle16.v v14, (a3)
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v12, v11, 1
-; ZVBB-NEXT: vslideup.vi v8, v10, 1
-; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v12, v13, 2
-; ZVBB-NEXT: vslideup.vi v8, v14, 2
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v9, 3
+; ZVBB-NEXT: vslideup.vi v12, v11, 2
+; ZVBB-NEXT: vslideup.vi v8, v9, 2
+; ZVBB-NEXT: vslideup.vi v10, v13, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 4
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave7_v7f16_v1f16:
+; ZIP-LABEL: vector_interleave6_v12f16_v2f16:
; ZIP: # %bb.0:
; ZIP-NEXT: addi sp, sp, -16
; ZIP-NEXT: csrr a0, vlenb
@@ -1911,28 +2015,502 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZIP-NEXT: srli a1, a1, 2
; ZIP-NEXT: add a2, a0, a1
; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg7e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a4)
-; ZIP-NEXT: add a4, a4, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: add a2, a4, a1
-; ZIP-NEXT: add a1, a2, a1
+; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZIP-NEXT: vle16.v v9, (a2)
+; ZIP-NEXT: add a2, a3, a1
; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v12, (a4)
+; ZIP-NEXT: add a2, a2, a1
+; ZIP-NEXT: vle16.v v12, (a3)
+; ZIP-NEXT: add a1, a2, a1
+; ZIP-NEXT: vle16.v v10, (a2)
; ZIP-NEXT: vle16.v v8, (a0)
; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vle16.v v14, (a3)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 1
-; ZIP-NEXT: vslideup.vi v8, v10, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v13, 2
-; ZIP-NEXT: vslideup.vi v8, v14, 2
; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: vslideup.vi v12, v11, 2
+; ZIP-NEXT: vslideup.vi v8, v9, 2
+; ZIP-NEXT: vslideup.vi v10, v13, 2
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v12, 4
+; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v10, 8
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: add sp, sp, a0
+; ZIP-NEXT: addi sp, sp, 16
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave6_v12f16_v2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: add a2, a3, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
+ %res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)
+ ret <12 x half> %res
+}
+
+define <12 x bfloat> @vector_interleave6_v12bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e, <2 x bfloat> %f) nounwind {
+;
+;
+;
+; CHECK-LABEL: vector_interleave6_v12bf16_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsseg6e16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: add a2, a3, a1
+; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v13, (a1)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v11, 2
+; CHECK-NEXT: vslideup.vi v8, v9, 2
+; CHECK-NEXT: vslideup.vi v10, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave6_v12bf16_v2bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: addi sp, sp, -16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: sub sp, sp, a0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vsseg6e16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: add a2, a3, a1
+; ZVBB-NEXT: vle16.v v11, (a2)
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v13, (a1)
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v12, v11, 2
+; ZVBB-NEXT: vslideup.vi v8, v9, 2
+; ZVBB-NEXT: vslideup.vi v10, v13, 2
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v12, 4
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: add sp, sp, a0
+; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave6_v12bf16_v2bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: addi sp, sp, -16
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: sub sp, sp, a0
+; ZIP-NEXT: addi a0, sp, 16
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: srli a1, a1, 2
+; ZIP-NEXT: add a2, a0, a1
+; ZIP-NEXT: add a3, a2, a1
+; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZIP-NEXT: vle16.v v9, (a2)
+; ZIP-NEXT: add a2, a3, a1
+; ZIP-NEXT: vle16.v v11, (a2)
+; ZIP-NEXT: add a2, a2, a1
+; ZIP-NEXT: vle16.v v12, (a3)
+; ZIP-NEXT: add a1, a2, a1
+; ZIP-NEXT: vle16.v v10, (a2)
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vle16.v v13, (a1)
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: vslideup.vi v12, v11, 2
+; ZIP-NEXT: vslideup.vi v8, v9, 2
+; ZIP-NEXT: vslideup.vi v10, v13, 2
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v12, 4
+; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v10, 8
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: add sp, sp, a0
+; ZIP-NEXT: addi sp, sp, 16
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave6_v12bf16_v2bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: add a2, a3, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
+ %res = call <12 x bfloat> @llvm.vector.interleave6.v12bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e, <2 x bfloat> %f)
+ ret <12 x bfloat> %res
+}
+
+define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g) nounwind {
+; CHECK-LABEL: vector_interleave7_v7f16_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsseg7e16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a4)
+; CHECK-NEXT: add a4, a4, a1
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: add a2, a4, a1
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: vle16.v v12, (a4)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v13, (a1)
+; CHECK-NEXT: vle16.v v14, (a3)
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v12, v11, 1
+; CHECK-NEXT: vslideup.vi v8, v10, 1
+; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v12, v13, 2
+; CHECK-NEXT: vslideup.vi v8, v14, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: addi sp, sp, -16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: sub sp, sp, a0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vsseg7e16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v9, (a4)
+; ZVBB-NEXT: add a4, a4, a1
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: add a2, a4, a1
+; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: vle16.v v11, (a2)
+; ZVBB-NEXT: vle16.v v12, (a4)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v13, (a1)
+; ZVBB-NEXT: vle16.v v14, (a3)
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v12, v11, 1
+; ZVBB-NEXT: vslideup.vi v8, v10, 1
+; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v12, v13, 2
+; ZVBB-NEXT: vslideup.vi v8, v14, 2
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v9, 3
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v12, 4
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: add sp, sp, a0
+; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave7_v7f16_v1f16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: addi sp, sp, -16
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: sub sp, sp, a0
+; ZIP-NEXT: addi a0, sp, 16
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: srli a1, a1, 2
+; ZIP-NEXT: add a2, a0, a1
+; ZIP-NEXT: add a3, a2, a1
+; ZIP-NEXT: add a4, a3, a1
+; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZIP-NEXT: vsseg7e16.v v8, (a0)
+; ZIP-NEXT: vle16.v v9, (a4)
+; ZIP-NEXT: add a4, a4, a1
+; ZIP-NEXT: vle16.v v10, (a2)
+; ZIP-NEXT: add a2, a4, a1
+; ZIP-NEXT: add a1, a2, a1
+; ZIP-NEXT: vle16.v v11, (a2)
+; ZIP-NEXT: vle16.v v12, (a4)
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vle16.v v13, (a1)
+; ZIP-NEXT: vle16.v v14, (a3)
+; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v12, v11, 1
+; ZIP-NEXT: vslideup.vi v8, v10, 1
+; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v12, v13, 2
+; ZIP-NEXT: vslideup.vi v8, v14, 2
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v9, 3
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v12, 4
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: add sp, sp, a0
+; ZIP-NEXT: addi sp, sp, 16
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg7e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a4)
+; ZVZIP-NEXT: add a4, a4, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: add a2, a4, a1
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: vle16.v v12, (a4)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vle16.v v14, (a3)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v13, 2
+; ZVZIP-NEXT: vslideup.vi v8, v14, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
+ %res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
+ ret <7 x half> %res
+}
+
+define <7 x bfloat> @vector_interleave7_v7bf16_v1bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g) nounwind {
+;
+;
+;
+; CHECK-LABEL: vector_interleave7_v7bf16_v1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsseg7e16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a4)
+; CHECK-NEXT: add a4, a4, a1
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: add a2, a4, a1
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: vle16.v v12, (a4)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v13, (a1)
+; CHECK-NEXT: vle16.v v14, (a3)
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v12, v11, 1
+; CHECK-NEXT: vslideup.vi v8, v10, 1
+; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v12, v13, 2
+; CHECK-NEXT: vslideup.vi v8, v14, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave7_v7bf16_v1bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: addi sp, sp, -16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: sub sp, sp, a0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vsseg7e16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v9, (a4)
+; ZVBB-NEXT: add a4, a4, a1
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: add a2, a4, a1
+; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: vle16.v v11, (a2)
+; ZVBB-NEXT: vle16.v v12, (a4)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v13, (a1)
+; ZVBB-NEXT: vle16.v v14, (a3)
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v12, v11, 1
+; ZVBB-NEXT: vslideup.vi v8, v10, 1
+; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v12, v13, 2
+; ZVBB-NEXT: vslideup.vi v8, v14, 2
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v9, 3
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v12, 4
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: add sp, sp, a0
+; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave7_v7bf16_v1bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: addi sp, sp, -16
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: sub sp, sp, a0
+; ZIP-NEXT: addi a0, sp, 16
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: srli a1, a1, 2
+; ZIP-NEXT: add a2, a0, a1
+; ZIP-NEXT: add a3, a2, a1
+; ZIP-NEXT: add a4, a3, a1
+; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZIP-NEXT: vsseg7e16.v v8, (a0)
+; ZIP-NEXT: vle16.v v9, (a4)
+; ZIP-NEXT: add a4, a4, a1
+; ZIP-NEXT: vle16.v v10, (a2)
+; ZIP-NEXT: add a2, a4, a1
+; ZIP-NEXT: add a1, a2, a1
+; ZIP-NEXT: vle16.v v11, (a2)
+; ZIP-NEXT: vle16.v v12, (a4)
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vle16.v v13, (a1)
+; ZIP-NEXT: vle16.v v14, (a3)
+; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v12, v11, 1
+; ZIP-NEXT: vslideup.vi v8, v10, 1
+; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v12, v13, 2
+; ZIP-NEXT: vslideup.vi v8, v14, 2
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v9, 3
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZIP-NEXT: vslideup.vi v8, v12, 4
; ZIP-NEXT: csrr a0, vlenb
; ZIP-NEXT: slli a0, a0, 1
@@ -1940,7 +2518,7 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
;
-; ZVZIP-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVZIP-LABEL: vector_interleave7_v7bf16_v1bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
; ZVZIP-NEXT: csrr a0, vlenb
@@ -1979,8 +2557,8 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
- %res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
- ret <7 x half> %res
+ %res = call <7 x bfloat> @llvm.vector.interleave7.v7bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g)
+ ret <7 x bfloat> %res
}
define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h) nounwind {
@@ -2159,6 +2737,185 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
ret <8 x half> %res
}
+define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h) nounwind {
+;
+;
+;
+; CHECK-LABEL: vector_interleave8_v8bf16_v1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: add a5, a4, a1
+; CHECK-NEXT: add a6, a5, a1
+; CHECK-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsseg8e16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a6)
+; CHECK-NEXT: add a6, a6, a1
+; CHECK-NEXT: vle16.v v10, (a5)
+; CHECK-NEXT: vle16.v v11, (a6)
+; CHECK-NEXT: add a1, a6, a1
+; CHECK-NEXT: vle16.v v12, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v13, (a3)
+; CHECK-NEXT: vle16.v v14, (a4)
+; CHECK-NEXT: vle16.v v15, (a1)
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v9, 1
+; CHECK-NEXT: vslideup.vi v8, v12, 1
+; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v11, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v15, 3
+; CHECK-NEXT: vslideup.vi v8, v14, 3
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; ZVBB-LABEL: vector_interleave8_v8bf16_v1bf16:
+; ZVBB: # %bb.0:
+; ZVBB-NEXT: addi sp, sp, -16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: sub sp, sp, a0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: add a5, a4, a1
+; ZVBB-NEXT: add a6, a5, a1
+; ZVBB-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vsseg8e16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v9, (a6)
+; ZVBB-NEXT: add a6, a6, a1
+; ZVBB-NEXT: vle16.v v10, (a5)
+; ZVBB-NEXT: vle16.v v11, (a6)
+; ZVBB-NEXT: add a1, a6, a1
+; ZVBB-NEXT: vle16.v v12, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: vle16.v v13, (a3)
+; ZVBB-NEXT: vle16.v v14, (a4)
+; ZVBB-NEXT: vle16.v v15, (a1)
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v10, v9, 1
+; ZVBB-NEXT: vslideup.vi v8, v12, 1
+; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVBB-NEXT: vslideup.vi v10, v11, 2
+; ZVBB-NEXT: vslideup.vi v8, v13, 2
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v10, v15, 3
+; ZVBB-NEXT: vslideup.vi v8, v14, 3
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 1
+; ZVBB-NEXT: add sp, sp, a0
+; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: ret
+;
+; ZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
+; ZIP: # %bb.0:
+; ZIP-NEXT: addi sp, sp, -16
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: sub sp, sp, a0
+; ZIP-NEXT: addi a0, sp, 16
+; ZIP-NEXT: csrr a1, vlenb
+; ZIP-NEXT: srli a1, a1, 2
+; ZIP-NEXT: add a2, a0, a1
+; ZIP-NEXT: add a3, a2, a1
+; ZIP-NEXT: add a4, a3, a1
+; ZIP-NEXT: add a5, a4, a1
+; ZIP-NEXT: add a6, a5, a1
+; ZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
+; ZIP-NEXT: vsseg8e16.v v8, (a0)
+; ZIP-NEXT: vle16.v v9, (a6)
+; ZIP-NEXT: add a6, a6, a1
+; ZIP-NEXT: vle16.v v10, (a5)
+; ZIP-NEXT: vle16.v v11, (a6)
+; ZIP-NEXT: add a1, a6, a1
+; ZIP-NEXT: vle16.v v12, (a2)
+; ZIP-NEXT: vle16.v v8, (a0)
+; ZIP-NEXT: vle16.v v13, (a3)
+; ZIP-NEXT: vle16.v v14, (a4)
+; ZIP-NEXT: vle16.v v15, (a1)
+; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v10, v9, 1
+; ZIP-NEXT: vslideup.vi v8, v12, 1
+; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZIP-NEXT: vslideup.vi v10, v11, 2
+; ZIP-NEXT: vslideup.vi v8, v13, 2
+; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZIP-NEXT: vslideup.vi v10, v15, 3
+; ZIP-NEXT: vslideup.vi v8, v14, 3
+; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZIP-NEXT: vslideup.vi v8, v10, 4
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: slli a0, a0, 1
+; ZIP-NEXT: add sp, sp, a0
+; ZIP-NEXT: addi sp, sp, 16
+; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a4, a1
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a6)
+; ZVZIP-NEXT: add a6, a6, a1
+; ZVZIP-NEXT: vle16.v v10, (a5)
+; ZVZIP-NEXT: vle16.v v11, (a6)
+; ZVZIP-NEXT: add a1, a6, a1
+; ZVZIP-NEXT: vle16.v v12, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a3)
+; ZVZIP-NEXT: vle16.v v14, (a4)
+; ZVZIP-NEXT: vle16.v v15, (a1)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v15, 3
+; ZVZIP-NEXT: vslideup.vi v8, v14, 3
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
+ %res = call <8 x bfloat> @llvm.vector.interleave8.v8bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h)
+ ret <8 x bfloat> %res
+}
+
define <8 x i16> @interleave4_const_splat_v8i16(<2 x i16> %a) {
; CHECK-LABEL: interleave4_const_splat_v8i16:
; CHECK: # %bb.0:
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