[llvm] [DAG] computeKnownFPClass - add ISD::FCOPYSIGN handling (PR #193672)

[Xinlong Chen via llvm-commits]

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@@ -256,3 +256,61 @@ define <4 x i1> @fneg_vec_unknown_sign(<4 x i32> %vecbits) nounwind {
   %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 60) ; any negative
   ret <4 x i1> %res
 }
+
+define i1 @copysign_fabs_sign_not_negative(float %x, float %y) nounwind {
+; CHECK-LABEL: copysign_fabs_sign_not_negative:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %s = call float @llvm.fabs.f32(float %y)
+  %r = call float @llvm.copysign.f32(float %x, float %s)
+  %res = call i1 @llvm.is.fpclass.f32(float %r, i32 60) ; 0x3C = any negative
+  ret i1 %res
+}
+
+define i1 @copysign_fneg_fabs_sign_not_positive(float %x, float %y) nounwind {
+; CHECK-LABEL: copysign_fneg_fabs_sign_not_positive:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %a = call float @llvm.fabs.f32(float %y)
+  %s = fneg float %a
+  %r = call float @llvm.copysign.f32(float %x, float %s)
+  %res = call i1 @llvm.is.fpclass.f32(float %r, i32 960) ; 0x3C0 = any positive
+  ret i1 %res
+}
+
+define i1 @copysign_nan_mag_is_finite_or_inf(float %y) nounwind {
+; CHECK-LABEL: copysign_nan_mag_is_finite_or_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
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Xinlong-Chen wrote:

Following the discussion at https://github.com/llvm/llvm-project/pull/190307#discussion_r3057532198, it appears we are missing a constant folding in `visitIS_FPCLASS`.
I plan to submit a separate PR addressing it, and then introduce the fold-to-true case afterwards. Is it ok?

https://github.com/llvm/llvm-project/pull/193672