[llvm] [LV][RISCV] Add explicit LMUL controls via computeFeasibleMaxVF (PR #193091)

[Florian Hahn via llvm-commits]

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@@ -1355,6 +1355,9 @@ class TargetTransformInfo {
   /// \return The width of the smallest vector register type.
   LLVM_ABI unsigned getMinVectorRegisterBitWidth() const;
 
+  /// \return The maximum VF configured for target.
+  std::optional<ElementCount> getMaxScalableVF(unsigned MaxWidthInBits) const;
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fhahn wrote:

I am not sure it is clear what maximum VF means here. Maximum legal VF, i.e. maxium VF so a vector with MaxWidthInBits fits into a single vector register? Would be good to clarify the documentation and also document argument

https://github.com/llvm/llvm-project/pull/193091