[llvm] [IR] Composable and Extensible Memory Cache Control Hints (PR #181612)

[Antonio Frighetto via llvm-commits]

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@@ -485,6 +485,49 @@ join:
   ret void
 }
 
+; Both loads have !mem.cache_hint, preserved after GVN deduplication.
+define i64 @test_mem_cache_hint_both(ptr %p) {
+; CHECK-LABEL: define i64 @test_mem_cache_hint_both
+; CHECK-SAME: (ptr [[P:%.*]]) {
+; CHECK-NEXT:    [[A:%.*]] = load i64, ptr [[P]], align 4, !mem.cache_hint [[META11:![0-9]+]]
+; CHECK-NEXT:    [[C:%.*]] = add i64 [[A]], [[A]]
+; CHECK-NEXT:    ret i64 [[C]]
+;
+  %a = load i64, ptr %p, !mem.cache_hint !12
+  %b = load i64, ptr %p, !mem.cache_hint !12
+  %c = add i64 %a, %b
+  ret i64 %c
+}
+
+; Only one load has !mem.cache_hint, dropped after GVN deduplication.
+define i64 @test_mem_cache_hint_one(ptr %p) {
+; CHECK-LABEL: define i64 @test_mem_cache_hint_one
+; CHECK-SAME: (ptr [[P:%.*]]) {
+; CHECK-NEXT:    [[A:%.*]] = load i64, ptr [[P]], align 4
+; CHECK-NEXT:    [[C:%.*]] = add i64 [[A]], [[A]]
+; CHECK-NEXT:    ret i64 [[C]]
+;
+  %a = load i64, ptr %p
+  %b = load i64, ptr %p, !mem.cache_hint !12
+  %c = add i64 %a, %b
+  ret i64 %c
+}
+
+; Both loads have !mem.cache_hint but with different payloads.
+; TODO: delegate to TTI to let targets decide how to merge differing payloads.
+define i64 @test_mem_cache_hint_diff(ptr %p) {
+; CHECK-LABEL: define i64 @test_mem_cache_hint_diff
+; CHECK-SAME: (ptr [[P:%.*]]) {
+; CHECK-NEXT:    [[A:%.*]] = load i64, ptr [[P]], align 4, !mem.cache_hint [[META13:![0-9]+]]
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antoniofrighetto wrote:

I'm not completely clear why we deliberately pick the cache hint of the GVN'd instruction (or whatever calls combineMetadata()) as a general / conservative option at this stage. As you suggested in the TODO, TTI should be delegated to retain the last operation's cache hint, and implement such a policy (or other eviction hints policies); but until then, shouldn't the most conservative option to drop on mismatch?

https://github.com/llvm/llvm-project/pull/181612