[llvm] [CodeGen] Disallow mixing of ignorable uses in MachineCSE (PR #193522)
Igor Wodiany via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 23 01:28:43 PDT 2026
https://github.com/IgWod updated https://github.com/llvm/llvm-project/pull/193522
>From d4cbb1f053a91502ad273eca13e28d04ff7d49a3 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Wed, 22 Apr 2026 15:13:03 +0100
Subject: [PATCH 1/2] [CodeGen] Disallow mixing of ignorable uses in MachineCSE
In the case of the AMDGPU target this could cause an issue when a V_CMP_*
instruction was replaced despite being no guarantee that the execution mask
for both instructions is the same.
Looking at the example below. The second V_CMP_GT cannot be replaced
with %3, despite both having the same operands as there is no guarantee
the execution mask is the same at the last loop iteration and after the
loop finishes.
```
bb.1
%3:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
%4:sreg_64 = SI_IF_BREAK killed %3:sreg_64, %2:sreg_64, implicit-def dead $scc
SI_LOOP %4:sreg_64, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.2
bb.2:
SI_END_CF %4:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%5:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
%6:sreg_64 = S_AND_B64 %5:sreg_64, $exec, implicit-def $scc
```
---
llvm/lib/CodeGen/MachineCSE.cpp | 26 ++++++--
.../test/CodeGen/AMDGPU/ignorable-use-cse.mir | 66 +++++++++++++++++++
2 files changed, 85 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 67ecb80bc3ee0..1ebd3c2b46702 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -619,18 +619,32 @@ bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
// Check if it's profitable to perform this CSE.
bool DoCSE = true;
- unsigned NumDefs = MI.getNumDefs();
- for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
+ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ MachineOperand &CSMO = CSMI->getOperand(i);
+
+ if (!MO.isReg())
continue;
+
+ // No need to check a reversed condition since MI with non-ignorable MO
+ // would not be a CSE candidate.
+ if (TII->isIgnorableUse(MO) && !TII->isIgnorableUse(CSMO)) {
+ LLVM_DEBUG(dbgs() << "*** Ignorable and non-ignorable use for the same "
+ "operand, avoid CSE!\n");
+ DoCSE = false;
+ break;
+ }
+
+ if (!MO.isDef())
+ continue;
+
Register OldReg = MO.getReg();
- Register NewReg = CSMI->getOperand(i).getReg();
+ Register NewReg = CSMO.getReg();
// Go through implicit defs of CSMI and MI, if a def is not dead at MI,
// we should make sure it is not dead at CSMI.
- if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
+ if (MO.isImplicit() && !MO.isDead() && CSMO.isDead())
ImplicitDefsToUpdate.push_back(i);
// Keep track of implicit defs of CSMI and MI, to clear possibly
@@ -639,7 +653,6 @@ bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
ImplicitDefs.push_back(OldReg);
if (OldReg == NewReg) {
- --NumDefs;
continue;
}
@@ -663,7 +676,6 @@ bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
}
CSEPairs.emplace_back(OldReg, NewReg);
- --NumDefs;
}
// Actually perform the elimination.
diff --git a/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir b/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
new file mode 100644
index 0000000000000..5d5176446855f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
@@ -0,0 +1,66 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+wavefrontsize32,+wavefrontsize64 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ignorable_use_cse
+tracksRegLiveness: true
+legalized: true
+regBankSelected: true
+selected: true
+body: |
+ ; CHECK-LABEL: name: ignorable_use_cse
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0, $sgpr0, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK killed [[V_CMP_GT_U32_e64_]], [[COPY2]], implicit-def dead $scc
+ ; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: [[V_CMP_GT_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_GT_U32_e64_1]], $exec, implicit-def $scc
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $vgpr0, $sgpr0, $sgpr2_sgpr3
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = COPY $sgpr0
+ %2:sreg_64 = COPY $sgpr2_sgpr3
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ %3:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
+ %4:sreg_64 = SI_IF_BREAK killed %3:sreg_64, %2:sreg_64, implicit-def dead $scc
+ SI_LOOP %4:sreg_64, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ SI_END_CF %4:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ %5:sreg_64 = V_CMP_GT_U32_e64 %0:vgpr_32, %1:sreg_32, implicit $exec
+ %6:sreg_64 = S_AND_B64 %5:sreg_64, $exec, implicit-def $scc
+ S_BRANCH %bb.3
+
+ bb.3:
+ S_ENDPGM 0
+...
>From 412547af2a0b6f209887cf1d6af0f8642205d2f0 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Thu, 23 Apr 2026 09:27:42 +0100
Subject: [PATCH 2/2] Fix test wavesize
---
llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir b/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
index 5d5176446855f..d5ec6d1e6dd3b 100644
--- a/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
+++ b/llvm/test/CodeGen/AMDGPU/ignorable-use-cse.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+wavefrontsize32,+wavefrontsize64 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+wavefrontsize64 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck %s
---
name: ignorable_use_cse
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