[llvm] 5a45fbb - [llvm][RISCV] Split LMUL=8 fixed vector fcmp for zvfhmin and zvfbfmin (#193424)

Thu Apr 23 00:58:42 PDT 2026

Author: Brandon Wu
Date: 2026-04-23T07:58:36Z
New Revision: 5a45fbb35ea32e01de7aec4defc7c3e11c204eaf

URL: https://github.com/llvm/llvm-project/commit/5a45fbb35ea32e01de7aec4defc7c3e11c204eaf
DIFF: https://github.com/llvm/llvm-project/commit/5a45fbb35ea32e01de7aec4defc7c3e11c204eaf.diff

LOG: [llvm][RISCV] Split LMUL=8 fixed vector fcmp for zvfhmin and zvfbfmin (#193424)

Currently we don't handle any of illegal promoted fixed vectors for
zvfhmin and zvfbfmin we expand it and make general legalizer handle it.
However some of operators are split and some are scalarized depends on
operator type, in this case we need to split it manually.

Added: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lmul-max.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fda4ed99477ff..4d5013c709e23 100644

--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1683,9 +1683,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
           MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
           // Don't promote f16 vector operations to f32 if f32 vector type is
           // not legal.
-          // TODO: could split the f16 vector into two vectors and do promotion.
-          if (!isTypeLegal(F32VecVT))
+          // Custom lower maximum LMUL case to split to 2 half LMUL operations.
+          // TODO: Support more operations.
+          if (!isTypeLegal(F32VecVT)) {
+            setOperationAction(ISD::SETCC, VT, Custom);
             continue;
+          }
           setOperationPromotedToType(ZvfhminZvfbfminPromoteOps, VT, F32VecVT);
           setOperationPromotedToType(ZvfhminZvfbfminPromoteVPOps, VT, F32VecVT);
           continue;
@@ -1711,11 +1714,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
               {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
               Custom);
           MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
-          // Don't promote f16 vector operations to f32 if f32 vector type is
+          // Don't promote bf16 vector operations to f32 if f32 vector type is
           // not legal.
-          // TODO: could split the f16 vector into two vectors and do promotion.
-          if (!isTypeLegal(F32VecVT))
+          // Custom lower maximum LMUL case to split to 2 half LMUL operations.
+          // TODO: Support more operations.
+          if (!isTypeLegal(F32VecVT)) {
+            setOperationAction(ISD::SETCC, VT, Custom);
             continue;
+          }
 
           if (Subtarget.hasVInstructionsBF16())
             setOperationPromotedToType(ZvfbfaPromoteOps, VT, F32VecVT);
@@ -7620,15 +7626,22 @@ static unsigned getRISCVVLOp(SDValue Op) {
 }
 
 static bool isPromotedOpNeedingSplit(SDValue Op,
-                                     const RISCVSubtarget &Subtarget) {
-  return (Op.getValueType() == MVT::nxv32f16 &&
-          (Subtarget.hasVInstructionsF16Minimal() &&
-           !Subtarget.hasVInstructionsF16())) ||
-         (Op.getValueType() == MVT::nxv32bf16 &&
-          Subtarget.hasVInstructionsBF16Minimal() &&
-          (!Subtarget.hasVInstructionsBF16() ||
-           (!llvm::is_contained(ZvfbfaOps, Op.getOpcode()) &&
-            !llvm::is_contained(ZvfbfaVPOps, Op.getOpcode()))));
+                                     const RISCVSubtarget &Subtarget,
+                                     const TargetLowering &TLI) {
+  MVT OpVT = Op.getSimpleValueType();
+  if (!OpVT.isVector())
+    return false;
+  MVT EltVT = OpVT.getVectorElementType();
+  if (!(EltVT == MVT::f16 && Subtarget.hasVInstructionsF16Minimal() &&
+        !Subtarget.hasVInstructionsF16()) &&
+      !(EltVT == MVT::bf16 && Subtarget.hasVInstructionsBF16Minimal() &&
+        (!Subtarget.hasVInstructionsBF16() ||
+         (!llvm::is_contained(ZvfbfaOps, Op.getOpcode()) &&
+          !llvm::is_contained(ZvfbfaVPOps, Op.getOpcode())))))
+    return false;
+  // Need to split when the same width f32 vector type isn't legal.
+  return !TLI.isTypeLegal(
+      MVT::getVectorVT(MVT::f32, OpVT.getVectorElementCount()));
 }
 
 static SDValue SplitVectorOp(SDValue Op, SelectionDAG &DAG) {
@@ -8043,7 +8056,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::FMAXIMUM:
   case ISD::FMINIMUM:
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitVectorOp(Op, DAG);
     return lowerFMAXIMUM_FMINIMUM(Op, DAG, Subtarget);
   case ISD::FP_EXTEND:
@@ -8327,7 +8340,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::FRINT:
   case ISD::FROUND:
   case ISD::FROUNDEVEN:
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitVectorOp(Op, DAG);
     return lowerFTRUNC_FCEIL_FFLOOR_FROUND(Op, DAG, Subtarget);
   case ISD::LRINT:
@@ -8384,7 +8397,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VP_REDUCE_FMAX:
   case ISD::VP_REDUCE_FMINIMUM:
   case ISD::VP_REDUCE_FMAXIMUM:
-    if (isPromotedOpNeedingSplit(Op.getOperand(1), Subtarget))
+    if (isPromotedOpNeedingSplit(Op.getOperand(1), Subtarget, *this))
       return SplitVectorReductionOp(Op, DAG);
     return lowerVPREDUCE(Op, DAG);
   case ISD::VP_REDUCE_AND:
@@ -8778,7 +8791,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       return SDValue();
     }
 
-    if (isPromotedOpNeedingSplit(Op.getOperand(0), Subtarget))
+    if (isPromotedOpNeedingSplit(Op.getOperand(0), Subtarget, *this))
       return SplitVectorOp(Op, DAG);
 
     return lowerToScalableOp(Op, DAG);
@@ -8878,7 +8891,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::FMAXNUM:
   case ISD::FMINIMUMNUM:
   case ISD::FMAXIMUMNUM:
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitVectorOp(Op, DAG);
     [[fallthrough]];
   case ISD::AVGFLOORS:
@@ -8941,7 +8954,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::FCOPYSIGN:
     if (Op.getValueType() == MVT::f16 || Op.getValueType() == MVT::bf16)
       return lowerFCOPYSIGN(Op, DAG, Subtarget);
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitVectorOp(Op, DAG);
     return lowerToScalableOp(Op, DAG);
   case ISD::STRICT_FADD:
@@ -8950,7 +8963,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::STRICT_FDIV:
   case ISD::STRICT_FSQRT:
   case ISD::STRICT_FMA:
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitStrictFPVectorOp(Op, DAG);
     return lowerToScalableOp(Op, DAG);
   case ISD::STRICT_FSETCC:
@@ -9007,7 +9020,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return lowerLogicVPOp(Op, DAG);
   case ISD::VP_FNEG:
   case ISD::VP_FMA:
-    if (isPromotedOpNeedingSplit(Op, Subtarget))
+    if (isPromotedOpNeedingSplit(Op, Subtarget, *this))
       return SplitVPOp(Op, DAG);
     [[fallthrough]];
   case ISD::VP_SRA:
@@ -9027,7 +9040,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::VP_FP_ROUND:
     return lowerVectorFPExtendOrRoundLike(Op, DAG);
   case ISD::VP_SETCC:
-    if (isPromotedOpNeedingSplit(Op.getOperand(0), Subtarget))
+    if (isPromotedOpNeedingSplit(Op.getOperand(0), Subtarget, *this))
       return SplitVPOp(Op, DAG);
     if (Op.getOperand(0).getSimpleValueType().getVectorElementType() == MVT::i1)
       return lowerVPSetCCMaskOp(Op, DAG);

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index 2e3022e008d76..d6a1173b1573a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN,ZVFBFMIN
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN,ZVFBFMIN
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN,ZVFBFA
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN,ZVFBFA
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
 
 define void @fcmp_oeq_vv_v8bf16(ptr %x, ptr %y, ptr %z) {
 ; ZVFBFMIN-LABEL: fcmp_oeq_vv_v8bf16:
@@ -860,1035 +860,100 @@ define void @fcmp_ugt_vv_v64f16(ptr %x, ptr %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v8, (a2)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
-; RV32ZVFHMIN-NEXT:    sw ra, 508(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 504(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a3, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v16, (a1)
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV32ZVFHMIN-NEXT:    addi a1, sp, 256
-; RV32ZVFHMIN-NEXT:    vse16.v v16, (a0)
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a1)
-; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 320(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 318(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 316(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 314(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 312(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 310(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 308(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 306(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 176(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 304(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV32ZVFHMIN-NEXT:    sb a1, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 174(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 302(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v8
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 172(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 300(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 170(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 298(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 168(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 296(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 166(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 294(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 164(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 292(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 162(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 290(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    xori a0, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 288(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 354(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v27, v8, 1
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 224(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 352(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 222(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 350(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 220(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 348(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 218(sp)
-; RV32ZVFHMIN-NEXT:    lh t1, 346(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v19
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV32ZVFHMIN-NEXT:    sb t0, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 216(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v20
-; RV32ZVFHMIN-NEXT:    lh t2, 344(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v21
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    xori a1, t2, 1
-; RV32ZVFHMIN-NEXT:    sb a1, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 214(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a0
-; RV32ZVFHMIN-NEXT:    lh t3, 342(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v23
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV32ZVFHMIN-NEXT:    sb a1, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 212(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh a7, 340(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v22
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 210(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    lh a6, 338(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v25
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 208(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh t0, 336(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV32ZVFHMIN-NEXT:    sb t0, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 206(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV32ZVFHMIN-NEXT:    lh t1, 334(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v26
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    xori a7, t1, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 204(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh t1, 332(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v27
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    xori a7, t1, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 202(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 330(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 200(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 328(sp)
-; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 198(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 326(sp)
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    xori t2, t2, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 196(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 324(sp)
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a7, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 194(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 322(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb t2, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a1, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 382(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 380(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 378(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 376(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 374(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v2
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v18
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v0
-; RV32ZVFHMIN-NEXT:    lh a1, 372(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v20
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 242(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    lh a4, 370(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV32ZVFHMIN-NEXT:    sb a1, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 240(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    lh a6, 368(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    sb a4, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 238(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    lh t0, 366(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV32ZVFHMIN-NEXT:    sb t0, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 236(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV32ZVFHMIN-NEXT:    lh t1, 364(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v30
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    xori a5, t1, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 234(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    lh a7, 362(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v26
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    xori a6, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a6, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 232(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    lh a7, 360(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v28
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    xori a5, a7, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 230(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    lh a6, 358(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    xori a5, t2, 1
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    sb a6, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 228(sp)
-; RV32ZVFHMIN-NEXT:    lh t2, 356(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a1, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 79(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a1, t1, 1
-; RV32ZVFHMIN-NEXT:    xori a4, t0, 1
-; RV32ZVFHMIN-NEXT:    xori a5, a7, 1
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb a1, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a2)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
-; RV32ZVFHMIN-NEXT:    lw ra, 508(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 504(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
-; RV64ZVFHMIN-NEXT:    sd ra, 504(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 496(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a3, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v16, (a1)
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV64ZVFHMIN-NEXT:    addi a1, sp, 256
-; RV64ZVFHMIN-NEXT:    vse16.v v16, (a0)
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a1)
-; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 320(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 318(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 316(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 314(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 312(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 310(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 308(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 306(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 176(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 304(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV64ZVFHMIN-NEXT:    sb a1, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 174(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 302(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v8
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 172(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 300(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 170(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 298(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 168(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 296(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 166(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 294(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 164(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 292(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 162(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 290(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    xori a0, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 288(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 354(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v27, v8, 1
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 224(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 352(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 222(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 350(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 220(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 348(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 218(sp)
-; RV64ZVFHMIN-NEXT:    lh t1, 346(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v19
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV64ZVFHMIN-NEXT:    sb t0, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 216(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v20
-; RV64ZVFHMIN-NEXT:    lh t2, 344(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v21
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    xori a1, t2, 1
-; RV64ZVFHMIN-NEXT:    sb a1, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 214(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a0
-; RV64ZVFHMIN-NEXT:    lh t3, 342(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v23
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV64ZVFHMIN-NEXT:    sb a1, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 212(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh a7, 340(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v22
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 210(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    lh a6, 338(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v25
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 208(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh t0, 336(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV64ZVFHMIN-NEXT:    sb t0, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 206(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV64ZVFHMIN-NEXT:    lh t1, 334(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v26
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    xori a7, t1, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 204(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh t1, 332(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v27
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    xori a7, t1, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 202(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 330(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 200(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 328(sp)
-; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 198(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 326(sp)
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    xori t2, t2, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 196(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 324(sp)
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a7, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 194(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 322(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb t2, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a1, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 382(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 380(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 378(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 376(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 374(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v2
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v18
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v0
-; RV64ZVFHMIN-NEXT:    lh a1, 372(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v20
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 242(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    lh a4, 370(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV64ZVFHMIN-NEXT:    sb a1, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 240(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    lh a6, 368(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    sb a4, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 238(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    lh t0, 366(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV64ZVFHMIN-NEXT:    sb t0, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 236(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV64ZVFHMIN-NEXT:    lh t1, 364(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v30
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    xori a5, t1, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 234(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    lh a7, 362(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v26
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    xori a6, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a6, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 232(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    lh a7, 360(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v28
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    xori a5, a7, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 230(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    lh a6, 358(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    xori a1, a1, 1
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    xori a5, t2, 1
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    sb a6, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 228(sp)
-; RV64ZVFHMIN-NEXT:    lh t2, 356(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a1, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 79(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a1, t1, 1
-; RV64ZVFHMIN-NEXT:    xori a4, t0, 1
-; RV64ZVFHMIN-NEXT:    xori a5, a7, 1
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb a1, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a2)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
-; RV64ZVFHMIN-NEXT:    ld ra, 504(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 496(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    addi sp, sp, -16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; ZVFHMIN-NEXT:    csrr a3, vlenb
+; ZVFHMIN-NEXT:    slli a3, a3, 5
+; ZVFHMIN-NEXT:    sub sp, sp, a3
+; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT:    li a3, 64
+; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v16, (a1)
+; ZVFHMIN-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFHMIN-NEXT:    vslidedown.vx v0, v8, a0
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a1, a1, 3
+; ZVFHMIN-NEXT:    mv a4, a1
+; ZVFHMIN-NEXT:    slli a1, a1, 1
+; ZVFHMIN-NEXT:    add a1, a1, a4
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 4
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vmv4r.v v8, v24
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    addi a0, sp, 16
+; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    mv a1, a0
+; ZVFHMIN-NEXT:    slli a0, a0, 1
+; ZVFHMIN-NEXT:    add a0, a0, a1
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v0
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 4
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfle.vv v16, v24, v0
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    mv a1, a0
+; ZVFHMIN-NEXT:    slli a0, a0, 1
+; ZVFHMIN-NEXT:    add a0, a0, a1
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT:    addi a0, sp, 16
+; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vmfle.vv v16, v8, v24
+; ZVFHMIN-NEXT:    vmnot.m v8, v16
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    mv a1, a0
+; ZVFHMIN-NEXT:    slli a0, a0, 1
+; ZVFHMIN-NEXT:    add a0, a0, a1
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT:    vmnot.m v9, v9
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v9, v8, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v9, (a2)
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 5
+; ZVFHMIN-NEXT:    add sp, sp, a0
+; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
+; ZVFHMIN-NEXT:    addi sp, sp, 16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = load <64 x half>, ptr %y
   %c = fcmp ugt <64 x half> %a, %b
@@ -1907,907 +972,59 @@ define void @fcmp_ugt_vv_v64f16_nonans(ptr %x, ptr %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v24, (a2)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16_nonans:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
-; RV32ZVFHMIN-NEXT:    sw ra, 508(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 504(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a3, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v16, (a0)
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a1)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 256
-; RV32ZVFHMIN-NEXT:    addi a1, sp, 128
-; RV32ZVFHMIN-NEXT:    vse16.v v16, (a0)
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a1)
-; RV32ZVFHMIN-NEXT:    lh a0, 320(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 192(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 318(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 190(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 316(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 188(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 314(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 186(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 312(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 184(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 310(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 182(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 308(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 180(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 306(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 178(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 304(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 176(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 302(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 174(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 300(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 172(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 298(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 170(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a1, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 296(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 168(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v8
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 294(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 166(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 292(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 164(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 290(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 162(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    sb a4, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 288(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 160(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a1, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 354(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 226(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 352(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 224(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 350(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 222(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v27, v16, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 348(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 220(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v8, 1
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 346(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 218(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a1, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a0, v13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 344(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 216(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 342(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 214(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 340(sp)
-; RV32ZVFHMIN-NEXT:    lh t1, 212(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v19
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb t0, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh t1, 338(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV32ZVFHMIN-NEXT:    lh t2, 210(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v21
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    sb t2, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 336(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a0
-; RV32ZVFHMIN-NEXT:    lh t2, 208(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v23
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    sb a1, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 334(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh a7, 206(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v22
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a5, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 332(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    lh a6, 204(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v25
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a5, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 330(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh t0, 202(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t3
-; RV32ZVFHMIN-NEXT:    sb t0, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 328(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV32ZVFHMIN-NEXT:    lh t1, 200(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v27
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    sb t1, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 326(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    lh t1, 198(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v26
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb t1, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 324(sp)
-; RV32ZVFHMIN-NEXT:    lh t1, 196(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb t0, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh t0, 322(sp)
-; RV32ZVFHMIN-NEXT:    lh t1, 194(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb t2, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a4, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a1, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 382(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 254(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 380(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 252(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 378(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 250(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 376(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 248(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v14
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 374(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 246(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v2
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v18
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 372(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v0
-; RV32ZVFHMIN-NEXT:    lh a1, 244(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v20
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    vmv.x.s t3, v4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a1, 370(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    lh a4, 242(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a1, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 368(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    lh a6, 240(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a6, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a6, 366(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    lh a7, 238(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    sb a7, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh a7, 364(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV32ZVFHMIN-NEXT:    lh t1, 236(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v30
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    sb t1, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 362(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    lh a4, 234(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v26
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a4, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 360(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV32ZVFHMIN-NEXT:    lh a6, 232(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v28
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    sb a6, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 358(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    lh a4, 230(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    sb a4, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a4, 356(sp)
-; RV32ZVFHMIN-NEXT:    lh a5, 228(sp)
-; RV32ZVFHMIN-NEXT:    sb t2, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a1, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 79(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a2)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
-; RV32ZVFHMIN-NEXT:    lw ra, 508(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 504(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 512
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16_nonans:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 512
-; RV64ZVFHMIN-NEXT:    sd ra, 504(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 496(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a3, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v16, (a0)
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a1)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 256
-; RV64ZVFHMIN-NEXT:    addi a1, sp, 128
-; RV64ZVFHMIN-NEXT:    vse16.v v16, (a0)
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a1)
-; RV64ZVFHMIN-NEXT:    lh a0, 320(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 192(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 318(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 190(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 316(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 188(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 314(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 186(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 312(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 184(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 310(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 182(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 308(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 180(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 306(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 178(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 304(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 176(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 302(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 174(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 300(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 172(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 298(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 170(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a1, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 296(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 168(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v8
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v16, 7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 294(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 166(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 7
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 292(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 164(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 6
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 290(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 162(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v19, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    sb a4, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 288(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 160(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a1, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 354(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 226(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v21, v8, 4
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v23, v16, 3
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 352(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 224(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 3
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v25, v16, 2
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 350(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 222(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v27, v16, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 348(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 220(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v8, 1
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v16, 15
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 346(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 218(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a1, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a0, v13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 344(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 216(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 15
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 342(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 214(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v16, 14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 340(sp)
-; RV64ZVFHMIN-NEXT:    lh t1, 212(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v19
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb t0, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh t1, 338(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v16, 13
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV64ZVFHMIN-NEXT:    lh t2, 210(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v21
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v16, 12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    sb t2, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 336(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a0
-; RV64ZVFHMIN-NEXT:    lh t2, 208(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v23
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    sb a1, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 334(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh a7, 206(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v22
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v16, 11
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a5, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 332(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    lh a6, 204(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v25
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a5, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 330(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh t0, 202(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v24, v16, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t0
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t3
-; RV64ZVFHMIN-NEXT:    sb t0, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 328(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t2
-; RV64ZVFHMIN-NEXT:    lh t1, 200(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v27
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    sb t1, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 326(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    lh t1, 198(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v26
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v26, v16, 9
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb t1, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 324(sp)
-; RV64ZVFHMIN-NEXT:    lh t1, 196(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb t0, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh t0, 322(sp)
-; RV64ZVFHMIN-NEXT:    lh t1, 194(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb t2, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a4, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a1, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 382(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 254(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v16, 8
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v2, v8, 14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 380(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 252(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v0, v8, 13
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v4, v8, 12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 378(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 250(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v6, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v30, v8, 10
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v28, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 376(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 248(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v14
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 374(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 246(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v2
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v18
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 372(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v0
-; RV64ZVFHMIN-NEXT:    lh a1, 244(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v20
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    vmv.x.s t3, v4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a1
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a1, 370(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    lh a4, 242(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a1
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a1, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 368(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    lh a6, 240(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a6, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a6, 366(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    lh a7, 238(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v24
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    sb a7, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh a7, 364(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t3
-; RV64ZVFHMIN-NEXT:    lh t1, 236(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t2, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v30
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    sb t1, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 362(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    lh a4, 234(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v26
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a4, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 360(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a7
-; RV64ZVFHMIN-NEXT:    lh a6, 232(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v28
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a6
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    sb a6, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 358(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    lh a4, 230(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a4
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa4, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    sb a4, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a4, 356(sp)
-; RV64ZVFHMIN-NEXT:    lh a5, 228(sp)
-; RV64ZVFHMIN-NEXT:    sb t2, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a1, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 79(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa4, a5
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa4, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a2)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 512
-; RV64ZVFHMIN-NEXT:    ld ra, 504(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 496(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 512
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_vv_v64f16_nonans:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    addi sp, sp, -16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; ZVFHMIN-NEXT:    csrr a3, vlenb
+; ZVFHMIN-NEXT:    slli a3, a3, 4
+; ZVFHMIN-NEXT:    sub sp, sp, a3
+; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVFHMIN-NEXT:    li a3, 64
+; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-NEXT:    vle16.v v16, (a1)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v8, a0
+; ZVFHMIN-NEXT:    addi a1, sp, 16
+; ZVFHMIN-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vslidedown.vx v0, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT:    addi a0, sp, 16
+; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    vmv4r.v v24, v0
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v24
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmflt.vv v24, v0, v16
+; ZVFHMIN-NEXT:    vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v24
+; ZVFHMIN-NEXT:    addi a0, sp, 16
+; ZVFHMIN-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v16, v8, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v16, (a2)
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 4
+; ZVFHMIN-NEXT:    add sp, sp, a0
+; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
+; ZVFHMIN-NEXT:    addi sp, sp, 16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = load <64 x half>, ptr %y
   %c = fcmp nnan ugt <64 x half> %a, %b
@@ -3424,743 +1641,31 @@ define void @fcmp_ugt_vf_v64f16(ptr %x, half %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v8, (a1)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a2, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a4, a7, 1
-; RV32ZVFHMIN-NEXT:    xori a5, t0, 1
-; RV32ZVFHMIN-NEXT:    xori a6, t1, 1
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a2, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a4, a7, 1
-; RV64ZVFHMIN-NEXT:    xori a5, t0, 1
-; RV64ZVFHMIN-NEXT:    xori a6, t1, 1
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    li a2, 64
+; ZVFHMIN-NEXT:    fmv.x.h a3, fa0
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v16, (a0)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vmv.v.x v24, a3
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfle.vv v24, v0, v8
+; ZVFHMIN-NEXT:    vmfle.vv v25, v16, v8
+; ZVFHMIN-NEXT:    vmnot.m v8, v25
+; ZVFHMIN-NEXT:    vmnot.m v9, v24
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v9, v8, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v9, (a1)
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = insertelement <64 x half> poison, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -4179,615 +1684,29 @@ define void @fcmp_ugt_vf_v64f16_nonans(ptr %x, half %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v16, (a1)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16_nonans:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a2, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16_nonans:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a2, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_vf_v64f16_nonans:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    li a2, 64
+; ZVFHMIN-NEXT:    fmv.x.h a3, fa0
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v16, (a0)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vmv.v.x v24, a3
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmflt.vv v24, v8, v16
+; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v0
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v16, v24, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v16, (a1)
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = insertelement <64 x half> poison, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -5413,743 +2332,31 @@ define void @fcmp_ugt_fv_v64f16(ptr %x, half %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v8, (a1)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a2, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV32ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV32ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV32ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV32ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV32ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV32ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV32ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a4, a7, 1
-; RV32ZVFHMIN-NEXT:    xori a5, t0, 1
-; RV32ZVFHMIN-NEXT:    xori a6, t1, 1
-; RV32ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV32ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a2, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV64ZVFHMIN-NEXT:    xori a7, a7, 1
-; RV64ZVFHMIN-NEXT:    xori t0, t0, 1
-; RV64ZVFHMIN-NEXT:    xori t1, t1, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a4, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    fle.h a5, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a6, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    fle.h a7, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV64ZVFHMIN-NEXT:    fle.h t0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    fle.h t1, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    xori a4, a4, 1
-; RV64ZVFHMIN-NEXT:    xori a5, a5, 1
-; RV64ZVFHMIN-NEXT:    xori a6, a6, 1
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV64ZVFHMIN-NEXT:    fle.h a3, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a4, a7, 1
-; RV64ZVFHMIN-NEXT:    xori a5, t0, 1
-; RV64ZVFHMIN-NEXT:    xori a6, t1, 1
-; RV64ZVFHMIN-NEXT:    xori a3, a3, 1
-; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    fle.h a0, fa0, fa5
-; RV64ZVFHMIN-NEXT:    xori a0, a0, 1
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    li a2, 64
+; ZVFHMIN-NEXT:    fmv.x.h a3, fa0
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v16, (a0)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vmv.v.x v24, a3
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfle.vv v24, v8, v0
+; ZVFHMIN-NEXT:    vmfle.vv v25, v8, v16
+; ZVFHMIN-NEXT:    vmnot.m v8, v25
+; ZVFHMIN-NEXT:    vmnot.m v9, v24
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v9, v8, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v9, (a1)
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = insertelement <64 x half> poison, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -6168,615 +2375,29 @@ define void @fcmp_ugt_fv_v64f16_nonans(ptr %x, half %y, ptr %z) {
 ; ZVFH-NEXT:    vsm.v v16, (a1)
 ; ZVFH-NEXT:    ret
 ;
-; RV32ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16_nonans:
-; RV32ZVFHMIN:       # %bb.0:
-; RV32ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV32ZVFHMIN-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
-; RV32ZVFHMIN-NEXT:    .cfi_offset ra, -4
-; RV32ZVFHMIN-NEXT:    .cfi_offset s0, -8
-; RV32ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV32ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV32ZVFHMIN-NEXT:    li a2, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV32ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV32ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV32ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV32ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV32ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV32ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV32ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV32ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV32ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV32ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV32ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV32ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV32ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV32ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV32ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV32ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV32ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV32ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV32ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV32ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV32ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV32ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV32ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV32ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV32ZVFHMIN-NEXT:    sb t1, 73(sp)
-; RV32ZVFHMIN-NEXT:    sb t0, 74(sp)
-; RV32ZVFHMIN-NEXT:    sb a7, 75(sp)
-; RV32ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV32ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV32ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV32ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV32ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV32ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV32ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV32ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV32ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV32ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV32ZVFHMIN-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
-; RV32ZVFHMIN-NEXT:    .cfi_restore ra
-; RV32ZVFHMIN-NEXT:    .cfi_restore s0
-; RV32ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV32ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV32ZVFHMIN-NEXT:    ret
-;
-; RV64ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16_nonans:
-; RV64ZVFHMIN:       # %bb.0:
-; RV64ZVFHMIN-NEXT:    addi sp, sp, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 384
-; RV64ZVFHMIN-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
-; RV64ZVFHMIN-NEXT:    .cfi_offset ra, -8
-; RV64ZVFHMIN-NEXT:    .cfi_offset s0, -16
-; RV64ZVFHMIN-NEXT:    addi s0, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa s0, 0
-; RV64ZVFHMIN-NEXT:    andi sp, sp, -128
-; RV64ZVFHMIN-NEXT:    li a2, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT:    vle16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 128
-; RV64ZVFHMIN-NEXT:    vse16.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    lh a0, 192(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 96(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 190(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 95(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 188(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 94(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 186(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 93(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 184(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 92(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 182(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 91(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 180(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 90(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 178(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 89(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 176(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 88(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 174(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 87(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 172(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 86(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 170(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 85(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 168(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 84(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 166(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 83(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 164(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 82(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 162(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 81(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 160(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a3, 64(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 80(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 226(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 113(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 224(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 112(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 222(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 111(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 220(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 110(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 218(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 109(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 216(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 108(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 214(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 107(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 212(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 7
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 106(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 210(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v11, v8, 6
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 5
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v13, v8, 4
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 105(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 208(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 3
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v15, v8, 2
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 1
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 104(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 206(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v11
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v12
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 103(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 204(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v13
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v15
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 102(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 202(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    sb a0, 101(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 200(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a0, 100(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 198(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a0, 99(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 196(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 98(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 194(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 65(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 66(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 67(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 68(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a5, 69(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 70(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 71(sp)
-; RV64ZVFHMIN-NEXT:    sb a0, 97(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 254(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 127(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 252(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 126(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 250(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 125(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 248(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 124(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 246(sp)
-; RV64ZVFHMIN-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v10, v8, 15
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v12, v8, 14
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v14, v8, 13
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 123(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 244(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v16, v8, 12
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v18, v8, 11
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v20, v8, 10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 122(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 242(sp)
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v22, v8, 9
-; RV64ZVFHMIN-NEXT:    vslidedown.vi v8, v8, 8
-; RV64ZVFHMIN-NEXT:    vmv.x.s a3, v10
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 121(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 240(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a4, v12
-; RV64ZVFHMIN-NEXT:    vmv.x.s a5, v14
-; RV64ZVFHMIN-NEXT:    vmv.x.s a6, v16
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 120(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 238(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s a7, v18
-; RV64ZVFHMIN-NEXT:    vmv.x.s t0, v20
-; RV64ZVFHMIN-NEXT:    vmv.x.s t1, v22
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 119(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 236(sp)
-; RV64ZVFHMIN-NEXT:    vmv.x.s t2, v8
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a3
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a4
-; RV64ZVFHMIN-NEXT:    sb a0, 118(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 234(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a4, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a5
-; RV64ZVFHMIN-NEXT:    flt.h a5, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a6
-; RV64ZVFHMIN-NEXT:    sb a0, 117(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 232(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a6, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a7
-; RV64ZVFHMIN-NEXT:    flt.h a7, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t0
-; RV64ZVFHMIN-NEXT:    sb a0, 116(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 230(sp)
-; RV64ZVFHMIN-NEXT:    flt.h t0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t1
-; RV64ZVFHMIN-NEXT:    flt.h t1, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, t2
-; RV64ZVFHMIN-NEXT:    sb a0, 115(sp)
-; RV64ZVFHMIN-NEXT:    lh a0, 228(sp)
-; RV64ZVFHMIN-NEXT:    sb a6, 76(sp)
-; RV64ZVFHMIN-NEXT:    sb a5, 77(sp)
-; RV64ZVFHMIN-NEXT:    sb a4, 78(sp)
-; RV64ZVFHMIN-NEXT:    sb a3, 79(sp)
-; RV64ZVFHMIN-NEXT:    flt.h a3, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a3, 72(sp)
-; RV64ZVFHMIN-NEXT:    sb t1, 73(sp)
-; RV64ZVFHMIN-NEXT:    sb t0, 74(sp)
-; RV64ZVFHMIN-NEXT:    sb a7, 75(sp)
-; RV64ZVFHMIN-NEXT:    fmv.h.x fa5, a0
-; RV64ZVFHMIN-NEXT:    flt.h a0, fa5, fa0
-; RV64ZVFHMIN-NEXT:    sb a0, 114(sp)
-; RV64ZVFHMIN-NEXT:    addi a0, sp, 64
-; RV64ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64ZVFHMIN-NEXT:    vle8.v v8, (a0)
-; RV64ZVFHMIN-NEXT:    vand.vi v8, v8, 1
-; RV64ZVFHMIN-NEXT:    vmsne.vi v12, v8, 0
-; RV64ZVFHMIN-NEXT:    vsm.v v12, (a1)
-; RV64ZVFHMIN-NEXT:    addi sp, s0, -384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa sp, 384
-; RV64ZVFHMIN-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
-; RV64ZVFHMIN-NEXT:    .cfi_restore ra
-; RV64ZVFHMIN-NEXT:    .cfi_restore s0
-; RV64ZVFHMIN-NEXT:    addi sp, sp, 384
-; RV64ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
-; RV64ZVFHMIN-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_ugt_fv_v64f16_nonans:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    li a2, 64
+; ZVFHMIN-NEXT:    fmv.x.h a3, fa0
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v16, (a0)
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vmv.v.x v24, a3
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmflt.vv v24, v16, v8
+; ZVFHMIN-NEXT:    vmflt.vv v16, v0, v8
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v16, v24, 4
+; ZVFHMIN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
+; ZVFHMIN-NEXT:    vsm.v v16, (a1)
+; ZVFHMIN-NEXT:    ret
   %a = load <64 x half>, ptr %x
   %b = insertelement <64 x half> poison, half %y, i32 0
   %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -6962,3 +2583,82 @@ define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
   store <2 x i1> %d, ptr %z
   ret void
 }
+define void @fcmp_oeq_vv_v64bf16(ptr %x, ptr %y, ptr %z) {
+; ZVFBFMIN-LABEL: fcmp_oeq_vv_v64bf16:
+; ZVFBFMIN:       # %bb.0:
+; ZVFBFMIN-NEXT:    addi sp, sp, -16
+; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 16
+; ZVFBFMIN-NEXT:    csrr a3, vlenb
+; ZVFBFMIN-NEXT:    slli a3, a3, 4
+; ZVFBFMIN-NEXT:    sub sp, sp, a3
+; ZVFBFMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVFBFMIN-NEXT:    li a3, 64
+; ZVFBFMIN-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
+; ZVFBFMIN-NEXT:    vle16.v v16, (a1)
+; ZVFBFMIN-NEXT:    vle16.v v8, (a0)
+; ZVFBFMIN-NEXT:    li a0, 32
+; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT:    vslidedown.vx v24, v16, a0
+; ZVFBFMIN-NEXT:    addi a1, sp, 16
+; ZVFBFMIN-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT:    vslidedown.vx v0, v8, a0
+; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v16
+; ZVFBFMIN-NEXT:    csrr a0, vlenb
+; ZVFBFMIN-NEXT:    slli a0, a0, 3
+; ZVFBFMIN-NEXT:    add a0, sp, a0
+; ZVFBFMIN-NEXT:    addi a0, a0, 16
+; ZVFBFMIN-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT:    addi a0, sp, 16
+; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v8, v24
+; ZVFBFMIN-NEXT:    vmv4r.v v24, v0
+; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v0, v24
+; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFBFMIN-NEXT:    vmfeq.vv v24, v0, v8
+; ZVFBFMIN-NEXT:    vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; ZVFBFMIN-NEXT:    csrr a0, vlenb
+; ZVFBFMIN-NEXT:    slli a0, a0, 3
+; ZVFBFMIN-NEXT:    add a0, sp, a0
+; ZVFBFMIN-NEXT:    addi a0, a0, 16
+; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT:    vmfeq.vv v8, v16, v24
+; ZVFBFMIN-NEXT:    addi a0, sp, 16
+; ZVFBFMIN-NEXT:    vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
+; ZVFBFMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT:    vslideup.vi v8, v9, 4
+; ZVFBFMIN-NEXT:    vsetvli zero, a3, e8, m4, ta, ma
+; ZVFBFMIN-NEXT:    vsm.v v8, (a2)
+; ZVFBFMIN-NEXT:    csrr a0, vlenb
+; ZVFBFMIN-NEXT:    slli a0, a0, 4
+; ZVFBFMIN-NEXT:    add sp, sp, a0
+; ZVFBFMIN-NEXT:    .cfi_def_cfa sp, 16
+; ZVFBFMIN-NEXT:    addi sp, sp, 16
+; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 0
+; ZVFBFMIN-NEXT:    ret
+;
+; ZVFBFA-LABEL: fcmp_oeq_vv_v64bf16:
+; ZVFBFA:       # %bb.0:
+; ZVFBFA-NEXT:    li a3, 64
+; ZVFBFA-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
+; ZVFBFA-NEXT:    vle16.v v8, (a1)
+; ZVFBFA-NEXT:    vle16.v v16, (a0)
+; ZVFBFA-NEXT:    li a0, 32
+; ZVFBFA-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFA-NEXT:    vslidedown.vx v24, v8, a0
+; ZVFBFA-NEXT:    vslidedown.vx v0, v16, a0
+; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT:    vmfeq.vv v12, v0, v24
+; ZVFBFA-NEXT:    vmfeq.vv v13, v16, v8
+; ZVFBFA-NEXT:    vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT:    vslideup.vi v13, v12, 4
+; ZVFBFA-NEXT:    vsetvli zero, a3, e8alt, m4, ta, ma
+; ZVFBFA-NEXT:    vsm.v v13, (a2)
+; ZVFBFA-NEXT:    ret
+  %a = load <64 x bfloat>, ptr %x
+  %b = load <64 x bfloat>, ptr %y
+  %c = fcmp oeq <64 x bfloat> %a, %b
+  store <64 x i1> %c, ptr %z
+  ret void
+}

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lmul-max.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lmul-max.ll
new file mode 100644
index 0000000000000..bbff025fb07a0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lmul-max.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin
+;          -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s
+
+define <32 x i1> @fcmp_oeq_vv_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
+; CHECK-LABEL: fcmp_oeq_vv_v32bf16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e16, m4, ta, ma
+; CHECK-NEXT:    vslidedown.vi v16, v12, 16
+; CHECK-NEXT:    vslidedown.vi v20, v8, 16
+; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v12
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v16
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v20
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vmfeq.vv v20, v16, v8
+; CHECK-NEXT:    vmfeq.vv v0, v12, v24
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vslideup.vi v0, v20, 2
+; CHECK-NEXT:    ret
+  %c = fcmp oeq <32 x bfloat> %a, %b
+  ret <32 x i1> %c
+}
+
+define <32 x i1> @fcmp_oeq_vv_v32f16(<32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: fcmp_oeq_vv_v32f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e16, m4, ta, ma
+; CHECK-NEXT:    vslidedown.vi v16, v12, 16
+; CHECK-NEXT:    vslidedown.vi v20, v8, 16
+; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vfwcvt.f.f.v v24, v12
+; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
+; CHECK-NEXT:    vfwcvt.f.f.v v8, v16
+; CHECK-NEXT:    vfwcvt.f.f.v v16, v20
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vmfeq.vv v20, v16, v8
+; CHECK-NEXT:    vmfeq.vv v0, v12, v24
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vslideup.vi v0, v20, 2
+; CHECK-NEXT:    ret
+  %c = fcmp oeq <32 x half> %a, %b
+  ret <32 x i1> %c
+}

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
index 5defaabccca30..a09e5582a3aea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
@@ -1,15 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfh -target-abi=ilp32d \
-; RUN:   -verify-machineinstrs < %s | FileCheck %s \
-; RUN:   --check-prefixes=CHECK,ZVFH,ZVFH32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfh -target-abi=lp64d \
-; RUN:   -verify-machineinstrs < %s | FileCheck %s \
-; RUN:   --check-prefixes=CHECK,ZVFH,ZVFH64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfhmin -target-abi=ilp32d \
-; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfhmin -target-abi=lp64d \
-; RUN:   -verify-machineinstrs < %s | FileCheck %s \
-; RUN:   --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfh,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfh,+zfbfmin,+zvfbfmin -target-abi=lp64d \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin -target-abi=lp64d \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
 
 define <7 x i1> @fcmp_oeq_vv_v7f16(<7 x half> %va, <7 x half> %vb, <7 x i1> %m, i32 zeroext %evl) {
 ; ZVFH-LABEL: fcmp_oeq_vv_v7f16:
@@ -1058,2269 +1055,114 @@ define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128
 ; ZVFH-NEXT:    .cfi_def_cfa_offset 0
 ; ZVFH-NEXT:    ret
 ;
-; ZVFHMIN32-LABEL: fcmp_oeq_vv_v128f16:
-; ZVFHMIN32:       # %bb.0:
-; ZVFHMIN32-NEXT:    addi sp, sp, -912
-; ZVFHMIN32-NEXT:    .cfi_def_cfa_offset 912
-; ZVFHMIN32-NEXT:    sw ra, 908(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s0, 904(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s1, 900(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s2, 896(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s3, 892(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s4, 888(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s5, 884(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s6, 880(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s7, 876(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s8, 872(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s9, 868(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s10, 864(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    sw s11, 860(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    .cfi_offset ra, -4
-; ZVFHMIN32-NEXT:    .cfi_offset s0, -8
-; ZVFHMIN32-NEXT:    .cfi_offset s1, -12
-; ZVFHMIN32-NEXT:    .cfi_offset s2, -16
-; ZVFHMIN32-NEXT:    .cfi_offset s3, -20
-; ZVFHMIN32-NEXT:    .cfi_offset s4, -24
-; ZVFHMIN32-NEXT:    .cfi_offset s5, -28
-; ZVFHMIN32-NEXT:    .cfi_offset s6, -32
-; ZVFHMIN32-NEXT:    .cfi_offset s7, -36
-; ZVFHMIN32-NEXT:    .cfi_offset s8, -40
-; ZVFHMIN32-NEXT:    .cfi_offset s9, -44
-; ZVFHMIN32-NEXT:    .cfi_offset s10, -48
-; ZVFHMIN32-NEXT:    .cfi_offset s11, -52
-; ZVFHMIN32-NEXT:    addi s0, sp, 912
-; ZVFHMIN32-NEXT:    .cfi_def_cfa s0, 0
-; ZVFHMIN32-NEXT:    csrr a1, vlenb
-; ZVFHMIN32-NEXT:    li a2, 29
-; ZVFHMIN32-NEXT:    mul a1, a1, a2
-; ZVFHMIN32-NEXT:    sub sp, sp, a1
-; ZVFHMIN32-NEXT:    andi sp, sp, -128
-; ZVFHMIN32-NEXT:    addi a1, a0, 128
-; ZVFHMIN32-NEXT:    li a2, 64
-; ZVFHMIN32-NEXT:    addi a3, sp, 640
-; ZVFHMIN32-NEXT:    addi a4, sp, 384
-; ZVFHMIN32-NEXT:    addi a5, sp, 512
-; ZVFHMIN32-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; ZVFHMIN32-NEXT:    vle16.v v0, (a0)
-; ZVFHMIN32-NEXT:    addi a0, sp, 256
-; ZVFHMIN32-NEXT:    vle16.v v24, (a1)
-; ZVFHMIN32-NEXT:    vse16.v v8, (a3)
-; ZVFHMIN32-NEXT:    vse16.v v0, (a4)
-; ZVFHMIN32-NEXT:    vse16.v v16, (a5)
-; ZVFHMIN32-NEXT:    vse16.v v24, (a0)
-; ZVFHMIN32-NEXT:    lh a0, 704(sp)
-; ZVFHMIN32-NEXT:    lh a1, 448(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 160(sp)
-; ZVFHMIN32-NEXT:    lh a0, 702(sp)
-; ZVFHMIN32-NEXT:    lh a1, 446(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 159(sp)
-; ZVFHMIN32-NEXT:    lh a0, 700(sp)
-; ZVFHMIN32-NEXT:    lh a1, 444(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 158(sp)
-; ZVFHMIN32-NEXT:    lh a0, 698(sp)
-; ZVFHMIN32-NEXT:    lh a1, 442(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 157(sp)
-; ZVFHMIN32-NEXT:    lh a0, 696(sp)
-; ZVFHMIN32-NEXT:    lh a1, 440(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 156(sp)
-; ZVFHMIN32-NEXT:    lh a0, 694(sp)
-; ZVFHMIN32-NEXT:    lh a1, 438(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 155(sp)
-; ZVFHMIN32-NEXT:    lh a0, 692(sp)
-; ZVFHMIN32-NEXT:    lh a1, 436(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 154(sp)
-; ZVFHMIN32-NEXT:    lh a0, 690(sp)
-; ZVFHMIN32-NEXT:    lh a1, 434(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 153(sp)
-; ZVFHMIN32-NEXT:    lh a0, 688(sp)
-; ZVFHMIN32-NEXT:    lh a1, 432(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 152(sp)
-; ZVFHMIN32-NEXT:    lh a0, 686(sp)
-; ZVFHMIN32-NEXT:    lh a1, 430(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 151(sp)
-; ZVFHMIN32-NEXT:    lh a0, 684(sp)
-; ZVFHMIN32-NEXT:    lh a1, 428(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 150(sp)
-; ZVFHMIN32-NEXT:    lh a0, 682(sp)
-; ZVFHMIN32-NEXT:    lh a1, 426(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 149(sp)
-; ZVFHMIN32-NEXT:    lh a0, 680(sp)
-; ZVFHMIN32-NEXT:    lh a1, 424(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 148(sp)
-; ZVFHMIN32-NEXT:    lh a0, 678(sp)
-; ZVFHMIN32-NEXT:    lh a1, 422(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 147(sp)
-; ZVFHMIN32-NEXT:    lh a0, 676(sp)
-; ZVFHMIN32-NEXT:    lh a1, 420(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 146(sp)
-; ZVFHMIN32-NEXT:    lh a0, 674(sp)
-; ZVFHMIN32-NEXT:    lh a1, 418(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a2
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 145(sp)
-; ZVFHMIN32-NEXT:    lh a0, 672(sp)
-; ZVFHMIN32-NEXT:    lh a1, 416(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a2, 128(sp)
-; ZVFHMIN32-NEXT:    sb a0, 144(sp)
-; ZVFHMIN32-NEXT:    lh a0, 576(sp)
-; ZVFHMIN32-NEXT:    lh a1, 320(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 224(sp)
-; ZVFHMIN32-NEXT:    lh a0, 574(sp)
-; ZVFHMIN32-NEXT:    lh a1, 318(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 223(sp)
-; ZVFHMIN32-NEXT:    lh a0, 572(sp)
-; ZVFHMIN32-NEXT:    lh a1, 316(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 222(sp)
-; ZVFHMIN32-NEXT:    lh a0, 570(sp)
-; ZVFHMIN32-NEXT:    lh a1, 314(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 221(sp)
-; ZVFHMIN32-NEXT:    lh a0, 568(sp)
-; ZVFHMIN32-NEXT:    lh a1, 312(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 220(sp)
-; ZVFHMIN32-NEXT:    lh a0, 566(sp)
-; ZVFHMIN32-NEXT:    lh a1, 310(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 219(sp)
-; ZVFHMIN32-NEXT:    lh a0, 564(sp)
-; ZVFHMIN32-NEXT:    lh a1, 308(sp)
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 7
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 28
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 6
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 27
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 5
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 26
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 4
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 25
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 3
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 24
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 2
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 23
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 1
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 22
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v4, v8, 15
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v8, 14
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v2, v8, 13
-; ZVFHMIN32-NEXT:    vslidedown.vi v30, v8, 12
-; ZVFHMIN32-NEXT:    vslidedown.vi v28, v8, 11
-; ZVFHMIN32-NEXT:    vslidedown.vi v26, v8, 10
-; ZVFHMIN32-NEXT:    vslidedown.vi v22, v8, 9
-; ZVFHMIN32-NEXT:    vslidedown.vi v20, v8, 8
-; ZVFHMIN32-NEXT:    vmv.x.s t5, v16
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 218(sp)
-; ZVFHMIN32-NEXT:    lh a0, 562(sp)
-; ZVFHMIN32-NEXT:    lh a1, 306(sp)
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v21, v16, 7
-; ZVFHMIN32-NEXT:    vslidedown.vi v31, v16, 6
-; ZVFHMIN32-NEXT:    vslidedown.vi v23, v16, 5
-; ZVFHMIN32-NEXT:    vslidedown.vi v27, v16, 4
-; ZVFHMIN32-NEXT:    vslidedown.vi v29, v16, 3
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v16, 2
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 19
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v16, 1
-; ZVFHMIN32-NEXT:    addi a2, sp, 848
-; ZVFHMIN32-NEXT:    vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v18, v16, 15
-; ZVFHMIN32-NEXT:    vslidedown.vi v14, v16, 14
-; ZVFHMIN32-NEXT:    vslidedown.vi v12, v16, 13
-; ZVFHMIN32-NEXT:    vslidedown.vi v10, v16, 12
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v16, 11
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v16, 10
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 20
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v16, 9
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 4
-; ZVFHMIN32-NEXT:    sub a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v16, v16, 8
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 13
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v16, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 217(sp)
-; ZVFHMIN32-NEXT:    lh a0, 560(sp)
-; ZVFHMIN32-NEXT:    lh a1, 304(sp)
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v3, v0, 7
-; ZVFHMIN32-NEXT:    vslidedown.vi v9, v0, 6
-; ZVFHMIN32-NEXT:    vslidedown.vi v15, v0, 5
-; ZVFHMIN32-NEXT:    vslidedown.vi v19, v0, 4
-; ZVFHMIN32-NEXT:    vslidedown.vi v11, v0, 3
-; ZVFHMIN32-NEXT:    vslidedown.vi v13, v0, 2
-; ZVFHMIN32-NEXT:    vslidedown.vi v16, v0, 1
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 15
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 1
-; ZVFHMIN32-NEXT:    add a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 14
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 3
-; ZVFHMIN32-NEXT:    sub a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 13
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 2
-; ZVFHMIN32-NEXT:    add a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 12
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 11
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 11
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 3
-; ZVFHMIN32-NEXT:    add a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 10
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 4
-; ZVFHMIN32-NEXT:    add a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN32-NEXT:    vslidedown.vi v6, v0, 9
-; ZVFHMIN32-NEXT:    vslidedown.vi v0, v0, 8
-; ZVFHMIN32-NEXT:    vmv.x.s t3, v4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 216(sp)
-; ZVFHMIN32-NEXT:    lh a0, 558(sp)
-; ZVFHMIN32-NEXT:    lh a1, 302(sp)
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v4, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s t4, v4
-; ZVFHMIN32-NEXT:    vmv.x.s t2, v2
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 215(sp)
-; ZVFHMIN32-NEXT:    lh a0, 556(sp)
-; ZVFHMIN32-NEXT:    lh a1, 300(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s t1, v30
-; ZVFHMIN32-NEXT:    vmv.x.s t0, v28
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 214(sp)
-; ZVFHMIN32-NEXT:    lh a0, 554(sp)
-; ZVFHMIN32-NEXT:    lh a1, 298(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a7, v26
-; ZVFHMIN32-NEXT:    vmv.x.s a6, v22
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 213(sp)
-; ZVFHMIN32-NEXT:    lh a0, 552(sp)
-; ZVFHMIN32-NEXT:    lh a1, 296(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a5, v20
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v18
-; ZVFHMIN32-NEXT:    sw a2, 108(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 212(sp)
-; ZVFHMIN32-NEXT:    lh a0, 550(sp)
-; ZVFHMIN32-NEXT:    lh a1, 294(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v14
-; ZVFHMIN32-NEXT:    sw a2, 112(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v12
-; ZVFHMIN32-NEXT:    sw a2, 116(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 211(sp)
-; ZVFHMIN32-NEXT:    lh t6, 548(sp)
-; ZVFHMIN32-NEXT:    lh s1, 292(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a0, v10
-; ZVFHMIN32-NEXT:    sw a0, 120(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    vmv.x.s a0, v8
-; ZVFHMIN32-NEXT:    sw a0, 124(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s1
-; ZVFHMIN32-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t6, 210(sp)
-; ZVFHMIN32-NEXT:    lh t6, 546(sp)
-; ZVFHMIN32-NEXT:    lh s1, 290(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    vmv.x.s t5, v24
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s1
-; ZVFHMIN32-NEXT:    feq.h t6, fa4, fa3
-; ZVFHMIN32-NEXT:    sb t6, 209(sp)
-; ZVFHMIN32-NEXT:    lh t6, 544(sp)
-; ZVFHMIN32-NEXT:    lh s1, 288(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t5
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s1
-; ZVFHMIN32-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t5, 192(sp)
-; ZVFHMIN32-NEXT:    sb t6, 208(sp)
-; ZVFHMIN32-NEXT:    lh t5, 738(sp)
-; ZVFHMIN32-NEXT:    lh t6, 482(sp)
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 28
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s7, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 27
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s5, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t5, 177(sp)
-; ZVFHMIN32-NEXT:    lh t5, 736(sp)
-; ZVFHMIN32-NEXT:    lh t6, 480(sp)
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 26
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s8, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 25
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s6, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t5, 176(sp)
-; ZVFHMIN32-NEXT:    lh t5, 734(sp)
-; ZVFHMIN32-NEXT:    lh t6, 478(sp)
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 24
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s4, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 23
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s3, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t5, 175(sp)
-; ZVFHMIN32-NEXT:    lh t5, 732(sp)
-; ZVFHMIN32-NEXT:    lh t6, 476(sp)
-; ZVFHMIN32-NEXT:    csrr a0, vlenb
-; ZVFHMIN32-NEXT:    li a1, 22
-; ZVFHMIN32-NEXT:    mul a0, a0, a1
-; ZVFHMIN32-NEXT:    add a0, sp, a0
-; ZVFHMIN32-NEXT:    lh s2, 848(a0) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s s1, v21
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    sb t5, 174(sp)
-; ZVFHMIN32-NEXT:    lh s9, 730(sp)
-; ZVFHMIN32-NEXT:    lh s10, 474(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s t6, v31
-; ZVFHMIN32-NEXT:    vmv.x.s t5, v23
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN32-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN32-NEXT:    sb s9, 173(sp)
-; ZVFHMIN32-NEXT:    lh s9, 728(sp)
-; ZVFHMIN32-NEXT:    lh s10, 472(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s11, v3
-; ZVFHMIN32-NEXT:    vmv.x.s ra, v9
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN32-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN32-NEXT:    sb s9, 172(sp)
-; ZVFHMIN32-NEXT:    lh s9, 726(sp)
-; ZVFHMIN32-NEXT:    lh s10, 470(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v15
-; ZVFHMIN32-NEXT:    vmv.x.s a3, v19
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN32-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN32-NEXT:    sb s9, 171(sp)
-; ZVFHMIN32-NEXT:    lh s9, 724(sp)
-; ZVFHMIN32-NEXT:    lh a0, 468(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a4, v11
-; ZVFHMIN32-NEXT:    vmv.x.s s10, v13
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 170(sp)
-; ZVFHMIN32-NEXT:    lh a0, 722(sp)
-; ZVFHMIN32-NEXT:    lh a1, 466(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s9, v16
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s7
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 169(sp)
-; ZVFHMIN32-NEXT:    lh a0, 720(sp)
-; ZVFHMIN32-NEXT:    lh a1, 464(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s5
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s8
-; ZVFHMIN32-NEXT:    fmv.h.x fa2, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa1, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa2, fa1
-; ZVFHMIN32-NEXT:    sb a0, 168(sp)
-; ZVFHMIN32-NEXT:    lh a0, 718(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa2, s6
-; ZVFHMIN32-NEXT:    lh a1, 462(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa1, s11
-; ZVFHMIN32-NEXT:    fmv.h.x fa0, a0
-; ZVFHMIN32-NEXT:    feq.h s5, fa5, fa1
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa0, fa5
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, ra
-; ZVFHMIN32-NEXT:    sb a0, 167(sp)
-; ZVFHMIN32-NEXT:    lh a0, 716(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa1, a2
-; ZVFHMIN32-NEXT:    lh a1, 460(sp)
-; ZVFHMIN32-NEXT:    feq.h a2, fa4, fa5
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    feq.h a0, fa3, fa1
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s4
-; ZVFHMIN32-NEXT:    sb a1, 166(sp)
-; ZVFHMIN32-NEXT:    lh a1, 714(sp)
-; ZVFHMIN32-NEXT:    lh s4, 458(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT:    feq.h a3, fa2, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s4
-; ZVFHMIN32-NEXT:    feq.h a1, fa4, fa3
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s3
-; ZVFHMIN32-NEXT:    sb a1, 165(sp)
-; ZVFHMIN32-NEXT:    lh a1, 712(sp)
-; ZVFHMIN32-NEXT:    lh s3, 456(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a4
-; ZVFHMIN32-NEXT:    feq.h a4, fa5, fa3
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s3
-; ZVFHMIN32-NEXT:    feq.h a1, fa5, fa3
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s2
-; ZVFHMIN32-NEXT:    sb a1, 164(sp)
-; ZVFHMIN32-NEXT:    lh a1, 710(sp)
-; ZVFHMIN32-NEXT:    lh s2, 454(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s10
-; ZVFHMIN32-NEXT:    feq.h s3, fa4, fa3
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, s2
-; ZVFHMIN32-NEXT:    feq.h a1, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a1, 163(sp)
-; ZVFHMIN32-NEXT:    lh a1, 708(sp)
-; ZVFHMIN32-NEXT:    lh s2, 452(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s9
-; ZVFHMIN32-NEXT:    feq.h s4, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN32-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a1, 162(sp)
-; ZVFHMIN32-NEXT:    lh a1, 706(sp)
-; ZVFHMIN32-NEXT:    lh s2, 450(sp)
-; ZVFHMIN32-NEXT:    sb s4, 129(sp)
-; ZVFHMIN32-NEXT:    sb s3, 130(sp)
-; ZVFHMIN32-NEXT:    sb a4, 131(sp)
-; ZVFHMIN32-NEXT:    sb a3, 132(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN32-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 133(sp)
-; ZVFHMIN32-NEXT:    sb a2, 134(sp)
-; ZVFHMIN32-NEXT:    sb s5, 135(sp)
-; ZVFHMIN32-NEXT:    sb a1, 161(sp)
-; ZVFHMIN32-NEXT:    lh a0, 610(sp)
-; ZVFHMIN32-NEXT:    lh a1, 354(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s5, v27
-; ZVFHMIN32-NEXT:    vmv.x.s s4, v29
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 241(sp)
-; ZVFHMIN32-NEXT:    lh a0, 608(sp)
-; ZVFHMIN32-NEXT:    lh a1, 352(sp)
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 19
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    lh s3, 848(a2) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    lh s2, 848(sp) # 8-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 240(sp)
-; ZVFHMIN32-NEXT:    lh a0, 606(sp)
-; ZVFHMIN32-NEXT:    lh a1, 350(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s1
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 7
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 239(sp)
-; ZVFHMIN32-NEXT:    lh a0, 604(sp)
-; ZVFHMIN32-NEXT:    lh a1, 348(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 6
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 238(sp)
-; ZVFHMIN32-NEXT:    lh a0, 602(sp)
-; ZVFHMIN32-NEXT:    lh a1, 346(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a3, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 5
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 237(sp)
-; ZVFHMIN32-NEXT:    lh a0, 600(sp)
-; ZVFHMIN32-NEXT:    lh a1, 344(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a4, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 4
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 236(sp)
-; ZVFHMIN32-NEXT:    lh a0, 598(sp)
-; ZVFHMIN32-NEXT:    lh a1, 342(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s6, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 3
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 235(sp)
-; ZVFHMIN32-NEXT:    lh a0, 596(sp)
-; ZVFHMIN32-NEXT:    lh a1, 340(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s7, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 2
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 234(sp)
-; ZVFHMIN32-NEXT:    lh a0, 594(sp)
-; ZVFHMIN32-NEXT:    lh a1, 338(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s s8, v8
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 1
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN32-NEXT:    sb a0, 233(sp)
-; ZVFHMIN32-NEXT:    lh a0, 592(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT:    lh a1, 336(sp)
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa3, a0
-; ZVFHMIN32-NEXT:    feq.h s1, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa3, fa5
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN32-NEXT:    sb a0, 232(sp)
-; ZVFHMIN32-NEXT:    lh a0, 590(sp)
-; ZVFHMIN32-NEXT:    lh a1, 334(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    sb a0, 231(sp)
-; ZVFHMIN32-NEXT:    lh a0, 588(sp)
-; ZVFHMIN32-NEXT:    lh a1, 332(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a4
-; ZVFHMIN32-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s5
-; ZVFHMIN32-NEXT:    sb a0, 230(sp)
-; ZVFHMIN32-NEXT:    lh a0, 586(sp)
-; ZVFHMIN32-NEXT:    lh a1, 330(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s6
-; ZVFHMIN32-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s4
-; ZVFHMIN32-NEXT:    sb a0, 229(sp)
-; ZVFHMIN32-NEXT:    lh a0, 584(sp)
-; ZVFHMIN32-NEXT:    lh a1, 328(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s7
-; ZVFHMIN32-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s3
-; ZVFHMIN32-NEXT:    sb a0, 228(sp)
-; ZVFHMIN32-NEXT:    lh a0, 582(sp)
-; ZVFHMIN32-NEXT:    lh a1, 326(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s8
-; ZVFHMIN32-NEXT:    feq.h s3, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s2
-; ZVFHMIN32-NEXT:    sb a0, 227(sp)
-; ZVFHMIN32-NEXT:    lh a0, 580(sp)
-; ZVFHMIN32-NEXT:    lh a1, 324(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 226(sp)
-; ZVFHMIN32-NEXT:    lh a0, 578(sp)
-; ZVFHMIN32-NEXT:    lh a1, 322(sp)
-; ZVFHMIN32-NEXT:    sb a2, 193(sp)
-; ZVFHMIN32-NEXT:    sb s3, 194(sp)
-; ZVFHMIN32-NEXT:    sb t5, 195(sp)
-; ZVFHMIN32-NEXT:    sb a4, 196(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a3, 197(sp)
-; ZVFHMIN32-NEXT:    sb t6, 198(sp)
-; ZVFHMIN32-NEXT:    sb s1, 199(sp)
-; ZVFHMIN32-NEXT:    sb a0, 225(sp)
-; ZVFHMIN32-NEXT:    lh a0, 766(sp)
-; ZVFHMIN32-NEXT:    lh a1, 510(sp)
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 20
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s s1, v8
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 4
-; ZVFHMIN32-NEXT:    sub a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s t5, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 191(sp)
-; ZVFHMIN32-NEXT:    lh a0, 764(sp)
-; ZVFHMIN32-NEXT:    lh a1, 508(sp)
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    li a3, 13
-; ZVFHMIN32-NEXT:    mul a2, a2, a3
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s t6, v8
-; ZVFHMIN32-NEXT:    csrr a2, vlenb
-; ZVFHMIN32-NEXT:    slli a3, a2, 1
-; ZVFHMIN32-NEXT:    add a2, a3, a2
-; ZVFHMIN32-NEXT:    add a2, sp, a2
-; ZVFHMIN32-NEXT:    addi a2, a2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 190(sp)
-; ZVFHMIN32-NEXT:    lh a0, 762(sp)
-; ZVFHMIN32-NEXT:    lh a1, 506(sp)
-; ZVFHMIN32-NEXT:    csrr a3, vlenb
-; ZVFHMIN32-NEXT:    slli a4, a3, 3
-; ZVFHMIN32-NEXT:    sub a3, a4, a3
-; ZVFHMIN32-NEXT:    add a3, sp, a3
-; ZVFHMIN32-NEXT:    addi a3, a3, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s a3, v8
-; ZVFHMIN32-NEXT:    csrr a4, vlenb
-; ZVFHMIN32-NEXT:    slli s2, a4, 2
-; ZVFHMIN32-NEXT:    add a4, s2, a4
-; ZVFHMIN32-NEXT:    add a4, sp, a4
-; ZVFHMIN32-NEXT:    addi a4, a4, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (a4) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s a4, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 189(sp)
-; ZVFHMIN32-NEXT:    lh a0, 760(sp)
-; ZVFHMIN32-NEXT:    lh a1, 504(sp)
-; ZVFHMIN32-NEXT:    csrr s2, vlenb
-; ZVFHMIN32-NEXT:    li s3, 11
-; ZVFHMIN32-NEXT:    mul s2, s2, s3
-; ZVFHMIN32-NEXT:    add s2, sp, s2
-; ZVFHMIN32-NEXT:    addi s2, s2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s s5, v8
-; ZVFHMIN32-NEXT:    csrr s2, vlenb
-; ZVFHMIN32-NEXT:    slli s3, s2, 3
-; ZVFHMIN32-NEXT:    add s2, s3, s2
-; ZVFHMIN32-NEXT:    add s2, sp, s2
-; ZVFHMIN32-NEXT:    addi s2, s2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s s3, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 188(sp)
-; ZVFHMIN32-NEXT:    lh a0, 758(sp)
-; ZVFHMIN32-NEXT:    lh a1, 502(sp)
-; ZVFHMIN32-NEXT:    csrr s2, vlenb
-; ZVFHMIN32-NEXT:    slli s4, s2, 4
-; ZVFHMIN32-NEXT:    add s2, s4, s2
-; ZVFHMIN32-NEXT:    add s2, sp, s2
-; ZVFHMIN32-NEXT:    addi s2, s2, 848
-; ZVFHMIN32-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN32-NEXT:    vmv.x.s s4, v8
-; ZVFHMIN32-NEXT:    vmv.x.s s2, v6
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t3
-; ZVFHMIN32-NEXT:    sb a0, 187(sp)
-; ZVFHMIN32-NEXT:    lh a0, 756(sp)
-; ZVFHMIN32-NEXT:    lh a1, 500(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT:    feq.h t3, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t4
-; ZVFHMIN32-NEXT:    sb a0, 186(sp)
-; ZVFHMIN32-NEXT:    lh a0, 754(sp)
-; ZVFHMIN32-NEXT:    lh a1, 498(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT:    feq.h t4, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t2
-; ZVFHMIN32-NEXT:    sb a0, 185(sp)
-; ZVFHMIN32-NEXT:    lh a0, 752(sp)
-; ZVFHMIN32-NEXT:    lh a1, 496(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a4
-; ZVFHMIN32-NEXT:    feq.h t2, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t1
-; ZVFHMIN32-NEXT:    sb a0, 184(sp)
-; ZVFHMIN32-NEXT:    lh a0, 750(sp)
-; ZVFHMIN32-NEXT:    lh a1, 494(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s5
-; ZVFHMIN32-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t0
-; ZVFHMIN32-NEXT:    sb a0, 183(sp)
-; ZVFHMIN32-NEXT:    lh a0, 748(sp)
-; ZVFHMIN32-NEXT:    lh a1, 492(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s3
-; ZVFHMIN32-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a7
-; ZVFHMIN32-NEXT:    sb a0, 182(sp)
-; ZVFHMIN32-NEXT:    lh a0, 746(sp)
-; ZVFHMIN32-NEXT:    lh a1, 490(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s4
-; ZVFHMIN32-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a6
-; ZVFHMIN32-NEXT:    sb a0, 181(sp)
-; ZVFHMIN32-NEXT:    lh a0, 744(sp)
-; ZVFHMIN32-NEXT:    lh a1, 488(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN32-NEXT:    feq.h a6, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a5
-; ZVFHMIN32-NEXT:    vmv.x.s a1, v0
-; ZVFHMIN32-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 15
-; ZVFHMIN32-NEXT:    vmv.x.s a5, v8
-; ZVFHMIN32-NEXT:    sb a0, 180(sp)
-; ZVFHMIN32-NEXT:    lh a0, 742(sp)
-; ZVFHMIN32-NEXT:    lh a7, 486(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 179(sp)
-; ZVFHMIN32-NEXT:    lh a0, 740(sp)
-; ZVFHMIN32-NEXT:    lh a7, 484(sp)
-; ZVFHMIN32-NEXT:    sb a2, 140(sp)
-; ZVFHMIN32-NEXT:    sb t2, 141(sp)
-; ZVFHMIN32-NEXT:    sb t4, 142(sp)
-; ZVFHMIN32-NEXT:    sb t3, 143(sp)
-; ZVFHMIN32-NEXT:    sb a1, 136(sp)
-; ZVFHMIN32-NEXT:    sb a6, 137(sp)
-; ZVFHMIN32-NEXT:    sb a4, 138(sp)
-; ZVFHMIN32-NEXT:    sb a3, 139(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 178(sp)
-; ZVFHMIN32-NEXT:    lh a0, 638(sp)
-; ZVFHMIN32-NEXT:    lh a1, 382(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 14
-; ZVFHMIN32-NEXT:    vmv.x.s t3, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 255(sp)
-; ZVFHMIN32-NEXT:    lh a0, 636(sp)
-; ZVFHMIN32-NEXT:    lh a1, 380(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 13
-; ZVFHMIN32-NEXT:    vmv.x.s t2, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 254(sp)
-; ZVFHMIN32-NEXT:    lh a0, 634(sp)
-; ZVFHMIN32-NEXT:    lh a1, 378(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 12
-; ZVFHMIN32-NEXT:    vmv.x.s t1, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 253(sp)
-; ZVFHMIN32-NEXT:    lh a0, 632(sp)
-; ZVFHMIN32-NEXT:    lh a1, 376(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 11
-; ZVFHMIN32-NEXT:    vmv.x.s t0, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 252(sp)
-; ZVFHMIN32-NEXT:    lh a0, 630(sp)
-; ZVFHMIN32-NEXT:    lh a1, 374(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 10
-; ZVFHMIN32-NEXT:    vmv.x.s a7, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 251(sp)
-; ZVFHMIN32-NEXT:    lh a0, 628(sp)
-; ZVFHMIN32-NEXT:    lh a1, 372(sp)
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 9
-; ZVFHMIN32-NEXT:    vmv.x.s a6, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    lw a1, 108(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    sb a0, 250(sp)
-; ZVFHMIN32-NEXT:    lh a0, 626(sp)
-; ZVFHMIN32-NEXT:    lh a1, 370(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a5
-; ZVFHMIN32-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    lw a1, 112(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    sb a0, 249(sp)
-; ZVFHMIN32-NEXT:    lh a0, 624(sp)
-; ZVFHMIN32-NEXT:    lh a1, 368(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t3
-; ZVFHMIN32-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    lw a1, 116(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    sb a0, 248(sp)
-; ZVFHMIN32-NEXT:    lh a0, 622(sp)
-; ZVFHMIN32-NEXT:    lh a1, 366(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t2
-; ZVFHMIN32-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    lw a1, 120(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    sb a0, 247(sp)
-; ZVFHMIN32-NEXT:    lh a0, 620(sp)
-; ZVFHMIN32-NEXT:    lh a1, 364(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t1
-; ZVFHMIN32-NEXT:    feq.h a5, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    lw a1, 124(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN32-NEXT:    sb a0, 246(sp)
-; ZVFHMIN32-NEXT:    lh a0, 618(sp)
-; ZVFHMIN32-NEXT:    lh a1, 362(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, t0
-; ZVFHMIN32-NEXT:    feq.h t0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, s1
-; ZVFHMIN32-NEXT:    sb a0, 245(sp)
-; ZVFHMIN32-NEXT:    lh a0, 616(sp)
-; ZVFHMIN32-NEXT:    lh a1, 360(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN32-NEXT:    feq.h a7, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN32-NEXT:    sb a0, 244(sp)
-; ZVFHMIN32-NEXT:    lh a0, 614(sp)
-; ZVFHMIN32-NEXT:    lh a1, 358(sp)
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a6
-; ZVFHMIN32-NEXT:    feq.h a6, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN32-NEXT:    vslidedown.vi v8, v24, 8
-; ZVFHMIN32-NEXT:    vmv.x.s a1, v8
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    sb a0, 243(sp)
-; ZVFHMIN32-NEXT:    lh a0, 612(sp)
-; ZVFHMIN32-NEXT:    lh a1, 356(sp)
-; ZVFHMIN32-NEXT:    sb a5, 204(sp)
-; ZVFHMIN32-NEXT:    sb a2, 205(sp)
-; ZVFHMIN32-NEXT:    sb a3, 206(sp)
-; ZVFHMIN32-NEXT:    sb a4, 207(sp)
-; ZVFHMIN32-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a2, 200(sp)
-; ZVFHMIN32-NEXT:    sb a6, 201(sp)
-; ZVFHMIN32-NEXT:    sb a7, 202(sp)
-; ZVFHMIN32-NEXT:    sb t0, 203(sp)
-; ZVFHMIN32-NEXT:    li a2, 128
-; ZVFHMIN32-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN32-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN32-NEXT:    sb a0, 242(sp)
-; ZVFHMIN32-NEXT:    addi a0, sp, 128
-; ZVFHMIN32-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
-; ZVFHMIN32-NEXT:    vle8.v v8, (a0)
-; ZVFHMIN32-NEXT:    vand.vi v8, v8, 1
-; ZVFHMIN32-NEXT:    vmsne.vi v0, v8, 0
-; ZVFHMIN32-NEXT:    addi sp, s0, -912
-; ZVFHMIN32-NEXT:    .cfi_def_cfa sp, 912
-; ZVFHMIN32-NEXT:    lw ra, 908(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s0, 904(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s1, 900(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s2, 896(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s3, 892(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s4, 888(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s5, 884(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s6, 880(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s7, 876(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s8, 872(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s9, 868(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s10, 864(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    lw s11, 860(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT:    .cfi_restore ra
-; ZVFHMIN32-NEXT:    .cfi_restore s0
-; ZVFHMIN32-NEXT:    .cfi_restore s1
-; ZVFHMIN32-NEXT:    .cfi_restore s2
-; ZVFHMIN32-NEXT:    .cfi_restore s3
-; ZVFHMIN32-NEXT:    .cfi_restore s4
-; ZVFHMIN32-NEXT:    .cfi_restore s5
-; ZVFHMIN32-NEXT:    .cfi_restore s6
-; ZVFHMIN32-NEXT:    .cfi_restore s7
-; ZVFHMIN32-NEXT:    .cfi_restore s8
-; ZVFHMIN32-NEXT:    .cfi_restore s9
-; ZVFHMIN32-NEXT:    .cfi_restore s10
-; ZVFHMIN32-NEXT:    .cfi_restore s11
-; ZVFHMIN32-NEXT:    addi sp, sp, 912
-; ZVFHMIN32-NEXT:    .cfi_def_cfa_offset 0
-; ZVFHMIN32-NEXT:    ret
-;
-; ZVFHMIN64-LABEL: fcmp_oeq_vv_v128f16:
-; ZVFHMIN64:       # %bb.0:
-; ZVFHMIN64-NEXT:    addi sp, sp, -912
-; ZVFHMIN64-NEXT:    .cfi_def_cfa_offset 912
-; ZVFHMIN64-NEXT:    sd ra, 904(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s0, 896(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s1, 888(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s2, 880(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s3, 872(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s4, 864(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s5, 856(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s6, 848(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s7, 840(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s8, 832(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s9, 824(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s10, 816(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    sd s11, 808(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    .cfi_offset ra, -8
-; ZVFHMIN64-NEXT:    .cfi_offset s0, -16
-; ZVFHMIN64-NEXT:    .cfi_offset s1, -24
-; ZVFHMIN64-NEXT:    .cfi_offset s2, -32
-; ZVFHMIN64-NEXT:    .cfi_offset s3, -40
-; ZVFHMIN64-NEXT:    .cfi_offset s4, -48
-; ZVFHMIN64-NEXT:    .cfi_offset s5, -56
-; ZVFHMIN64-NEXT:    .cfi_offset s6, -64
-; ZVFHMIN64-NEXT:    .cfi_offset s7, -72
-; ZVFHMIN64-NEXT:    .cfi_offset s8, -80
-; ZVFHMIN64-NEXT:    .cfi_offset s9, -88
-; ZVFHMIN64-NEXT:    .cfi_offset s10, -96
-; ZVFHMIN64-NEXT:    .cfi_offset s11, -104
-; ZVFHMIN64-NEXT:    addi s0, sp, 912
-; ZVFHMIN64-NEXT:    .cfi_def_cfa s0, 0
-; ZVFHMIN64-NEXT:    csrr a1, vlenb
-; ZVFHMIN64-NEXT:    li a2, 29
-; ZVFHMIN64-NEXT:    mul a1, a1, a2
-; ZVFHMIN64-NEXT:    sub sp, sp, a1
-; ZVFHMIN64-NEXT:    andi sp, sp, -128
-; ZVFHMIN64-NEXT:    addi a1, a0, 128
-; ZVFHMIN64-NEXT:    li a2, 64
-; ZVFHMIN64-NEXT:    addi a3, sp, 640
-; ZVFHMIN64-NEXT:    addi a4, sp, 384
-; ZVFHMIN64-NEXT:    addi a5, sp, 512
-; ZVFHMIN64-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
-; ZVFHMIN64-NEXT:    vle16.v v0, (a0)
-; ZVFHMIN64-NEXT:    addi a0, sp, 256
-; ZVFHMIN64-NEXT:    vle16.v v24, (a1)
-; ZVFHMIN64-NEXT:    vse16.v v8, (a3)
-; ZVFHMIN64-NEXT:    vse16.v v0, (a4)
-; ZVFHMIN64-NEXT:    vse16.v v16, (a5)
-; ZVFHMIN64-NEXT:    vse16.v v24, (a0)
-; ZVFHMIN64-NEXT:    lh a0, 704(sp)
-; ZVFHMIN64-NEXT:    lh a1, 448(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 160(sp)
-; ZVFHMIN64-NEXT:    lh a0, 702(sp)
-; ZVFHMIN64-NEXT:    lh a1, 446(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 159(sp)
-; ZVFHMIN64-NEXT:    lh a0, 700(sp)
-; ZVFHMIN64-NEXT:    lh a1, 444(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 158(sp)
-; ZVFHMIN64-NEXT:    lh a0, 698(sp)
-; ZVFHMIN64-NEXT:    lh a1, 442(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 157(sp)
-; ZVFHMIN64-NEXT:    lh a0, 696(sp)
-; ZVFHMIN64-NEXT:    lh a1, 440(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 156(sp)
-; ZVFHMIN64-NEXT:    lh a0, 694(sp)
-; ZVFHMIN64-NEXT:    lh a1, 438(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 155(sp)
-; ZVFHMIN64-NEXT:    lh a0, 692(sp)
-; ZVFHMIN64-NEXT:    lh a1, 436(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 154(sp)
-; ZVFHMIN64-NEXT:    lh a0, 690(sp)
-; ZVFHMIN64-NEXT:    lh a1, 434(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 153(sp)
-; ZVFHMIN64-NEXT:    lh a0, 688(sp)
-; ZVFHMIN64-NEXT:    lh a1, 432(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 152(sp)
-; ZVFHMIN64-NEXT:    lh a0, 686(sp)
-; ZVFHMIN64-NEXT:    lh a1, 430(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 151(sp)
-; ZVFHMIN64-NEXT:    lh a0, 684(sp)
-; ZVFHMIN64-NEXT:    lh a1, 428(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 150(sp)
-; ZVFHMIN64-NEXT:    lh a0, 682(sp)
-; ZVFHMIN64-NEXT:    lh a1, 426(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 149(sp)
-; ZVFHMIN64-NEXT:    lh a0, 680(sp)
-; ZVFHMIN64-NEXT:    lh a1, 424(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 148(sp)
-; ZVFHMIN64-NEXT:    lh a0, 678(sp)
-; ZVFHMIN64-NEXT:    lh a1, 422(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 147(sp)
-; ZVFHMIN64-NEXT:    lh a0, 676(sp)
-; ZVFHMIN64-NEXT:    lh a1, 420(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 146(sp)
-; ZVFHMIN64-NEXT:    lh a0, 674(sp)
-; ZVFHMIN64-NEXT:    lh a1, 418(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a2
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 145(sp)
-; ZVFHMIN64-NEXT:    lh a0, 672(sp)
-; ZVFHMIN64-NEXT:    lh a1, 416(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a2, 128(sp)
-; ZVFHMIN64-NEXT:    sb a0, 144(sp)
-; ZVFHMIN64-NEXT:    lh a0, 576(sp)
-; ZVFHMIN64-NEXT:    lh a1, 320(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 224(sp)
-; ZVFHMIN64-NEXT:    lh a0, 574(sp)
-; ZVFHMIN64-NEXT:    lh a1, 318(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 223(sp)
-; ZVFHMIN64-NEXT:    lh a0, 572(sp)
-; ZVFHMIN64-NEXT:    lh a1, 316(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 222(sp)
-; ZVFHMIN64-NEXT:    lh a0, 570(sp)
-; ZVFHMIN64-NEXT:    lh a1, 314(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 221(sp)
-; ZVFHMIN64-NEXT:    lh a0, 568(sp)
-; ZVFHMIN64-NEXT:    lh a1, 312(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 220(sp)
-; ZVFHMIN64-NEXT:    lh a0, 566(sp)
-; ZVFHMIN64-NEXT:    lh a1, 310(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 219(sp)
-; ZVFHMIN64-NEXT:    lh a0, 564(sp)
-; ZVFHMIN64-NEXT:    lh a1, 308(sp)
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 7
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 28
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 6
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 27
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 5
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 26
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 4
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 25
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 3
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 24
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 2
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 23
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 1
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 22
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v10, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v4, v8, 15
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v8, 14
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v2, v8, 13
-; ZVFHMIN64-NEXT:    vslidedown.vi v30, v8, 12
-; ZVFHMIN64-NEXT:    vslidedown.vi v28, v8, 11
-; ZVFHMIN64-NEXT:    vslidedown.vi v26, v8, 10
-; ZVFHMIN64-NEXT:    vslidedown.vi v22, v8, 9
-; ZVFHMIN64-NEXT:    vslidedown.vi v20, v8, 8
-; ZVFHMIN64-NEXT:    vmv.x.s t5, v16
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 218(sp)
-; ZVFHMIN64-NEXT:    lh a0, 562(sp)
-; ZVFHMIN64-NEXT:    lh a1, 306(sp)
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v21, v16, 7
-; ZVFHMIN64-NEXT:    vslidedown.vi v31, v16, 6
-; ZVFHMIN64-NEXT:    vslidedown.vi v23, v16, 5
-; ZVFHMIN64-NEXT:    vslidedown.vi v27, v16, 4
-; ZVFHMIN64-NEXT:    vslidedown.vi v29, v16, 3
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v16, 2
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 19
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v16, 1
-; ZVFHMIN64-NEXT:    addi a2, sp, 800
-; ZVFHMIN64-NEXT:    vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v18, v16, 15
-; ZVFHMIN64-NEXT:    vslidedown.vi v14, v16, 14
-; ZVFHMIN64-NEXT:    vslidedown.vi v12, v16, 13
-; ZVFHMIN64-NEXT:    vslidedown.vi v10, v16, 12
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v16, 11
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v16, 10
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 20
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v16, 9
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 4
-; ZVFHMIN64-NEXT:    sub a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v16, v16, 8
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 13
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v16, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 217(sp)
-; ZVFHMIN64-NEXT:    lh a0, 560(sp)
-; ZVFHMIN64-NEXT:    lh a1, 304(sp)
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v3, v0, 7
-; ZVFHMIN64-NEXT:    vslidedown.vi v9, v0, 6
-; ZVFHMIN64-NEXT:    vslidedown.vi v15, v0, 5
-; ZVFHMIN64-NEXT:    vslidedown.vi v19, v0, 4
-; ZVFHMIN64-NEXT:    vslidedown.vi v11, v0, 3
-; ZVFHMIN64-NEXT:    vslidedown.vi v13, v0, 2
-; ZVFHMIN64-NEXT:    vslidedown.vi v16, v0, 1
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 15
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 1
-; ZVFHMIN64-NEXT:    add a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 14
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 3
-; ZVFHMIN64-NEXT:    sub a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 13
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 2
-; ZVFHMIN64-NEXT:    add a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 12
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 11
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 11
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 3
-; ZVFHMIN64-NEXT:    add a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 10
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 4
-; ZVFHMIN64-NEXT:    add a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
-; ZVFHMIN64-NEXT:    vslidedown.vi v6, v0, 9
-; ZVFHMIN64-NEXT:    vslidedown.vi v0, v0, 8
-; ZVFHMIN64-NEXT:    vmv.x.s t3, v4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 216(sp)
-; ZVFHMIN64-NEXT:    lh a0, 558(sp)
-; ZVFHMIN64-NEXT:    lh a1, 302(sp)
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v4, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s t4, v4
-; ZVFHMIN64-NEXT:    vmv.x.s t2, v2
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 215(sp)
-; ZVFHMIN64-NEXT:    lh a0, 556(sp)
-; ZVFHMIN64-NEXT:    lh a1, 300(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s t1, v30
-; ZVFHMIN64-NEXT:    vmv.x.s t0, v28
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 214(sp)
-; ZVFHMIN64-NEXT:    lh a0, 554(sp)
-; ZVFHMIN64-NEXT:    lh a1, 298(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a7, v26
-; ZVFHMIN64-NEXT:    vmv.x.s a6, v22
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 213(sp)
-; ZVFHMIN64-NEXT:    lh a0, 552(sp)
-; ZVFHMIN64-NEXT:    lh a1, 296(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a5, v20
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v18
-; ZVFHMIN64-NEXT:    sd a2, 88(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 212(sp)
-; ZVFHMIN64-NEXT:    lh a0, 550(sp)
-; ZVFHMIN64-NEXT:    lh a1, 294(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v14
-; ZVFHMIN64-NEXT:    sd a2, 96(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v12
-; ZVFHMIN64-NEXT:    sd a2, 104(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 211(sp)
-; ZVFHMIN64-NEXT:    lh t6, 548(sp)
-; ZVFHMIN64-NEXT:    lh s1, 292(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a0, v10
-; ZVFHMIN64-NEXT:    sd a0, 112(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    vmv.x.s a0, v8
-; ZVFHMIN64-NEXT:    sd a0, 120(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s1
-; ZVFHMIN64-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t6, 210(sp)
-; ZVFHMIN64-NEXT:    lh t6, 546(sp)
-; ZVFHMIN64-NEXT:    lh s1, 290(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    vmv.x.s t5, v24
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s1
-; ZVFHMIN64-NEXT:    feq.h t6, fa4, fa3
-; ZVFHMIN64-NEXT:    sb t6, 209(sp)
-; ZVFHMIN64-NEXT:    lh t6, 544(sp)
-; ZVFHMIN64-NEXT:    lh s1, 288(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t5
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s1
-; ZVFHMIN64-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t5, 192(sp)
-; ZVFHMIN64-NEXT:    sb t6, 208(sp)
-; ZVFHMIN64-NEXT:    lh t5, 738(sp)
-; ZVFHMIN64-NEXT:    lh t6, 482(sp)
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 28
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s7, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 27
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s5, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t5, 177(sp)
-; ZVFHMIN64-NEXT:    lh t5, 736(sp)
-; ZVFHMIN64-NEXT:    lh t6, 480(sp)
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 26
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s8, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 25
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s6, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t5, 176(sp)
-; ZVFHMIN64-NEXT:    lh t5, 734(sp)
-; ZVFHMIN64-NEXT:    lh t6, 478(sp)
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 24
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s4, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 23
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s3, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t5, 175(sp)
-; ZVFHMIN64-NEXT:    lh t5, 732(sp)
-; ZVFHMIN64-NEXT:    lh t6, 476(sp)
-; ZVFHMIN64-NEXT:    csrr a0, vlenb
-; ZVFHMIN64-NEXT:    li a1, 22
-; ZVFHMIN64-NEXT:    mul a0, a0, a1
-; ZVFHMIN64-NEXT:    add a0, sp, a0
-; ZVFHMIN64-NEXT:    lh s2, 800(a0) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s s1, v21
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t6
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    sb t5, 174(sp)
-; ZVFHMIN64-NEXT:    lh s9, 730(sp)
-; ZVFHMIN64-NEXT:    lh s10, 474(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s t6, v31
-; ZVFHMIN64-NEXT:    vmv.x.s t5, v23
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN64-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN64-NEXT:    sb s9, 173(sp)
-; ZVFHMIN64-NEXT:    lh s9, 728(sp)
-; ZVFHMIN64-NEXT:    lh s10, 472(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s11, v3
-; ZVFHMIN64-NEXT:    vmv.x.s ra, v9
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN64-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN64-NEXT:    sb s9, 172(sp)
-; ZVFHMIN64-NEXT:    lh s9, 726(sp)
-; ZVFHMIN64-NEXT:    lh s10, 470(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v15
-; ZVFHMIN64-NEXT:    vmv.x.s a3, v19
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s10
-; ZVFHMIN64-NEXT:    feq.h s9, fa5, fa4
-; ZVFHMIN64-NEXT:    sb s9, 171(sp)
-; ZVFHMIN64-NEXT:    lh s9, 724(sp)
-; ZVFHMIN64-NEXT:    lh a0, 468(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a4, v11
-; ZVFHMIN64-NEXT:    vmv.x.s s10, v13
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s9
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 170(sp)
-; ZVFHMIN64-NEXT:    lh a0, 722(sp)
-; ZVFHMIN64-NEXT:    lh a1, 466(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s9, v16
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s7
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 169(sp)
-; ZVFHMIN64-NEXT:    lh a0, 720(sp)
-; ZVFHMIN64-NEXT:    lh a1, 464(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s5
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s8
-; ZVFHMIN64-NEXT:    fmv.h.x fa2, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa1, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa2, fa1
-; ZVFHMIN64-NEXT:    sb a0, 168(sp)
-; ZVFHMIN64-NEXT:    lh a0, 718(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa2, s6
-; ZVFHMIN64-NEXT:    lh a1, 462(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa1, s11
-; ZVFHMIN64-NEXT:    fmv.h.x fa0, a0
-; ZVFHMIN64-NEXT:    feq.h s5, fa5, fa1
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa0, fa5
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, ra
-; ZVFHMIN64-NEXT:    sb a0, 167(sp)
-; ZVFHMIN64-NEXT:    lh a0, 716(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa1, a2
-; ZVFHMIN64-NEXT:    lh a1, 460(sp)
-; ZVFHMIN64-NEXT:    feq.h a2, fa4, fa5
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    feq.h a0, fa3, fa1
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s4
-; ZVFHMIN64-NEXT:    sb a1, 166(sp)
-; ZVFHMIN64-NEXT:    lh a1, 714(sp)
-; ZVFHMIN64-NEXT:    lh s4, 458(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT:    feq.h a3, fa2, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s4
-; ZVFHMIN64-NEXT:    feq.h a1, fa4, fa3
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s3
-; ZVFHMIN64-NEXT:    sb a1, 165(sp)
-; ZVFHMIN64-NEXT:    lh a1, 712(sp)
-; ZVFHMIN64-NEXT:    lh s3, 456(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a4
-; ZVFHMIN64-NEXT:    feq.h a4, fa5, fa3
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s3
-; ZVFHMIN64-NEXT:    feq.h a1, fa5, fa3
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s2
-; ZVFHMIN64-NEXT:    sb a1, 164(sp)
-; ZVFHMIN64-NEXT:    lh a1, 710(sp)
-; ZVFHMIN64-NEXT:    lh s2, 454(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s10
-; ZVFHMIN64-NEXT:    feq.h s3, fa4, fa3
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, s2
-; ZVFHMIN64-NEXT:    feq.h a1, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a1, 163(sp)
-; ZVFHMIN64-NEXT:    lh a1, 708(sp)
-; ZVFHMIN64-NEXT:    lh s2, 452(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s9
-; ZVFHMIN64-NEXT:    feq.h s4, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN64-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a1, 162(sp)
-; ZVFHMIN64-NEXT:    lh a1, 706(sp)
-; ZVFHMIN64-NEXT:    lh s2, 450(sp)
-; ZVFHMIN64-NEXT:    sb s4, 129(sp)
-; ZVFHMIN64-NEXT:    sb s3, 130(sp)
-; ZVFHMIN64-NEXT:    sb a4, 131(sp)
-; ZVFHMIN64-NEXT:    sb a3, 132(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN64-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 133(sp)
-; ZVFHMIN64-NEXT:    sb a2, 134(sp)
-; ZVFHMIN64-NEXT:    sb s5, 135(sp)
-; ZVFHMIN64-NEXT:    sb a1, 161(sp)
-; ZVFHMIN64-NEXT:    lh a0, 610(sp)
-; ZVFHMIN64-NEXT:    lh a1, 354(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s5, v27
-; ZVFHMIN64-NEXT:    vmv.x.s s4, v29
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 241(sp)
-; ZVFHMIN64-NEXT:    lh a0, 608(sp)
-; ZVFHMIN64-NEXT:    lh a1, 352(sp)
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 19
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    lh s3, 800(a2) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    lh s2, 800(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 240(sp)
-; ZVFHMIN64-NEXT:    lh a0, 606(sp)
-; ZVFHMIN64-NEXT:    lh a1, 350(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s1
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 7
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 239(sp)
-; ZVFHMIN64-NEXT:    lh a0, 604(sp)
-; ZVFHMIN64-NEXT:    lh a1, 348(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 6
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 238(sp)
-; ZVFHMIN64-NEXT:    lh a0, 602(sp)
-; ZVFHMIN64-NEXT:    lh a1, 346(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a3, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 5
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 237(sp)
-; ZVFHMIN64-NEXT:    lh a0, 600(sp)
-; ZVFHMIN64-NEXT:    lh a1, 344(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a4, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 4
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 236(sp)
-; ZVFHMIN64-NEXT:    lh a0, 598(sp)
-; ZVFHMIN64-NEXT:    lh a1, 342(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s6, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 3
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 235(sp)
-; ZVFHMIN64-NEXT:    lh a0, 596(sp)
-; ZVFHMIN64-NEXT:    lh a1, 340(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s7, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 2
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 234(sp)
-; ZVFHMIN64-NEXT:    lh a0, 594(sp)
-; ZVFHMIN64-NEXT:    lh a1, 338(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s s8, v8
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 1
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa4, fa3
-; ZVFHMIN64-NEXT:    sb a0, 233(sp)
-; ZVFHMIN64-NEXT:    lh a0, 592(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT:    lh a1, 336(sp)
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa3, a0
-; ZVFHMIN64-NEXT:    feq.h s1, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa3, fa5
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN64-NEXT:    sb a0, 232(sp)
-; ZVFHMIN64-NEXT:    lh a0, 590(sp)
-; ZVFHMIN64-NEXT:    lh a1, 334(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT:    feq.h t6, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    sb a0, 231(sp)
-; ZVFHMIN64-NEXT:    lh a0, 588(sp)
-; ZVFHMIN64-NEXT:    lh a1, 332(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a4
-; ZVFHMIN64-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s5
-; ZVFHMIN64-NEXT:    sb a0, 230(sp)
-; ZVFHMIN64-NEXT:    lh a0, 586(sp)
-; ZVFHMIN64-NEXT:    lh a1, 330(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s6
-; ZVFHMIN64-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s4
-; ZVFHMIN64-NEXT:    sb a0, 229(sp)
-; ZVFHMIN64-NEXT:    lh a0, 584(sp)
-; ZVFHMIN64-NEXT:    lh a1, 328(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s7
-; ZVFHMIN64-NEXT:    feq.h t5, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s3
-; ZVFHMIN64-NEXT:    sb a0, 228(sp)
-; ZVFHMIN64-NEXT:    lh a0, 582(sp)
-; ZVFHMIN64-NEXT:    lh a1, 326(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s8
-; ZVFHMIN64-NEXT:    feq.h s3, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s2
-; ZVFHMIN64-NEXT:    sb a0, 227(sp)
-; ZVFHMIN64-NEXT:    lh a0, 580(sp)
-; ZVFHMIN64-NEXT:    lh a1, 324(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 226(sp)
-; ZVFHMIN64-NEXT:    lh a0, 578(sp)
-; ZVFHMIN64-NEXT:    lh a1, 322(sp)
-; ZVFHMIN64-NEXT:    sb a2, 193(sp)
-; ZVFHMIN64-NEXT:    sb s3, 194(sp)
-; ZVFHMIN64-NEXT:    sb t5, 195(sp)
-; ZVFHMIN64-NEXT:    sb a4, 196(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a3, 197(sp)
-; ZVFHMIN64-NEXT:    sb t6, 198(sp)
-; ZVFHMIN64-NEXT:    sb s1, 199(sp)
-; ZVFHMIN64-NEXT:    sb a0, 225(sp)
-; ZVFHMIN64-NEXT:    lh a0, 766(sp)
-; ZVFHMIN64-NEXT:    lh a1, 510(sp)
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 20
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s s1, v8
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 4
-; ZVFHMIN64-NEXT:    sub a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s t5, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 191(sp)
-; ZVFHMIN64-NEXT:    lh a0, 764(sp)
-; ZVFHMIN64-NEXT:    lh a1, 508(sp)
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    li a3, 13
-; ZVFHMIN64-NEXT:    mul a2, a2, a3
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s t6, v8
-; ZVFHMIN64-NEXT:    csrr a2, vlenb
-; ZVFHMIN64-NEXT:    slli a3, a2, 1
-; ZVFHMIN64-NEXT:    add a2, a3, a2
-; ZVFHMIN64-NEXT:    add a2, sp, a2
-; ZVFHMIN64-NEXT:    addi a2, a2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s a2, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 190(sp)
-; ZVFHMIN64-NEXT:    lh a0, 762(sp)
-; ZVFHMIN64-NEXT:    lh a1, 506(sp)
-; ZVFHMIN64-NEXT:    csrr a3, vlenb
-; ZVFHMIN64-NEXT:    slli a4, a3, 3
-; ZVFHMIN64-NEXT:    sub a3, a4, a3
-; ZVFHMIN64-NEXT:    add a3, sp, a3
-; ZVFHMIN64-NEXT:    addi a3, a3, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s a3, v8
-; ZVFHMIN64-NEXT:    csrr a4, vlenb
-; ZVFHMIN64-NEXT:    slli s2, a4, 2
-; ZVFHMIN64-NEXT:    add a4, s2, a4
-; ZVFHMIN64-NEXT:    add a4, sp, a4
-; ZVFHMIN64-NEXT:    addi a4, a4, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (a4) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s a4, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 189(sp)
-; ZVFHMIN64-NEXT:    lh a0, 760(sp)
-; ZVFHMIN64-NEXT:    lh a1, 504(sp)
-; ZVFHMIN64-NEXT:    csrr s2, vlenb
-; ZVFHMIN64-NEXT:    li s3, 11
-; ZVFHMIN64-NEXT:    mul s2, s2, s3
-; ZVFHMIN64-NEXT:    add s2, sp, s2
-; ZVFHMIN64-NEXT:    addi s2, s2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s s5, v8
-; ZVFHMIN64-NEXT:    csrr s2, vlenb
-; ZVFHMIN64-NEXT:    slli s3, s2, 3
-; ZVFHMIN64-NEXT:    add s2, s3, s2
-; ZVFHMIN64-NEXT:    add s2, sp, s2
-; ZVFHMIN64-NEXT:    addi s2, s2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s s3, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 188(sp)
-; ZVFHMIN64-NEXT:    lh a0, 758(sp)
-; ZVFHMIN64-NEXT:    lh a1, 502(sp)
-; ZVFHMIN64-NEXT:    csrr s2, vlenb
-; ZVFHMIN64-NEXT:    slli s4, s2, 4
-; ZVFHMIN64-NEXT:    add s2, s4, s2
-; ZVFHMIN64-NEXT:    add s2, sp, s2
-; ZVFHMIN64-NEXT:    addi s2, s2, 800
-; ZVFHMIN64-NEXT:    vl2r.v v8, (s2) # vscale x 16-byte Folded Reload
-; ZVFHMIN64-NEXT:    vmv.x.s s4, v8
-; ZVFHMIN64-NEXT:    vmv.x.s s2, v6
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t3
-; ZVFHMIN64-NEXT:    sb a0, 187(sp)
-; ZVFHMIN64-NEXT:    lh a0, 756(sp)
-; ZVFHMIN64-NEXT:    lh a1, 500(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT:    feq.h t3, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t4
-; ZVFHMIN64-NEXT:    sb a0, 186(sp)
-; ZVFHMIN64-NEXT:    lh a0, 754(sp)
-; ZVFHMIN64-NEXT:    lh a1, 498(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT:    feq.h t4, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t2
-; ZVFHMIN64-NEXT:    sb a0, 185(sp)
-; ZVFHMIN64-NEXT:    lh a0, 752(sp)
-; ZVFHMIN64-NEXT:    lh a1, 496(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a4
-; ZVFHMIN64-NEXT:    feq.h t2, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t1
-; ZVFHMIN64-NEXT:    sb a0, 184(sp)
-; ZVFHMIN64-NEXT:    lh a0, 750(sp)
-; ZVFHMIN64-NEXT:    lh a1, 494(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s5
-; ZVFHMIN64-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t0
-; ZVFHMIN64-NEXT:    sb a0, 183(sp)
-; ZVFHMIN64-NEXT:    lh a0, 748(sp)
-; ZVFHMIN64-NEXT:    lh a1, 492(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s3
-; ZVFHMIN64-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a7
-; ZVFHMIN64-NEXT:    sb a0, 182(sp)
-; ZVFHMIN64-NEXT:    lh a0, 746(sp)
-; ZVFHMIN64-NEXT:    lh a1, 490(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s4
-; ZVFHMIN64-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a6
-; ZVFHMIN64-NEXT:    sb a0, 181(sp)
-; ZVFHMIN64-NEXT:    lh a0, 744(sp)
-; ZVFHMIN64-NEXT:    lh a1, 488(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, s2
-; ZVFHMIN64-NEXT:    feq.h a6, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a5
-; ZVFHMIN64-NEXT:    vmv.x.s a1, v0
-; ZVFHMIN64-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 15
-; ZVFHMIN64-NEXT:    vmv.x.s a5, v8
-; ZVFHMIN64-NEXT:    sb a0, 180(sp)
-; ZVFHMIN64-NEXT:    lh a0, 742(sp)
-; ZVFHMIN64-NEXT:    lh a7, 486(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a1, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 179(sp)
-; ZVFHMIN64-NEXT:    lh a0, 740(sp)
-; ZVFHMIN64-NEXT:    lh a7, 484(sp)
-; ZVFHMIN64-NEXT:    sb a2, 140(sp)
-; ZVFHMIN64-NEXT:    sb t2, 141(sp)
-; ZVFHMIN64-NEXT:    sb t4, 142(sp)
-; ZVFHMIN64-NEXT:    sb t3, 143(sp)
-; ZVFHMIN64-NEXT:    sb a1, 136(sp)
-; ZVFHMIN64-NEXT:    sb a6, 137(sp)
-; ZVFHMIN64-NEXT:    sb a4, 138(sp)
-; ZVFHMIN64-NEXT:    sb a3, 139(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 178(sp)
-; ZVFHMIN64-NEXT:    lh a0, 638(sp)
-; ZVFHMIN64-NEXT:    lh a1, 382(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 14
-; ZVFHMIN64-NEXT:    vmv.x.s t3, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 255(sp)
-; ZVFHMIN64-NEXT:    lh a0, 636(sp)
-; ZVFHMIN64-NEXT:    lh a1, 380(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 13
-; ZVFHMIN64-NEXT:    vmv.x.s t2, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 254(sp)
-; ZVFHMIN64-NEXT:    lh a0, 634(sp)
-; ZVFHMIN64-NEXT:    lh a1, 378(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 12
-; ZVFHMIN64-NEXT:    vmv.x.s t1, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 253(sp)
-; ZVFHMIN64-NEXT:    lh a0, 632(sp)
-; ZVFHMIN64-NEXT:    lh a1, 376(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 11
-; ZVFHMIN64-NEXT:    vmv.x.s t0, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 252(sp)
-; ZVFHMIN64-NEXT:    lh a0, 630(sp)
-; ZVFHMIN64-NEXT:    lh a1, 374(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 10
-; ZVFHMIN64-NEXT:    vmv.x.s a7, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 251(sp)
-; ZVFHMIN64-NEXT:    lh a0, 628(sp)
-; ZVFHMIN64-NEXT:    lh a1, 372(sp)
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 9
-; ZVFHMIN64-NEXT:    vmv.x.s a6, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    ld a1, 88(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    sb a0, 250(sp)
-; ZVFHMIN64-NEXT:    lh a0, 626(sp)
-; ZVFHMIN64-NEXT:    lh a1, 370(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a5
-; ZVFHMIN64-NEXT:    feq.h a4, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    ld a1, 96(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    sb a0, 249(sp)
-; ZVFHMIN64-NEXT:    lh a0, 624(sp)
-; ZVFHMIN64-NEXT:    lh a1, 368(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t3
-; ZVFHMIN64-NEXT:    feq.h a3, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    ld a1, 104(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    sb a0, 248(sp)
-; ZVFHMIN64-NEXT:    lh a0, 622(sp)
-; ZVFHMIN64-NEXT:    lh a1, 366(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t2
-; ZVFHMIN64-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    ld a1, 112(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    sb a0, 247(sp)
-; ZVFHMIN64-NEXT:    lh a0, 620(sp)
-; ZVFHMIN64-NEXT:    lh a1, 364(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t1
-; ZVFHMIN64-NEXT:    feq.h a5, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    ld a1, 120(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a1
-; ZVFHMIN64-NEXT:    sb a0, 246(sp)
-; ZVFHMIN64-NEXT:    lh a0, 618(sp)
-; ZVFHMIN64-NEXT:    lh a1, 362(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, t0
-; ZVFHMIN64-NEXT:    feq.h t0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, s1
-; ZVFHMIN64-NEXT:    sb a0, 245(sp)
-; ZVFHMIN64-NEXT:    lh a0, 616(sp)
-; ZVFHMIN64-NEXT:    lh a1, 360(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a7
-; ZVFHMIN64-NEXT:    feq.h a7, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t5
-; ZVFHMIN64-NEXT:    sb a0, 244(sp)
-; ZVFHMIN64-NEXT:    lh a0, 614(sp)
-; ZVFHMIN64-NEXT:    lh a1, 358(sp)
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a6
-; ZVFHMIN64-NEXT:    feq.h a6, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, t6
-; ZVFHMIN64-NEXT:    vslidedown.vi v8, v24, 8
-; ZVFHMIN64-NEXT:    vmv.x.s a1, v8
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    sb a0, 243(sp)
-; ZVFHMIN64-NEXT:    lh a0, 612(sp)
-; ZVFHMIN64-NEXT:    lh a1, 356(sp)
-; ZVFHMIN64-NEXT:    sb a5, 204(sp)
-; ZVFHMIN64-NEXT:    sb a2, 205(sp)
-; ZVFHMIN64-NEXT:    sb a3, 206(sp)
-; ZVFHMIN64-NEXT:    sb a4, 207(sp)
-; ZVFHMIN64-NEXT:    feq.h a2, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a2, 200(sp)
-; ZVFHMIN64-NEXT:    sb a6, 201(sp)
-; ZVFHMIN64-NEXT:    sb a7, 202(sp)
-; ZVFHMIN64-NEXT:    sb t0, 203(sp)
-; ZVFHMIN64-NEXT:    li a2, 128
-; ZVFHMIN64-NEXT:    fmv.h.x fa5, a0
-; ZVFHMIN64-NEXT:    fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT:    feq.h a0, fa5, fa4
-; ZVFHMIN64-NEXT:    sb a0, 242(sp)
-; ZVFHMIN64-NEXT:    addi a0, sp, 128
-; ZVFHMIN64-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
-; ZVFHMIN64-NEXT:    vle8.v v8, (a0)
-; ZVFHMIN64-NEXT:    vand.vi v8, v8, 1
-; ZVFHMIN64-NEXT:    vmsne.vi v0, v8, 0
-; ZVFHMIN64-NEXT:    addi sp, s0, -912
-; ZVFHMIN64-NEXT:    .cfi_def_cfa sp, 912
-; ZVFHMIN64-NEXT:    ld ra, 904(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s0, 896(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s1, 888(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s2, 880(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s3, 872(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s4, 864(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s5, 856(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s6, 848(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s7, 840(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s8, 832(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s9, 824(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s10, 816(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    ld s11, 808(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT:    .cfi_restore ra
-; ZVFHMIN64-NEXT:    .cfi_restore s0
-; ZVFHMIN64-NEXT:    .cfi_restore s1
-; ZVFHMIN64-NEXT:    .cfi_restore s2
-; ZVFHMIN64-NEXT:    .cfi_restore s3
-; ZVFHMIN64-NEXT:    .cfi_restore s4
-; ZVFHMIN64-NEXT:    .cfi_restore s5
-; ZVFHMIN64-NEXT:    .cfi_restore s6
-; ZVFHMIN64-NEXT:    .cfi_restore s7
-; ZVFHMIN64-NEXT:    .cfi_restore s8
-; ZVFHMIN64-NEXT:    .cfi_restore s9
-; ZVFHMIN64-NEXT:    .cfi_restore s10
-; ZVFHMIN64-NEXT:    .cfi_restore s11
-; ZVFHMIN64-NEXT:    addi sp, sp, 912
-; ZVFHMIN64-NEXT:    .cfi_def_cfa_offset 0
-; ZVFHMIN64-NEXT:    ret
+; ZVFHMIN-LABEL: fcmp_oeq_vv_v128f16:
+; ZVFHMIN:       # %bb.0:
+; ZVFHMIN-NEXT:    addi sp, sp, -16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    li a2, 25
+; ZVFHMIN-NEXT:    mul a1, a1, a2
+; ZVFHMIN-NEXT:    sub sp, sp, a1
+; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a2, a1, 4
+; ZVFHMIN-NEXT:    add a1, a2, a1
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    li a1, 64
+; ZVFHMIN-NEXT:    addi a2, a0, 128
+; ZVFHMIN-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vle16.v v0, (a2)
+; ZVFHMIN-NEXT:    addi a1, sp, 16
+; ZVFHMIN-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a1, a0, 3
+; ZVFHMIN-NEXT:    add a0, a1, a0
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT:    li a0, 32
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v0
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfeq.vv v7, v8, v24
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a1, a1, 3
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vs1r.v v7, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a2, a1, 4
+; ZVFHMIN-NEXT:    add a1, a2, a1
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a2, a1, 3
+; ZVFHMIN-NEXT:    add a1, a2, a1
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v0
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v24
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v8, v16, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT:    addi a1, sp, 16
+; ZVFHMIN-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v8, v8, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfeq.vv v7, v16, v24
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a2, a1, 4
+; ZVFHMIN-NEXT:    add a1, a2, a1
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v8, v8, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT:    csrr a1, vlenb
+; ZVFHMIN-NEXT:    slli a2, a1, 3
+; ZVFHMIN-NEXT:    add a1, a2, a1
+; ZVFHMIN-NEXT:    add a1, sp, a1
+; ZVFHMIN-NEXT:    addi a1, a1, 16
+; ZVFHMIN-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT:    vslidedown.vx v8, v8, a0
+; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT:    vmfeq.vv v8, v16, v24
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    slli a0, a0, 3
+; ZVFHMIN-NEXT:    add a0, sp, a0
+; ZVFHMIN-NEXT:    addi a0, a0, 16
+; ZVFHMIN-NEXT:    vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v9, v7, 4
+; ZVFHMIN-NEXT:    vslideup.vi v0, v8, 4
+; ZVFHMIN-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; ZVFHMIN-NEXT:    vslideup.vi v0, v9, 8
+; ZVFHMIN-NEXT:    csrr a0, vlenb
+; ZVFHMIN-NEXT:    li a1, 25
+; ZVFHMIN-NEXT:    mul a0, a0, a1
+; ZVFHMIN-NEXT:    add sp, sp, a0
+; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
+; ZVFHMIN-NEXT:    addi sp, sp, 16
+; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
+; ZVFHMIN-NEXT:    ret
   %v = call <128 x i1> @llvm.vp.fcmp.v128f16(<128 x half> %va, <128 x half> %vb, metadata !"oeq", <128 x i1> %m, i32 %evl)
   ret <128 x i1> %v
 }
@@ -3882,6 +1724,79 @@ define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x
   %v = call <32 x i1> @llvm.vp.fcmp.v32f64(<32 x double> %va, <32 x double> %vb, metadata !"oeq", <32 x i1> %m, i32 %evl)
   ret <32 x i1> %v
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; ZVFH32: {{.*}}
-; ZVFH64: {{.*}}
+
+define <8 x i1> @fcmp_oeq_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: fcmp_oeq_vv_v8bf16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vmfeq.vv v0, v12, v10
+; CHECK-NEXT:    ret
+  %v = call <8 x i1> @llvm.vp.fcmp.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, metadata !"oeq", <8 x i1> %m, i32 %evl)
+  ret <8 x i1> %v
+}
+
+define <32 x i1> @fcmp_oeq_vv_v32bf16(<32 x bfloat> %va, <32 x bfloat> %vb, <32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: fcmp_oeq_vv_v32bf16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v12
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vmfeq.vv v0, v24, v16
+; CHECK-NEXT:    ret
+  %v = call <32 x i1> @llvm.vp.fcmp.v32bf16(<32 x bfloat> %va, <32 x bfloat> %vb, metadata !"oeq", <32 x i1> %m, i32 %evl)
+  ret <32 x i1> %v
+}
+
+define <64 x i1> @fcmp_oeq_vv_v64bf16(<64 x bfloat> %va, <64 x bfloat> %vb, <64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: fcmp_oeq_vv_v64bf16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 4
+; CHECK-NEXT:    sub sp, sp, a0
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT:    vslidedown.vx v24, v16, a0
+; CHECK-NEXT:    addi a1, sp, 16
+; CHECK-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT:    vslidedown.vx v0, v8, a0
+; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    addi a0, a0, 16
+; CHECK-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT:    addi a0, sp, 16
+; CHECK-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v24
+; CHECK-NEXT:    vmv4r.v v24, v0
+; CHECK-NEXT:    vfwcvtbf16.f.f.v v0, v24
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vmfeq.vv v24, v0, v8
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    addi a0, a0, 16
+; CHECK-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT:    vmfeq.vv v0, v16, v8
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslideup.vi v0, v24, 4
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    slli a0, a0, 4
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa sp, 16
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %v = call <64 x i1> @llvm.vp.fcmp.v64bf16(<64 x bfloat> %va, <64 x bfloat> %vb, metadata !"oeq", <64 x i1> %m, i32 %evl)
+  ret <64 x i1> %v
+}


        
