[llvm] [DAGCombine] Relax restriction on (bswap shl(x, c)) combine (PR #193679)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

We can still do the
(bswap shl(x,c)) -> (zext(bswap(trunc(shl(x,sub(c,bw/2))))))
combine if the shift amount is a multiple of 8 not just 16.

https://alive2.llvm.org/ce/z/crnSB6

---
Full diff: https://github.com/llvm/llvm-project/pull/193679.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+1-1) 
- (modified) llvm/test/CodeGen/X86/combine-bswap.ll (+20) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d1c7e668a2604..48b48c3a23d65 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12102,7 +12102,7 @@ SDValue DAGCombiner::visitBSWAP(SDNode *N) {
     EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2);
     if (ShAmt && ShAmt->getAPIntValue().ult(BW) &&
         ShAmt->getZExtValue() >= (BW / 2) &&
-        (ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) &&
+        (ShAmt->getZExtValue() % 8) == 0 && TLI.isTypeLegal(HalfVT) &&
         TLI.isTruncateFree(VT, HalfVT) &&
         (!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) {
       SDValue Res = N0.getOperand(0);
diff --git a/llvm/test/CodeGen/X86/combine-bswap.ll b/llvm/test/CodeGen/X86/combine-bswap.ll
index 1f074c877f3ae..0a40c61c79719 100644
--- a/llvm/test/CodeGen/X86/combine-bswap.ll
+++ b/llvm/test/CodeGen/X86/combine-bswap.ll
@@ -236,6 +236,26 @@ define i64 @test_bswap64_shift48(i64 %a0) {
   ret i64 %b
 }
 
+define i64 @test_bswap64_shift40(i64 %a0) {
+; X86-LABEL: test_bswap64_shift40:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    bswapl %eax
+; X86-NEXT:    shrl $8, %eax
+; X86-NEXT:    xorl %edx, %edx
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_bswap64_shift40:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    bswapl %eax
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    retq
+  %s = shl i64 %a0, 40
+  %b = call i64 @llvm.bswap.i64(i64 %s)
+  ret i64 %b
+}
+
 define i32 @test_bswap32_shift17(i32 %a0) {
 ; X86-LABEL: test_bswap32_shift17:
 ; X86:       # %bb.0:

``````````

</details>


https://github.com/llvm/llvm-project/pull/193679