[llvm] ed2f5f4 - AMDGPU: Skip last corrections in afn f64 reciprocal (#183696)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 22 13:59:50 PDT 2026
Author: Matt Arsenault
Date: 2026-04-22T21:59:45+01:00
New Revision: ed2f5f42ee266d16334291498780178c16d70c95
URL: https://github.com/llvm/llvm-project/commit/ed2f5f42ee266d16334291498780178c16d70c95
DIFF: https://github.com/llvm/llvm-project/commit/ed2f5f42ee266d16334291498780178c16d70c95.diff
LOG: AMDGPU: Skip last corrections in afn f64 reciprocal (#183696)
Device libs has a fast reciprocal macro that is close
to the fast division expansion, but skips the last terms
compared to the full division.
The basic reciprocal handling has identical output to this
macro. The negative reciprocal case has different fneg placement
and smaller code size, but I believe should be the same.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
llvm/test/CodeGen/AMDGPU/rsq.f64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 4e956db103188..5fc7e22b5feee 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -5495,12 +5495,21 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(MachineInstr &MI,
if (!AllowInaccurateRcp)
return false;
- auto NegY = B.buildFNeg(ResTy, Y);
+ const ConstantFP *CLHS = getConstantFPVRegVal(X, MRI);
+ bool IsNegRcp = CLHS && CLHS->isExactlyValue(-1.0);
+
+ // Pull out the negation so it folds for free into the source modifiers.
+ if (IsNegRcp)
+ X = B.buildFConstant(ResTy, 1.0).getReg(0);
+
+ Register NegY = IsNegRcp ? Y : B.buildFNeg(ResTy, Y).getReg(0);
auto One = B.buildFConstant(ResTy, 1.0);
auto R = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy})
.addUse(Y)
.setMIFlags(Flags);
+ if (IsNegRcp)
+ R = B.buildFNeg(ResTy, R);
auto Tmp0 = B.buildFMA(ResTy, NegY, R, One);
R = B.buildFMA(ResTy, Tmp0, R, R);
@@ -5508,6 +5517,13 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(MachineInstr &MI,
auto Tmp1 = B.buildFMA(ResTy, NegY, R, One);
R = B.buildFMA(ResTy, Tmp1, R, R);
+ // Skip the last 2 correction terms for reciprocal.
+ if (IsNegRcp || (CLHS && CLHS->isExactlyValue(1.0))) {
+ B.buildCopy(Res, R);
+ MI.eraseFromParent();
+ return true;
+ }
+
auto Ret = B.buildFMul(ResTy, X, R);
auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 8bb072a9626a9..f08e12a7fbf31 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -13029,15 +13029,30 @@ SDValue SITargetLowering::lowerFastUnsafeFDIV64(SDValue Op,
if (!AllowInaccurateDiv)
return SDValue();
- SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y);
+ const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(X);
+ bool IsNegRcp = CLHS && CLHS->isExactlyValue(-1.0);
+
+ // Pull out the negation so it folds for free into the source modifiers.
+ if (IsNegRcp)
+ X = DAG.getConstantFP(1.0, SL, VT);
+
+ SDValue NegY = IsNegRcp ? Y : DAG.getNode(ISD::FNEG, SL, VT, Y);
SDValue One = DAG.getConstantFP(1.0, SL, VT);
SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y);
+ if (IsNegRcp)
+ R = DAG.getNode(ISD::FNEG, SL, VT, R);
+
SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One);
R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R);
SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One);
R = DAG.getNode(ISD::FMA, SL, VT, Tmp1, R, R);
+
+ // Skip the last 2 correction terms for reciprocal.
+ if (IsNegRcp || (CLHS && CLHS->isExactlyValue(1.0)))
+ return R;
+
SDValue Ret = DAG.getNode(ISD::FMUL, SL, VT, X, R);
SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X);
return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
index 74f99d5ba7bb1..958dd4cce4424 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
@@ -438,8 +438,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; GCN-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GCN-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -450,8 +448,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GFX10-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GFX10-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GFX10-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -464,9 +460,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
@@ -475,6 +468,43 @@ define double @v_rcp_f64_arcp_afn(double %x) {
ret double %fdiv
}
+define double @v_neg_rcp_f64_afn(double %x) {
+; GCN-LABEL: v_neg_rcp_f64_afn:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_neg_rcp_f64_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GFX10-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_neg_rcp_f64_afn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fdiv = fdiv afn double -1.0, %x
+ ret double %fdiv
+}
+
define double @v_rcp_f64_ulp25(double %x) {
; GFX6-LABEL: v_rcp_f64_ulp25:
; GFX6: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
index 11476a6aa862e..96dc7caa5b2ed 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
@@ -57,8 +57,6 @@ define double @v_fdiv_f64_afn(double %x, double %y) #0 {
; GCN: v_rcp_f64_e32 v[2:3], v[0:1]
; GCN: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GCN: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GCN: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GCN: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GCN: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GCN: s_setpc_b64
@@ -67,6 +65,18 @@ define double @v_rcp_f64_afn(double %x) #0 {
ret double %result
}
+; GCN-LABEL: {{^}}v_neg_rcp_f64_afn:
+; GCN: v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GCN: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GCN: s_setpc_b64
+define double @v_neg_rcp_f64_afn(double %x) #0 {
+ %result = fdiv afn double -1.0, %x
+ ret double %result
+}
+
; GCN-LABEL: {{^}}fdiv_f64_s_v:
define amdgpu_kernel void @fdiv_f64_s_v(ptr addrspace(1) %out, ptr addrspace(1) %in, double %num) #0 {
%den = load double, ptr addrspace(1) %in
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index e1fef9083e132..3cbde439cdf99 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -721,8 +721,6 @@ define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %t
; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; SI-NEXT: s_brev_b32 s3, 1
@@ -744,8 +742,6 @@ define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %t
; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_brev_b32 s3, 1
; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
index 130de84a9407d..58cac9e3c8cf3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
@@ -145,8 +145,6 @@ define amdgpu_kernel void @rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
; SI: v_fma_f64
; SI: v_fma_f64
; SI: v_fma_f64
-; SI: v_fma_f64
-; SI: v_fma_f64
define amdgpu_kernel void @unsafe_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
%rcp = fdiv afn double 1.0, %src
store double %rcp, ptr addrspace(1) %out, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
index d7a5ce43b85ab..e10846f41da9a 100644
--- a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
@@ -3782,8 +3782,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3817,8 +3815,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3852,8 +3848,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3887,8 +3881,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3984,8 +3976,6 @@ define double @v_rsq_f64__afn(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4008,8 +3998,6 @@ define double @v_rsq_f64__afn(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4032,8 +4020,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4056,8 +4042,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4151,13 +4135,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4176,12 +4157,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4200,13 +4179,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4225,12 +4201,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract afn double @llvm.sqrt.f64(double %x)
%rsq = fdiv contract afn double -1.0, %sqrt
@@ -4307,8 +4281,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4330,8 +4302,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4353,8 +4323,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4376,8 +4344,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4473,8 +4439,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4497,8 +4461,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4521,8 +4483,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4545,8 +4505,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4625,8 +4583,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4648,8 +4604,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4671,8 +4625,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4694,8 +4646,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4772,13 +4722,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4796,12 +4743,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4819,13 +4764,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4843,12 +4785,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract afn nnan ninf double @llvm.sqrt.f64(double %x)
%rsq = fdiv contract afn nnan ninf double -1.0, %sqrt
@@ -5179,10 +5119,6 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; SI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
; SI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[6:7]
@@ -5262,10 +5198,6 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[11:12], -v[2:3], v[7:8], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[9:10], v[5:6], v[5:6]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[11:12], v[7:8], v[7:8]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[4:5]
@@ -5417,8 +5349,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5444,8 +5374,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5471,8 +5399,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5498,8 +5424,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5604,8 +5528,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5628,8 +5550,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5652,8 +5572,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5676,8 +5594,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
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