[llvm] 59596d7 - [AArch64][GlobalISel] Add hadd-combine globalisel test coverage. NFC (#193591)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 22 13:54:29 PDT 2026
Author: David Green
Date: 2026-04-22T21:54:24+01:00
New Revision: 59596d789eacd059a3f9aaaebad5dde173398b6a
URL: https://github.com/llvm/llvm-project/commit/59596d789eacd059a3f9aaaebad5dde173398b6a
DIFF: https://github.com/llvm/llvm-project/commit/59596d789eacd059a3f9aaaebad5dde173398b6a.diff
LOG: [AArch64][GlobalISel] Add hadd-combine globalisel test coverage. NFC (#193591)
Added:
Modified:
llvm/test/CodeGen/AArch64/hadd-combine.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/hadd-combine.ll b/llvm/test/CodeGen/AArch64/hadd-combine.ll
index f288741d8908c..6496d4bdedfa4 100644
--- a/llvm/test/CodeGen/AArch64/hadd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/hadd-combine.ll
@@ -1,11 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <8 x i16> @haddu_base(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: haddu_base:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_base:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_base:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> %src2 to <8 x i32>
%add = add <8 x i32> %zextsrc1, %zextsrc2
@@ -15,11 +24,20 @@ define <8 x i16> @haddu_base(<8 x i16> %src1, <8 x i16> %src2) {
}
define <8 x i16> @haddu_const(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_const:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_const:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -28,11 +46,20 @@ define <8 x i16> @haddu_const(<8 x i16> %src1) {
}
define <8 x i16> @haddu_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -41,13 +68,22 @@ define <8 x i16> @haddu_const_lhs(<8 x i16> %src1) {
}
define <8 x i16> @haddu_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: shrn v0.4h, v1.4s, #1
-; CHECK-NEXT: shrn2 v0.8h, v2.4s, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-SD-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -67,10 +103,19 @@ define <8 x i16> @haddu_const_both() {
}
define <8 x i16> @haddu_const_bothhigh() {
-; CHECK-LABEL: haddu_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mvni v0.8h, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mvni v0.8h, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff
+; CHECK-GI-NEXT: mvni v1.4h, #1
+; CHECK-GI-NEXT: uaddl v1.4s, v1.4h, v0.4h
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%ext1 = zext <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> to <8 x i32>
%ext2 = zext <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535> to <8 x i32>
%add = add <8 x i32> %ext1, %ext2
@@ -80,13 +125,22 @@ define <8 x i16> @haddu_const_bothhigh() {
}
define <8 x i16> @haddu_undef(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: shrn v0.4h, v1.4s, #1
-; CHECK-NEXT: shrn2 v0.8h, v2.4s, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-SD-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> undef to <8 x i32>
%add = add <8 x i32> %zextsrc2, %zextsrc1
@@ -117,47 +171,78 @@ define <8 x i16> @haddu_i_const(<8 x i16> %src1) {
}
define <8 x i16> @haddu_i_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_i_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_i_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_i_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: uhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @haddu_i_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: haddu_i_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushr v0.8h, v0.8h, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_i_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_i_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: uhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @haddu_i_const_both() {
-; CHECK-LABEL: haddu_i_const_both:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.8h, #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_i_const_both:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.8h, #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_i_const_both:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.8h, #3
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result
}
define <8 x i16> @haddu_i_const_bothhigh() {
-; CHECK-LABEL: haddu_i_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mvni v0.8h, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_i_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mvni v0.8h, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_i_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: mvni v1.8h, #1
+; CHECK-GI-NEXT: uhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>)
ret <8 x i16> %result
}
define <8 x i16> @haddu_i_undef(<8 x i16> %t, <8 x i16> %src1) {
-; CHECK-LABEL: haddu_i_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_i_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_i_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> undef, <8 x i16> %src1)
ret <8 x i16> %result
}
@@ -167,10 +252,18 @@ define <8 x i16> @haddu_i_undef(<8 x i16> %t, <8 x i16> %src1) {
define <8 x i16> @hadds_base(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: hadds_base:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_base:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_base:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> %src2 to <8 x i32>
%add = add <8 x i32> %zextsrc1, %zextsrc2
@@ -180,11 +273,20 @@ define <8 x i16> @hadds_base(<8 x i16> %src1, <8 x i16> %src2) {
}
define <8 x i16> @hadds_const(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_const:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_const:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -193,11 +295,20 @@ define <8 x i16> @hadds_const(<8 x i16> %src1) {
}
define <8 x i16> @hadds_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -206,13 +317,22 @@ define <8 x i16> @hadds_const_lhs(<8 x i16> %src1) {
}
define <8 x i16> @hadds_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: shrn v0.4h, v1.4s, #1
-; CHECK-NEXT: shrn2 v0.8h, v2.4s, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-SD-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add = add <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -232,11 +352,21 @@ define <8 x i16> @hadds_const_both() {
}
define <8 x i16> @hadds_const_bothhigh() {
-; CHECK-LABEL: hadds_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #32766 // =0x7ffe
-; CHECK-NEXT: dup v0.8h, w8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #32766 // =0x7ffe
+; CHECK-SD-NEXT: dup v0.8h, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI19_0
+; CHECK-GI-NEXT: mvni v0.4h, #128, lsl #8
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI19_0]
+; CHECK-GI-NEXT: saddl v1.4s, v1.4h, v0.4h
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%ext1 = sext <8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> to <8 x i32>
%ext2 = sext <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> to <8 x i32>
%add = add <8 x i32> %ext1, %ext2
@@ -246,13 +376,22 @@ define <8 x i16> @hadds_const_bothhigh() {
}
define <8 x i16> @hadds_undef(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
-; CHECK-NEXT: shrn v0.4h, v1.4s, #1
-; CHECK-NEXT: shrn2 v0.8h, v2.4s, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-SD-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> undef to <8 x i32>
%add = add <8 x i32> %zextsrc2, %zextsrc1
@@ -283,57 +422,97 @@ define <8 x i16> @hadds_i_const(<8 x i16> %src1) {
}
define <8 x i16> @hadds_i_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_i_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_i_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_i_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: shadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @hadds_i_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: hadds_i_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v0.8h, v0.8h, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_i_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_i_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: shadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @hadds_i_const_both() {
-; CHECK-LABEL: hadds_i_const_both:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.8h, #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_i_const_both:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.8h, #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_i_const_both:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.8h, #3
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result
}
define <8 x i16> @hadds_i_const_bothhigh() {
-; CHECK-LABEL: hadds_i_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #32766 // =0x7ffe
-; CHECK-NEXT: dup v0.8h, w8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_i_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #32766 // =0x7ffe
+; CHECK-SD-NEXT: dup v0.8h, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_i_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI26_0
+; CHECK-GI-NEXT: mvni v0.8h, #128, lsl #8
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]
+; CHECK-GI-NEXT: shadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)
ret <8 x i16> %result
}
define <8 x i16> @hadds_i_undef(<8 x i16> %t, <8 x i16> %src1) {
-; CHECK-LABEL: hadds_i_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_i_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_i_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> undef, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @sub_fixedwidth_v4i32(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: sub_fixedwidth_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sub_fixedwidth_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sub_fixedwidth_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v2.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ushr v1.8h, v2.8h, #1
+; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%or = or <8 x i16> %a0, %a1
%xor = xor <8 x i16> %a0, %a1
%srl = lshr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -342,10 +521,18 @@ define <8 x i16> @sub_fixedwidth_v4i32(<8 x i16> %a0, <8 x i16> %a1) {
}
define <8 x i16> @srhadd_fixedwidth_v8i16(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: srhadd_fixedwidth_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_fixedwidth_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_fixedwidth_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v2.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: sshr v1.8h, v2.8h, #1
+; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%or = or <8 x i16> %a0, %a1
%xor = xor <8 x i16> %a0, %a1
%srl = ashr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -354,10 +541,21 @@ define <8 x i16> @srhadd_fixedwidth_v8i16(<8 x i16> %a0, <8 x i16> %a1) {
}
define <8 x i16> @rhaddu_base(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: rhaddu_base:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_base:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_base:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: uaddl v3.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v0.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> %src2 to <8 x i32>
%add1 = add <8 x i32> %zextsrc1, %zextsrc2
@@ -368,11 +566,20 @@ define <8 x i16> @rhaddu_base(<8 x i16> %src1, <8 x i16> %src2) {
}
define <8 x i16> @rhaddu_const(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_const:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_const:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #2
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -382,11 +589,22 @@ define <8 x i16> @rhaddu_const(<8 x i16> %src1) {
}
define <8 x i16> @rhaddu_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: uaddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v2.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -396,11 +614,23 @@ define <8 x i16> @rhaddu_const_lhs(<8 x i16> %src1) {
}
define <8 x i16> @rhaddu_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: uaddw v3.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -422,10 +652,21 @@ define <8 x i16> @rhaddu_const_both() {
}
define <8 x i16> @rhaddu_const_bothhigh() {
-; CHECK-LABEL: rhaddu_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff
+; CHECK-GI-NEXT: mvni v1.4h, #1
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: uaddl v0.4s, v1.4h, v0.4h
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%ext1 = zext <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> to <8 x i32>
%ext2 = zext <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535> to <8 x i32>
%add1 = add <8 x i32> %ext1, %ext2
@@ -436,11 +677,23 @@ define <8 x i16> @rhaddu_const_bothhigh() {
}
define <8 x i16> @rhaddu_undef(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: uaddw v3.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> undef to <8 x i32>
%add1 = add <8 x i32> %zextsrc2, %zextsrc1
@@ -472,48 +725,79 @@ define <8 x i16> @rhaddu_i_const(<8 x i16> %src1) {
}
define <8 x i16> @rhaddu_i_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_i_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_i_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_i_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: urhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @rhaddu_i_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_i_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_i_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_i_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: urhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @rhaddu_i_const_both() {
-; CHECK-LABEL: rhaddu_i_const_both:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.8h, #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_i_const_both:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.8h, #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_i_const_both:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.8h, #3
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result
}
define <8 x i16> @rhaddu_i_const_bothhigh() {
-; CHECK-LABEL: rhaddu_i_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_i_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_i_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: mvni v1.8h, #1
+; CHECK-GI-NEXT: urhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>)
ret <8 x i16> %result
}
define <8 x i16> @rhaddu_i_undef(<8 x i16> %t, <8 x i16> %src1) {
-; CHECK-LABEL: rhaddu_i_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_i_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_i_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> undef, <8 x i16> %src1)
ret <8 x i16> %result
}
@@ -523,10 +807,21 @@ define <8 x i16> @rhaddu_i_undef(<8 x i16> %t, <8 x i16> %src1) {
define <8 x i16> @rhadds_base(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: rhadds_base:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_base:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_base:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: saddl v3.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v0.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> %src2 to <8 x i32>
%add1 = add <8 x i32> %zextsrc1, %zextsrc2
@@ -537,11 +832,20 @@ define <8 x i16> @rhadds_base(<8 x i16> %src1, <8 x i16> %src2) {
}
define <8 x i16> @rhadds_const(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_const:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_const:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_const:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #2
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v1.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -551,11 +855,22 @@ define <8 x i16> @rhadds_const(<8 x i16> %src1) {
}
define <8 x i16> @rhadds_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #1
+; CHECK-GI-NEXT: saddw v2.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v2.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: shrn v0.4h, v2.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -565,11 +880,23 @@ define <8 x i16> @rhadds_const_lhs(<8 x i16> %src1) {
}
define <8 x i16> @rhadds_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: saddw v3.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add1 = add <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -591,10 +918,22 @@ define <8 x i16> @rhadds_const_both() {
}
define <8 x i16> @rhadds_const_bothhigh() {
-; CHECK-LABEL: rhadds_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mvni v0.8h, #128, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mvni v0.8h, #128, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI49_0
+; CHECK-GI-NEXT: mvni v0.4h, #128, lsl #8
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI49_0]
+; CHECK-GI-NEXT: saddl v0.4s, v1.4h, v0.4h
+; CHECK-GI-NEXT: add v1.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v1.4s, #1
+; CHECK-GI-NEXT: ret
%ext1 = sext <8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> to <8 x i32>
%ext2 = sext <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> to <8 x i32>
%add1 = add <8 x i32> %ext1, %ext2
@@ -605,11 +944,23 @@ define <8 x i16> @rhadds_const_bothhigh() {
}
define <8 x i16> @rhadds_undef(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: saddw v3.4s, v1.4s, v0.4h
+; CHECK-GI-NEXT: saddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-GI-NEXT: add v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: shrn v0.4h, v1.4s, #1
+; CHECK-GI-NEXT: shrn2 v0.8h, v2.4s, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> undef to <8 x i32>
%add1 = add <8 x i32> %zextsrc2, %zextsrc1
@@ -641,249 +992,409 @@ define <8 x i16> @rhadds_i_const(<8 x i16> %src1) {
}
define <8 x i16> @rhadds_i_const_lhs(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_i_const_lhs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.8h, #1
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_i_const_lhs:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.8h, #1
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_i_const_lhs:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: srhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @rhadds_i_const_zero(<8 x i16> %src1) {
-; CHECK-LABEL: rhadds_i_const_zero:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_i_const_zero:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_i_const_zero:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: srhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i16> @rhadds_i_const_both() {
-; CHECK-LABEL: rhadds_i_const_both:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.8h, #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_i_const_both:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.8h, #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_i_const_both:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v0.8h, #3
+; CHECK-GI-NEXT: movi v1.8h, #1
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result
}
define <8 x i16> @rhadds_i_const_bothhigh() {
-; CHECK-LABEL: rhadds_i_const_bothhigh:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mvni v0.8h, #128, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_i_const_bothhigh:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mvni v0.8h, #128, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_i_const_bothhigh:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI56_0
+; CHECK-GI-NEXT: mvni v0.8h, #128, lsl #8
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI56_0]
+; CHECK-GI-NEXT: srhadd v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)
ret <8 x i16> %result
}
define <8 x i16> @rhadds_i_undef(<8 x i16> %t, <8 x i16> %src1) {
-; CHECK-LABEL: rhadds_i_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadds_i_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadds_i_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> undef, <8 x i16> %src1)
ret <8 x i16> %result
}
define <8 x i8> @shadd_v8i8(<8 x i8> %x) {
-; CHECK-LABEL: shadd_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @shadd_v4i16(<4 x i16> %x) {
-; CHECK-LABEL: shadd_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @shadd_v2i32(<2 x i32> %x) {
-; CHECK-LABEL: shadd_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.2s, v0.2s, v0.2s
+; CHECK-GI-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @shadd_v16i8(<16 x i8> %x) {
-; CHECK-LABEL: shadd_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.16b, v0.16b, v0.16b
+; CHECK-GI-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @shadd_v8i16(<8 x i16> %x) {
-; CHECK-LABEL: shadd_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v0.8h
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @shadd_v4i32(<4 x i32> %x) {
-; CHECK-LABEL: shadd_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shadd v0.4s, v0.4s, v0.4s
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @uhadd_v8i8(<8 x i8> %x) {
-; CHECK-LABEL: uhadd_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @uhadd_v4i16(<4 x i16> %x) {
-; CHECK-LABEL: uhadd_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @uhadd_v2i32(<2 x i32> %x) {
-; CHECK-LABEL: uhadd_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.2s, v0.2s, v0.2s
+; CHECK-GI-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @uhadd_v16i8(<16 x i8> %x) {
-; CHECK-LABEL: uhadd_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.16b, v0.16b, v0.16b
+; CHECK-GI-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @uhadd_v8i16(<8 x i16> %x) {
-; CHECK-LABEL: uhadd_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v0.8h
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @uhadd_v4i32(<4 x i32> %x) {
-; CHECK-LABEL: uhadd_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uhadd v0.4s, v0.4s, v0.4s
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @srhadd_v8i8(<8 x i8> %x) {
-; CHECK-LABEL: srhadd_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @srhadd_v4i16(<4 x i16> %x) {
-; CHECK-LABEL: srhadd_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @srhadd_v2i32(<2 x i32> %x) {
-; CHECK-LABEL: srhadd_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.2s, v0.2s, v0.2s
+; CHECK-GI-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @srhadd_v16i8(<16 x i8> %x) {
-; CHECK-LABEL: srhadd_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.16b, v0.16b, v0.16b
+; CHECK-GI-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @srhadd_v8i16(<8 x i16> %x) {
-; CHECK-LABEL: srhadd_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v0.8h
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @srhadd_v4i32(<4 x i32> %x) {
-; CHECK-LABEL: srhadd_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: srhadd v0.4s, v0.4s, v0.4s
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @urhadd_v8i8(<8 x i8> %x) {
-; CHECK-LABEL: urhadd_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @urhadd_v4i16(<4 x i16> %x) {
-; CHECK-LABEL: urhadd_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @urhadd_v2i32(<2 x i32> %x) {
-; CHECK-LABEL: urhadd_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.2s, v0.2s, v0.2s
+; CHECK-GI-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @urhadd_v16i8(<16 x i8> %x) {
-; CHECK-LABEL: urhadd_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.16b, v0.16b, v0.16b
+; CHECK-GI-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @urhadd_v8i16(<8 x i16> %x) {
-; CHECK-LABEL: urhadd_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v0.8h
+; CHECK-GI-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
-; CHECK-LABEL: urhadd_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: urhadd v0.4s, v0.4s, v0.4s
+; CHECK-GI-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i16> @uhadd_fixedwidth_v4i32(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: uhadd_fixedwidth_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uhadd_fixedwidth_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uhadd_fixedwidth_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v2.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: usra v2.8h, v0.8h, #1
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%and = and <8 x i16> %a0, %a1
%xor = xor <8 x i16> %a0, %a1
%srl = lshr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -892,10 +1403,18 @@ define <8 x i16> @uhadd_fixedwidth_v4i32(<8 x i16> %a0, <8 x i16> %a1) {
}
define <8 x i16> @shadd_fixedwidth_v8i16(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: shadd_fixedwidth_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_fixedwidth_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_fixedwidth_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v2.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ssra v2.8h, v0.8h, #1
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%and = and <8 x i16> %a0, %a1
%xor = xor <8 x i16> %a0, %a1
%srl = ashr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -957,13 +1476,25 @@ define <8 x i16> @urhadd_demandedelts(<8 x i16> %a0, <8 x i16> %a1) {
; Remove unnecessary sign_extend_inreg after shadd
define <2 x i32> @shadd_signbits_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) {
-; CHECK-LABEL: shadd_signbits_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v0.2s, v0.2s, #17
-; CHECK-NEXT: sshr v1.2s, v1.2s, #17
-; CHECK-NEXT: shadd v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shadd_signbits_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-SD-NEXT: shadd v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shadd_signbits_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-GI-NEXT: and v2.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ssra v2.2s, v0.2s, #1
+; CHECK-GI-NEXT: shl v0.2s, v2.2s, #17
+; CHECK-GI-NEXT: str d2, [x0]
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: ret
%x0 = ashr <2 x i32> %a0, <i32 17, i32 17>
%x1 = ashr <2 x i32> %a1, <i32 17, i32 17>
%m = and <2 x i32> %x0, %x1
@@ -978,13 +1509,26 @@ define <2 x i32> @shadd_signbits_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) {
; Remove unnecessary sign_extend_inreg after srhadd
define <2 x i32> @srhadd_signbits_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) {
-; CHECK-LABEL: srhadd_signbits_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v0.2s, v0.2s, #17
-; CHECK-NEXT: sshr v1.2s, v1.2s, #17
-; CHECK-NEXT: srhadd v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_signbits_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-SD-NEXT: srhadd v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_signbits_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-GI-NEXT: eor v2.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: sshr v1.2s, v2.2s, #1
+; CHECK-GI-NEXT: sub v1.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: shl v0.2s, v1.2s, #17
+; CHECK-GI-NEXT: str d1, [x0]
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: ret
%x0 = ashr <2 x i32> %a0, <i32 17, i32 17>
%x1 = ashr <2 x i32> %a1, <i32 17, i32 17>
%m = or <2 x i32> %x0, %x1
@@ -999,15 +1543,28 @@ define <2 x i32> @srhadd_signbits_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) {
; negative test - not enough signbits to remove sign_extend_inreg after srhadd
define <2 x i32> @srhadd_signbits_v2i32_negative(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) {
-; CHECK-LABEL: srhadd_signbits_v2i32_negative:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v0.2s, v0.2s, #17
-; CHECK-NEXT: sshr v1.2s, v1.2s, #17
-; CHECK-NEXT: srhadd v1.2s, v0.2s, v1.2s
-; CHECK-NEXT: shl v0.2s, v1.2s, #22
-; CHECK-NEXT: str d1, [x0]
-; CHECK-NEXT: sshr v0.2s, v0.2s, #22
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_signbits_v2i32_negative:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-SD-NEXT: srhadd v1.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: shl v0.2s, v1.2s, #22
+; CHECK-SD-NEXT: str d1, [x0]
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #22
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_signbits_v2i32_negative:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #17
+; CHECK-GI-NEXT: eor v2.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: sshr v1.2s, v2.2s, #1
+; CHECK-GI-NEXT: sub v1.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: shl v0.2s, v1.2s, #22
+; CHECK-GI-NEXT: str d1, [x0]
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #22
+; CHECK-GI-NEXT: ret
%x0 = ashr <2 x i32> %a0, <i32 17, i32 17>
%x1 = ashr <2 x i32> %a1, <i32 17, i32 17>
%m = or <2 x i32> %x0, %x1
@@ -1021,13 +1578,26 @@ define <2 x i32> @srhadd_signbits_v2i32_negative(<2 x i32> %a0, <2 x i32> %a1, p
}
define <8 x i8> @dontcrashonnvcasts() {
-; CHECK-LABEL: dontcrashonnvcasts:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2s, #128, lsl #24
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: fneg d0, d0
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: dontcrashonnvcasts:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2s, #128, lsl #24
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-SD-NEXT: fneg d0, d0
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: dontcrashonnvcasts:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d0, #0000000000000000
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: adrp x8, .LCPI91_0
+; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI91_0]
+; CHECK-GI-NEXT: mov v0.b[2], wzr
+; CHECK-GI-NEXT: urhadd v1.8b, v2.8b, v1.8b
+; CHECK-GI-NEXT: mov v0.b[4], wzr
+; CHECK-GI-NEXT: mov v0.b[6], wzr
+; CHECK-GI-NEXT: uzp1 v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
%vrhadd_v.i = tail call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> <i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 0>, <8 x i8> zeroinitializer)
%shuffle.i = shufflevector <8 x i8> %vrhadd_v.i, <8 x i8> <i8 0, i8 poison, i8 0, i8 poison, i8 0, i8 poison, i8 0, i8 poison>, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
ret <8 x i8> %shuffle.i
More information about the llvm-commits
mailing list