[llvm] verify scc is not live-in (PR #193143)
Zeng Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 22 11:49:07 PDT 2026
https://github.com/zwu-2025 updated https://github.com/llvm/llvm-project/pull/193143
>From b82604a1a8dd8aeddf5bcf39b1e8764b02e3571f Mon Sep 17 00:00:00 2001
From: zwu-2025 <Zeng.Wu2 at amd.com>
Date: Wed, 22 Apr 2026 04:28:08 +0000
Subject: [PATCH] verify scc not live-in
---
.../llvm/CodeGen/MachineRegisterInfo.h | 2 +-
.../include/llvm/CodeGen/TargetRegisterInfo.h | 3 +
llvm/lib/CodeGen/MachineVerifier.cpp | 7 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 41 ++++++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 6 +
llvm/test/CodeGen/AMDGPU/early-term.mir | 8 +-
.../AMDGPU/finalize-isel-kill-scc-vcc.mir | 4 +-
llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir | 122 ++++++++++--------
...ate-branch-lowering-preserve-loop-info.mir | 3 +-
.../CodeGen/AMDGPU/si-lower-wwm-copies.mir | 4 +-
llvm/test/CodeGen/AMDGPU/wait-xcnt.mir | 40 ++++--
11 files changed, 163 insertions(+), 77 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 737b74ef3f761..b67ffe183876f 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -197,7 +197,7 @@ class MachineRegisterInfo {
// register has a single defining instruction.
//
// The TwoAddressInstructionPass and PHIElimination passes take the machine
- // function out of SSA form when they introduce multiple defs per virtual
+ // function oout of SSA form when they introduce multiple defs per virtual
// register.
bool isSSA() const { return MF->getProperties().hasIsSSA(); }
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 5902fcdfcf172..329e7a4f7c847 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1290,6 +1290,9 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
// Whether this register should be ignored when generating CodeView debug
// info, because it's a known there is no mapping available.
virtual bool isIgnoredCVReg(MCRegister LLVMReg) const { return false; }
+
+ /// return true if the physical register can be a live-in register.
+ virtual bool cannotBeLiveInDuringSSA(MCRegister Reg) const { return false; }
};
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e5b145bb82c71..5f56402ab7259 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -893,6 +893,13 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
regsLive.clear();
if (MRI->tracksLiveness()) {
for (const auto &LI : MBB->liveins()) {
+ if (MRI->isSSA() && LI.PhysReg.isPhysical() &&
+ TRI->cannotBeLiveInDuringSSA(LI.PhysReg)) {
+ report("This physical register cannot be a live-in during SSA form",
+ MBB);
+ StringRef RegName = TRI->getRegAsmName(LI.PhysReg);
+ OS << "Register Name is " << RegName << "\n";
+ }
if (!LI.PhysReg.isPhysical()) {
report("MBB live-in list contains non-physical register", MBB);
continue;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 544aca0458975..7e207c62f6599 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -37,6 +37,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/PseudoSourceValueManager.h"
#include "llvm/CodeGen/SDPatternMatch.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicInst.h"
@@ -5009,6 +5010,46 @@ SITargetLowering::splitKillBlock(MachineInstr &MI,
MachineBasicBlock *BB) const {
MachineBasicBlock *SplitBB = BB->splitAt(MI, /*UpdateLiveIns=*/true);
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
+
+ if (SplitBB->isLiveIn(AMDGPU::SCC)) {
+ const GCNSubtarget &ST = BB->getParent()->getSubtarget<GCNSubtarget>();
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+ DebugLoc DL = MI.getDebugLoc();
+ // Insert a COPY from SCC from the last instruction which defines SCC in
+ // `BB`
+ bool Inserted = false;
+ Register SCCCopy;
+ for (auto I = BB->rbegin(), E = BB->rend(); I != E; ++I) {
+ if (I->isDebugInstr())
+ continue;
+
+ if (I->isCall()) {
+ // $scc is caller saved register, so if it is clobbered, we ingore it since the value of $scc is not a useful one.
+ continue;
+ }
+ if (I->definesRegister(AMDGPU::SCC, TRI)) {
+ SCCCopy = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0_XEXECRegClass);
+ // const TargetRegisterClass *RC =
+ // TRI->getAllocatableClass(&AMDGPU::SCC_CLASSRegClass); SCCCopy =
+ // MRI.createVirtualRegister(RC);
+ BuildMI(*BB, std::next(I->getIterator()), DL,
+ TII->get(TargetOpcode::COPY), SCCCopy)
+ .addReg(AMDGPU::SCC);
+ Inserted = true;
+ break;
+ }
+ }
+
+ assert(Inserted);
+ // Copy back to $scc in the SplitBB
+ BuildMI(*SplitBB, SplitBB->getFirstNonPHI(), DL,
+ TII->get(TargetOpcode::COPY), AMDGPU::SCC)
+ .addReg(SCCCopy, RegState::Kill);
+ // Now remove the scc from the livein of splitBB
+ SplitBB->removeLiveIn(AMDGPU::SCC);
+ }
+
MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
return SplitBB;
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 9d1a9eae75020..931af7f2aa012 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -18,6 +18,7 @@
#define GET_REGINFO_HEADER
#include "AMDGPUGenRegisterInfo.inc"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
@@ -497,6 +498,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
? 2.0
: 1.0);
}
+
+ /// return true if the physical register can be a live-in register.
+ bool cannotBeLiveInDuringSSA(MCRegister Reg) const override {
+ return Reg == AMDGPU::SCC;
+ }
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/early-term.mir b/llvm/test/CodeGen/AMDGPU/early-term.mir
index 2c43a15a109a7..c3279e07f8db7 100644
--- a/llvm/test/CodeGen/AMDGPU/early-term.mir
+++ b/llvm/test/CodeGen/AMDGPU/early-term.mir
@@ -1,8 +1,8 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -run-pass=phi-node-elimination,si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=si-late-branch-lowering %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=phi-node-elimination,si-late-branch-lowering %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
--- |
define amdgpu_ps void @early_term_scc0_end_block() {
diff --git a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
index c33ed34e8cb40..7c47db1538f28 100644
--- a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
@@ -21,12 +21,14 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY [[V_CNDMASK_B32_e64_]]
; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: S_CMP_LG_U32 [[COPY]], killed [[S_MOV_B32_3]], implicit-def $scc
+ ; CHECK-NEXT: [[SCCCOPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
; CHECK-NEXT: SI_KILL_F32_COND_IMM_TERMINATOR [[V_ADD_F32_e64_]], 0, 2, implicit-def $vcc_lo, implicit $exec
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $vcc_lo, $scc
+ ; CHECK-NEXT: liveins: $vcc_lo
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: scc = COPY killed [[SCCCOPY]]
; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
; CHECK-NEXT: S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
index 7e81b78ac378c..2c6bc24d04df1 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
@@ -11,7 +11,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_multiuse
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -22,7 +22,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_3]], %bb.0, %13.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_2]], %bb.0, %13.sub1, %bb.1
@@ -32,6 +31,7 @@ body: |
; GFX908-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -44,7 +44,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_multiuse
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -55,7 +55,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.0, %13.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %13.sub1, %bb.1
@@ -65,6 +64,7 @@ body: |
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -74,20 +74,21 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%0:sgpr_32 = COPY $sgpr0
%1:vgpr_32 = COPY %0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
-
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %1, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %1, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %1, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -110,7 +111,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_multiuse_agprtuple
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0_sgpr1, $scc
+ ; GFX908-NEXT: liveins: $sgpr0_sgpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]]
@@ -119,12 +120,12 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:areg_64_align2 = PHI [[COPY3]], %bb.0, %9.sub0_sub1, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:areg_64_align2 = PHI [[COPY2]], %bb.0, %9.sub2_sub3, %bb.1
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vreg_64_align2 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]].sub0, %subreg.sub0, [[COPY5]].sub1, %subreg.sub1, [[COPY4]].sub0, %subreg.sub2, [[COPY4]].sub1, %subreg.sub3
; GFX908-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B64_e32_1:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -137,7 +138,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_multiuse_agprtuple
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0_sgpr1, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0_sgpr1
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[COPY]]
@@ -146,12 +147,12 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:areg_64_align2 = PHI [[COPY3]], %bb.0, %9.sub0_sub1, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:areg_64_align2 = PHI [[COPY2]], %bb.0, %9.sub2_sub3, %bb.1
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vreg_64_align2 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]].sub0, %subreg.sub0, [[COPY5]].sub1, %subreg.sub1, [[COPY4]].sub0, %subreg.sub2, [[COPY4]].sub1, %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B64_e32_1:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -162,17 +163,19 @@ body: |
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
successors: %bb.1
- liveins: $sgpr0_sgpr1, $scc
+ liveins: $sgpr0_sgpr1
%0:sgpr_64 = COPY $sgpr0_sgpr1
%1:vreg_64_align2 = COPY %0:sgpr_64
bb.1:
successors: %bb.1, %bb.2
- liveins: $scc
%2:vreg_64_align2 = PHI %1, %bb.0, %3, %bb.1
%4:vreg_64_align2 = PHI %1, %bb.0, %5, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%6:areg_128_align2 = REG_SEQUENCE %2.sub0, %subreg.sub0, %2.sub1, %subreg.sub1, %4.sub0, %subreg.sub2, %4.sub1, %subreg.sub3
%7:vreg_64_align2 = V_MOV_B64_e32 1073741824, implicit $exec
%8:vreg_64_align2 = V_MOV_B64_e32 1065353216, implicit $exec
@@ -194,7 +197,7 @@ body: |
; GFX908-LABEL: name: test_sgpr_init_singleuse
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -208,7 +211,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
@@ -218,6 +220,7 @@ body: |
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -230,7 +233,7 @@ body: |
; GFX90A-LABEL: name: test_sgpr_init_singleuse
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
@@ -244,7 +247,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY2]], %bb.0, %16.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %16.sub1, %bb.1
@@ -254,6 +256,7 @@ body: |
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY9]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -263,7 +266,7 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%0:sgpr_32 = COPY $sgpr0
@@ -273,13 +276,15 @@ body: |
%4:vgpr_32 = COPY %0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %1, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %2, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %3, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %4, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -302,7 +307,7 @@ body: |
; GFX908-LABEL: name: test_vgpr_init
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $scc
+ ; GFX908-NEXT: liveins: $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -312,7 +317,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -322,6 +326,7 @@ body: |
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -334,7 +339,7 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -344,7 +349,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -354,6 +358,7 @@ body: |
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -363,19 +368,21 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %0, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -398,7 +405,7 @@ body: |
; GFX908-LABEL: name: test_use_vgpr_temp
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $sgpr0, $scc
+ ; GFX908-NEXT: liveins: $sgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
@@ -412,7 +419,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %18.sub1, %bb.1
@@ -422,6 +428,7 @@ body: |
; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -434,7 +441,7 @@ body: |
; GFX90A-LABEL: name: test_use_vgpr_temp
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr0, $scc
+ ; GFX90A-NEXT: liveins: $sgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
@@ -446,7 +453,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[REG_SEQUENCE]].sub0, %bb.0, %18.sub1, %bb.1
@@ -456,6 +462,7 @@ body: |
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY2]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -465,7 +472,7 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $sgpr0, $scc
+ liveins: $sgpr0
successors: %bb.1
%1:vgpr_32 = COPY $sgpr0
@@ -476,13 +483,15 @@ body: |
%6:areg_128_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1, %4, %subreg.sub2, %5, %subreg.sub3
%7:vgpr_32 = COPY %6.sub0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %7, %bb.0, %16, %bb.1
%9:vgpr_32 = PHI %7, %bb.0, %17, %bb.1
%10:vgpr_32 = PHI %7, %bb.0, %18, %bb.1
%11:vgpr_32 = PHI %7, %bb.0, %19, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -504,7 +513,7 @@ body: |
; GFX908-LABEL: name: test_vgpr_init_two_copies
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $scc
+ ; GFX908-NEXT: liveins: $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -514,7 +523,6 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -524,6 +532,7 @@ body: |
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -536,7 +545,7 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init_two_copies
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[COPY]]
@@ -546,7 +555,6 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.0, %12.sub0, %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.0, %12.sub1, %bb.1
@@ -556,6 +564,7 @@ body: |
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI1]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -565,19 +574,22 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
+
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%8:vgpr_32 = PHI %0, %bb.0, %17, %bb.1
%9:vgpr_32 = PHI %0, %bb.0, %18, %bb.1
%10:vgpr_32 = PHI %0, %bb.0, %19, %bb.1
%11:vgpr_32 = PHI %0, %bb.0, %20, %bb.1
+
+ $scc = IMPLICIT_DEF
+
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -601,14 +613,13 @@ body: |
; GFX908-LABEL: name: test_vgpr_init_skip_phis_insertpt
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $vgpr0, $vgpr1, $scc
+ ; GFX908-NEXT: liveins: $vgpr0, $vgpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GFX908-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
@@ -616,11 +627,11 @@ body: |
; GFX908-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX908-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX908-NEXT: [[COPY5:%[0-9]+]]:agpr_32 = COPY [[PHI]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.2:
; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.1, %15.sub0, %bb.2
; GFX908-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.1, %15.sub1, %bb.2
@@ -630,6 +641,7 @@ body: |
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI4]]
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX908-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -642,14 +654,13 @@ body: |
; GFX90A-LABEL: name: test_vgpr_init_skip_phis_insertpt
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $scc
+ ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
@@ -657,11 +668,11 @@ body: |
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX90A-NEXT: [[COPY4:%[0-9]+]]:agpr_32 = COPY [[PHI]]
; GFX90A-NEXT: [[COPY5:%[0-9]+]]:agpr_32 = COPY [[PHI]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI2:%[0-9]+]]:agpr_32 = PHI [[COPY5]], %bb.1, %15.sub0, %bb.2
; GFX90A-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY4]], %bb.1, %15.sub1, %bb.2
@@ -671,6 +682,7 @@ body: |
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[PHI4]]
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[PHI3]]
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[PHI2]]
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY8]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY6]], %subreg.sub3
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -680,27 +692,28 @@ body: |
; GFX90A-NEXT: bb.3:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $vgpr0, $vgpr1, $scc
+ liveins: $vgpr0, $vgpr1
successors: %bb.1
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr0
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%6:vgpr_32 = PHI %0, %bb.0, %1, %bb.1
%7:vgpr_32 = PHI %0, %bb.0, %1, %bb.1
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.1, implicit $scc
bb.2:
- liveins: $scc
successors: %bb.2, %bb.3
%8:vgpr_32 = PHI %6, %bb.1, %16, %bb.2
%9:vgpr_32 = PHI %6, %bb.1, %17, %bb.2
%10:vgpr_32 = PHI %6, %bb.1, %18, %bb.2
%11:vgpr_32 = PHI %6, %bb.1, %19, %bb.2
+
+ $scc = IMPLICIT_DEF
%12:areg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1, %10, %subreg.sub2, %11, %subreg.sub3
%13:vgpr_32 = V_MOV_B32_e32 1073741824, implicit $exec
%14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
@@ -722,8 +735,8 @@ body: |
; GFX908-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; GFX908-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
@@ -734,9 +747,9 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX908-NEXT: liveins: $scc
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
+ ; GFX908-NEXT: $scc = IMPLICIT_DEF
; GFX908-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
@@ -747,8 +760,8 @@ body: |
; GFX90A-LABEL: name: skip_optimize_agpr_phi_without_subreg_use
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
@@ -759,9 +772,9 @@ body: |
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.1:
; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GFX90A-NEXT: liveins: $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[PHI:%[0-9]+]]:areg_128_align2 = PHI [[REG_SEQUENCE]], %bb.0, %7, %bb.1
+ ; GFX90A-NEXT: $scc = IMPLICIT_DEF
; GFX90A-NEXT: [[V_MFMA_F32_16X16X4F32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], [[PHI]], 0, 0, 0, implicit $mode, implicit $exec
; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[V_MFMA_F32_16X16X4F32_e64_]], implicit $exec
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
@@ -769,9 +782,9 @@ body: |
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: S_ENDPGM 0
bb.0:
- liveins: $scc
successors: %bb.1
+ $scc = IMPLICIT_DEF
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%1:sgpr_32 = S_MOV_B32 0
%2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
@@ -780,10 +793,10 @@ body: |
%5:areg_128_align2 = COPY %3, implicit $exec
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%9:areg_128_align2 = PHI %5, %bb.0, %10, %bb.1
+ $scc = IMPLICIT_DEF
%11:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 %0:vgpr_32, %0:vgpr_32, %9:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
%12:vgpr_32 = COPY %11.sub3
%13:vgpr_32 = COPY %11.sub2
@@ -805,9 +818,9 @@ name: phi_output_reg_type_is_vgpr
tracksRegLiveness: true
body: |
bb.0:
- liveins: $scc
successors: %bb.1
+ $scc = IMPLICIT_DEF
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%1:sgpr_32 = S_MOV_B32 0
%2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
@@ -816,10 +829,11 @@ body: |
%5:areg_128_align2 = COPY %3, implicit $exec
bb.1:
- liveins: $scc
successors: %bb.1, %bb.2
%9:areg_128_align2 = PHI %5, %bb.0, %10, %bb.1
+ $scc = IMPLICIT_DEF
+
%11:areg_128_align2 = V_MFMA_F32_16X16X4F32_e64 %0:vgpr_32, %0:vgpr_32, %9:areg_128_align2, 0, 0, 0, implicit $mode, implicit $exec
%12:vgpr_32 = COPY %11.sub3
%13:vgpr_32 = COPY %11.sub2
diff --git a/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir b/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
index b5c9319f809c0..3ab05b403432e 100644
--- a/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="require<machine-loops>,si-late-branch-lowering,print<machine-loops>" -debug-pass-manager -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="phi-node-elimination,require<machine-loops>,si-late-branch-lowering,print<machine-loops>" -debug-pass-manager -filetype=null %s 2>&1 | FileCheck %s
# Test that MachineLoopInfo is preserved when splitting a block inside a loop
# due to early termination handling.
@@ -24,6 +24,7 @@ body: |
bb.1:
liveins: $vgpr0
successors: %bb.1, %bb.2
+ $scc = IMPLICIT_DEF
S_CMP_LG_U32 0, 1, implicit-def $scc
SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
$vgpr1 = V_MOV_B32_e32 1, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir b/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
index 039b6f9041129..aed4da55c1f2e 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-LABEL: name: lower-wwm-copies
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr0, $scc
+ ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $sgpr0 = IMPLICIT_DEF
; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc
@@ -32,7 +32,7 @@ body: |
; CHECK-NEXT: $vgpr2 = COPY $vgpr1
; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr2_sgpr3
bb.0:
- liveins: $vgpr0, $scc
+ liveins: $vgpr0
$sgpr0 = IMPLICIT_DEF
S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc
$vgpr1 = WWM_COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
index 84f1d4e150d65..ad1e07c1663da 100644
--- a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass si-insert-waitcnts -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=si-insert-waitcnts -o - %s | FileCheck -check-prefix=GCN %s
---
name: vmem_scratch_load
@@ -954,9 +954,10 @@ body: |
; GCN-LABEL: name: wait_kmcnt_with_outstanding_vmem_2
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -973,8 +974,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -994,9 +996,10 @@ body: |
; GCN-LABEL: name: wait_kmcnt_and_wait_loadcnt
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1013,8 +1016,9 @@ body: |
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1034,9 +1038,10 @@ body: |
; GCN-LABEL: name: implicit_handling_of_pending_vmem_group
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1055,8 +1060,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1078,10 +1084,11 @@ body: |
; GCN-LABEL: name: mixed_pending_events
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
- ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
+ ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000)
@@ -1100,8 +1107,9 @@ body: |
; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $sgpr2
@@ -1123,9 +1131,10 @@ body: |
; GCN-LABEL: name: pending_vmem_event_between_block
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1146,8 +1155,9 @@ body: |
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr2
@@ -1170,9 +1180,10 @@ body: |
; GCN-LABEL: name: flushing_vmem_cnt_on_block_entry
; GCN: bb.0:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ ; GCN-NEXT: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ ; GCN-NEXT: $scc = IMPLICIT_DEF
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -1190,8 +1201,9 @@ body: |
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0_sgpr1, $scc
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
+ $scc = IMPLICIT_DEF
S_CBRANCH_SCC1 %bb.2, implicit $scc
bb.1:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr2
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