[llvm] [AMDGPU] Add a sched group mask for LDSDMA instructions (PR #190872)

[Shilei Tian via llvm-commits]

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@@ -1605,6 +1605,7 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    - 0x0100: All DS read instructions may be scheduled across sched_barrier.
                                                    - 0x0200: All DS write instructions may be scheduled across sched_barrier.
                                                    - 0x0400: All Transcendental (e.g. V_EXP) instructions may be scheduled across sched_barrier.
+                                                   - 0x0800: All LDSDMA instructions may be scheduled across sched_barrier.
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shiltian wrote:

¯\_(ツ)_/¯

https://github.com/llvm/llvm-project/pull/190872