[llvm] [llvm][RISCV] Split LMUL=8 fixed vector fcmp for zvfhmin and zvfbfmin (PR #193424)

[Brandon Wu via llvm-commits]

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@@ -1683,9 +1683,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
           MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
           // Don't promote f16 vector operations to f32 if f32 vector type is
           // not legal.
-          // TODO: could split the f16 vector into two vectors and do promotion.
-          if (!isTypeLegal(F32VecVT))
+          // For LMUL=8, custom lower them so we can split to 2 LMUL=4
+          // operations to be able to lower them.
+          // TODO: Support more operations.
+          if (!isTypeLegal(F32VecVT)) {
+            if (getLMUL(getContainerForFixedLengthVector(VT)) ==
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4vtomat wrote:

Oops I think we don't need 

https://github.com/llvm/llvm-project/pull/193424