[llvm] [RISCV] Expand vp.inttoptr, vp.ptrtoint (PR #193530)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 22 09:26:14 PDT 2026
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/193530
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 2 intrinsics from #179622. There are no corresponding ISD nodes, they are converted into the appropriate integer casts in SelectionDAGBuilder
>From e6138ce576396a4170751db7c23b3e2f34de08ac Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 22 Apr 2026 17:24:08 +0100
Subject: [PATCH] [RISCV] Expand vp.inttoptr, vp.ptrtoint
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 2 intrinsics from #179622. There are no corresponding ISD nodes, they are converted into the appropriate integer casts in SelectionDAGBuilder
---
.../Target/RISCV/RISCVTargetTransformInfo.h | 2 --
.../rvv/fixed-vectors-inttoptr-ptrtoint.ll | 8 ++---
.../CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll | 30 +++++++++----------
3 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index f55e869cfd092..a386231c46de9 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -385,7 +385,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_fshr,
Intrinsic::vp_gather,
Intrinsic::vp_icmp,
- Intrinsic::vp_inttoptr,
Intrinsic::vp_is_fpclass,
Intrinsic::vp_load,
Intrinsic::vp_load_ff,
@@ -393,7 +392,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_merge,
Intrinsic::vp_mul,
Intrinsic::vp_or,
- Intrinsic::vp_ptrtoint,
Intrinsic::vp_reduce_add,
Intrinsic::vp_reduce_and,
Intrinsic::vp_reduce_fadd,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
index 0abad3bf1c56c..a3caf95e26ebf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
@@ -4,9 +4,9 @@
define <4 x ptr> @inttoptr_v4p0_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: inttoptr_v4p0_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vzext.vf2 v8, v10, v0.t
+; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%v = call <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
ret <4 x ptr> %v
@@ -23,8 +23,8 @@ define <4 x ptr> @inttoptr_v4p0_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
define <4 x i32> @ptrtoint_v4i32_v4p0(<4 x ptr> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: ptrtoint_v4i32_v4p0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.ptrtoint.v4i32.v4p0(<4 x ptr> %va, <4 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll b/llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
index 4f4db95f058a3..d9a827aa617b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
@@ -4,9 +4,9 @@
define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: inttoptr_nxv4p0_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vzext.vf8 v8, v12, v0.t
+; CHECK-NEXT: vzext.vf8 v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x ptr> %v
@@ -15,9 +15,9 @@ define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i8(<vscale x 4 x i8> %va, <vscale
define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: inttoptr_nxv4p0_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vmv1r.v v12, v8
-; CHECK-NEXT: vzext.vf4 v8, v12, v0.t
+; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x ptr> %v
@@ -26,9 +26,9 @@ define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i16(<vscale x 4 x i16> %va, <vsca
define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: inttoptr_nxv4p0_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vzext.vf2 v8, v12, v0.t
+; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x ptr> %v
@@ -45,12 +45,12 @@ define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i64(<vscale x 4 x i64> %va, <vsca
define <vscale x 4 x i8> @ptrtoint_nxv4i8_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: ptrtoint_nxv4i8_nxv4p0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ptrtoint.nxv4i8.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -59,10 +59,10 @@ define <vscale x 4 x i8> @ptrtoint_nxv4i8_nxv4p0(<vscale x 4 x ptr> %va, <vscale
define <vscale x 4 x i16> @ptrtoint_nxv4i16_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: ptrtoint_nxv4i16_nxv4p0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ptrtoint.nxv4i16.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -71,8 +71,8 @@ define <vscale x 4 x i16> @ptrtoint_nxv4i16_nxv4p0(<vscale x 4 x ptr> %va, <vsca
define <vscale x 4 x i32> @ptrtoint_nxv4i32_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: ptrtoint_nxv4i32_nxv4p0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ptrtoint.nxv4i32.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)
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