[llvm] [AMDGPU] Break v2i32 and/or/xor ops into i32 pairs when followed by t… (PR #191422)

[Matt Arsenault via llvm-commits]

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@@ -13956,6 +13956,57 @@ static uint32_t getPermuteMask(SDValue V) {
   return ~0;
 }
 
+static SDValue performAndOrXorv2i32Combine(SDNode *N, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+  const unsigned Opc = N->getOpcode();
+  assert(VT == MVT::v2i32);
+  if (!N->isDivergent())
+    return SDValue();
+
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+
+  // Reject v2i32 ops that would be handled by v2i32-v2i32 patterns
+  auto matchV2I32Patterns = [](const unsigned Opc,
+                               const unsigned userOpc) -> bool {
+    return (Opc == ISD::AND || Opc == ISD::OR) && userOpc == ISD::OR;
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arsenm wrote:

These opcodes are implied by the contexts you call performAndOrXorv2i32Combine from?

https://github.com/llvm/llvm-project/pull/191422