[llvm] [AMDGPU] implement no-sdwa prediction in td and support globalisel (PR #193518)

[via llvm-commits]

https://github.com/xiongzile created https://github.com/llvm/llvm-project/pull/193518

Fixes: https://github.com/llvm/llvm-project/issues/193202

>From cc95df22dca0d3be2356625f1386f55a202b79b3 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Wed, 22 Apr 2026 20:41:21 +0800
Subject: [PATCH] [AMDGPU] implement no-sdwa prediction in td

---
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 20 ----------------
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td  | 24 +++++++++++++++++++
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index c2322bd922f31..598ab6f7354f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -897,26 +897,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
   SelectCode(N);
 }
 
-bool AMDGPUDAGToDAGISel::isSDWAOperand(const SDNode *N) const {
-  if (!Subtarget->hasSDWA())
-    return false;
-
-  if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
-    EVT VT = cast<VTSDNode>(N->getOperand(1))->getVT();
-    return VT.getScalarSizeInBits() == 8 || VT.getScalarSizeInBits() == 16;
-  }
-
-  if (N->getOpcode() == ISD::AND)
-    if (auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1)))
-      return RHS->getZExtValue() == 0xFF || RHS->getZExtValue() == 0xFFFF;
-
-  if (N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL)
-    if (auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1)))
-      return (RHS->getZExtValue() % 8) == 0;
-
-  return false;
-}
-
 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
   const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
   const Instruction *Term = BB->getTerminator();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 529b2990f9b3a..24471d73fa0a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -230,6 +230,30 @@ class BinOp_no_sdwa<SDPatternOperator binop> : PatFrag<
   (ops node:$lhs, node:$rhs),
   (binop node:$lhs, node:$rhs),
   [{
+    auto isSDWAOperand = [&](const SDNode *N) -> bool {
+      if (!Subtarget->hasSDWA())
+        return false;
+
+      if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+        EVT VT = cast<VTSDNode>(N->getOperand(1))->getVT();
+        return VT.getScalarSizeInBits() == 8 ||
+               VT.getScalarSizeInBits() == 16;
+      }
+
+      if (N->getOpcode() == ISD::AND) {
+        if (const auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+          return RHS->getZExtValue() == 0xFF ||
+                 RHS->getZExtValue() == 0xFFFF;
+      }
+
+      if (N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) {
+        if (const auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+          return (RHS->getZExtValue() % 8) == 0;
+      }
+
+      return false;
+    };
+
     return !isSDWAOperand(Op.getOperand(0).getNode()) &&
            !isSDWAOperand(Op.getOperand(1).getNode());
   }]> {