[llvm] AMDGPU: Set transient stack alignment to 4 (PR #193517)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/193517

Some of the frame index handling code seems to assume
it can preserve values in SCC through an add by using an
add carry, and clearing the low bit of the resultant pointer,
which means an odd SP value could be corrupted. I haven't
found a case where this was meaningful; we always end up
using a 4 byte aligned pointer anyway. Set this just in case.

>From 109749a7214d4246b9192f8e692b0862b92153c4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 22 Apr 2026 14:55:42 +0100
Subject: [PATCH] AMDGPU: Set transient stack alignment to 4

Some of the frame index handling code seems to assume
it can preserve values in SCC through an add by using an
add carry, and clearing the low bit of the resultant pointer,
which means an odd SP value could be corrupted. I haven't
found a case where this was meaningful; we always end up
using a 4 byte aligned pointer anyway. Set this just in case.
---
 llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index c56a746d63000..bbb491a4849b2 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -185,7 +185,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
     InstrItins(getInstrItineraryForCPU(GPU)),
     InstrInfo(initializeSubtargetDependencies(TT, GPU, FS)),
     TLInfo(TM, *this),
-    FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0) {
+    FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0,
+                  /*TransAl=*/Align(4)) {
   // clang-format on
   MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
   EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(this);