[llvm] 93419bf - [AArch64][ISel] Use TripleOpVT in LowerVECTOR_INTERLEAVE (#193506)

[via llvm-commits]

Author: Matthew Devereau
Date: 2026-04-22T16:05:26+01:00
New Revision: 93419bf99ede00317b8aa02064d71dc74280bf7a

URL: https://github.com/llvm/llvm-project/commit/93419bf99ede00317b8aa02064d71dc74280bf7a
DIFF: https://github.com/llvm/llvm-project/commit/93419bf99ede00317b8aa02064d71dc74280bf7a.diff

LOG: [AArch64][ISel] Use TripleOpVT in LowerVECTOR_INTERLEAVE (#193506)

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index afe984bf93be3..0ea5b2986e9c0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -32415,8 +32415,11 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
       Ops.push_back(V);
     Ops.push_back(StackPtr);
 
+    EVT TripleOpVT =
+        EVT::getVectorVT(*DAG.getContext(), OpVT.getVectorElementType(),
+                         OpVT.getVectorNumElements() * 3);
     SDValue Chain = DAG.getMemIntrinsicNode(
-        ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops, OpVT,
+        ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops, TripleOpVT,
         MachinePointerInfo(), Alignment, MachineMemOperand::MOStore);
 
     SmallVector<SDValue, 3> Results;