[llvm] [GlobalISel] Combine sext(load), zext(load) patterns when the load has multiple uses (PR #182831)

[Matt Arsenault via llvm-commits]

================
@@ -1063,16 +1068,20 @@ bool CombinerHelper::matchSextInRegOfLoad(
     return false;
 
   Register SrcReg = MI.getOperand(1).getReg();
-  auto *LoadDef = getOpcodeDef<GLoad>(SrcReg, MRI);
-  if (!LoadDef || !MRI.hasOneNonDBGUse(SrcReg))
+  auto *LoadDef = dyn_cast<GLoad>(MRI.getVRegDef(SrcReg));
+  if (!LoadDef)
     return false;
 
   uint64_t MemBits = LoadDef->getMemSizeInBits().getValue();
+  uint64_t ExtFrom = MI.getOperand(2).getImm();
+
+  if (!MRI.hasOneNonDBGUse(SrcReg) && MemBits > ExtFrom)
+    return false;
----------------
arsenm wrote:

```suggestion
  if (MemBits > ExtFrom && !MRI.hasOneNonDBGUse(SrcReg))
    return false;
```

https://github.com/llvm/llvm-project/pull/182831