[llvm] 04f3d43 - [X86][APX] Add assert isReserved if source operand is PhysReg (#192595)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 20 18:49:06 PDT 2026
Author: Phoebe Wang
Date: 2026-04-21T09:49:01+08:00
New Revision: 04f3d43e2175a1658d6550d331ec63420954da50
URL: https://github.com/llvm/llvm-project/commit/04f3d43e2175a1658d6550d331ec63420954da50
DIFF: https://github.com/llvm/llvm-project/commit/04f3d43e2175a1658d6550d331ec63420954da50.diff
LOG: [X86][APX] Add assert isReserved if source operand is PhysReg (#192595)
Added:
llvm/test/CodeGen/X86/apx/foldmemory.mir
Modified:
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LiveRangeEdit.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index ea062282b97b2..a9341a3c3253c 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1110,6 +1110,8 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
if (R.isVirtual()) {
LiveInterval &LI = LIS.getInterval(R);
LIS.shrinkToUses(&LI);
+ } else {
+ assert(MRI.isReserved(R) && "Unexpected PhysReg in source operand!");
}
}
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index edff8c8600188..10b23819c1de0 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -174,6 +174,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
if (R.isVirtual()) {
LiveInterval &SrcLI = LIS.getInterval(R);
LIS.shrinkToUses(&SrcLI);
+ } else {
+ assert(MRI.isReserved(R) && "Unexpected PhysReg in source operand!");
}
}
return true;
diff --git a/llvm/test/CodeGen/X86/apx/foldmemory.mir b/llvm/test/CodeGen/X86/apx/foldmemory.mir
new file mode 100644
index 0000000000000..3cdaf613e9431
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/foldmemory.mir
@@ -0,0 +1,112 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=x86_64-- -run-pass=greedy %s -o - | FileCheck %s
+--- |
+ define fastcc void @fold_with_physical_reg(i64 %arg1) "target-features"="+ndd" {
+ %alloc = alloca i8, i64 %arg1, align 16
+ ret void
+ }
+...
+---
+name: fold_with_physical_reg
+alignment: 1
+tracksRegLiveness: true
+noPhis: true
+isSSA: false
+frameInfo:
+ adjustsStack: true
+ hasCalls: true
+stack:
+ - { id: 0, name: alloc, type: variable-sized, offset: 0, alignment: 1,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ ; CHECK-LABEL: name: fold_with_physical_reg
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $rdi, $rsi, $rdx, $ecx
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY2]], 1, $noreg, 15, $noreg
+ ; CHECK-NEXT: [[AND64ri32_ND:%[0-9]+]]:gr64 = AND64ri32_ND [[LEA64r]], -16, implicit-def dead $eflags
+ ; CHECK-NEXT: MOV64mr %stack.1, 1, $noreg, 0, $noreg, [[AND64ri32_ND]] :: (store (s64) into %stack.1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rsp
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = SUB64rm [[COPY4]], %stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s64) from %stack.1)
+ ; CHECK-NEXT: MOV64mr %stack.2, 1, $noreg, 0, $noreg, [[COPY4]] :: (store (s64) into %stack.2)
+ ; CHECK-NEXT: $rsp = COPY [[COPY4]]
+ ; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: $xmm0 = FsFLD0SS
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY3]]
+ ; CHECK-NEXT: $rdi = COPY [[COPY5]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY [[COPY2]]
+ ; CHECK-NEXT: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr64 = COPY [[COPY1]]
+ ; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; CHECK-NEXT: dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+ ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: CALL64r [[MOV32r0_1]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY5]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY6]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY [[COPY7]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY [[COPY8]]
+ ; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %stack.2)
+ ; CHECK-NEXT: MOV64mi32 [[MOV64rm]], 8, [[MOV32r0_]], 0, $noreg, 0 :: (store (s64))
+ ; CHECK-NEXT: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64))
+ ; CHECK-NEXT: TEST8ri [[COPY]].sub_8bit, 1, implicit-def $eflags
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr64_nosp = COPY [[COPY2]]
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
+ ; CHECK-NEXT: JMP_1 %bb.2
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $rdi, $rsi, $rdx, $ecx
+
+ %5:gr32 = COPY $ecx
+ %4:gr64 = COPY $rdx
+ %3:gr64 = COPY $rsi
+ %2:gr64 = COPY $rdi
+ %8:gr64 = LEA64r %3, 1, $noreg, 15, $noreg
+ %9:gr64 = AND64ri32_ND %8, -16, implicit-def dead $eflags
+ undef %7.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ %0:gr64 = SUB64rr_ND $rsp, %9, implicit-def dead $eflags
+ $rsp = COPY %0
+ ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ undef %16.sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+
+ bb.2:
+ successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+
+ ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ $xmm0 = FsFLD0SS
+ $rdi = COPY %2
+ dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+ CALL64r %7, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
+ ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ MOV64mi32 %0, 8, %16, 0, $noreg, 0 :: (store (s64))
+ MOV64mi32 %4, 1, $noreg, 0, $noreg, 0 :: (store (s64))
+ TEST8ri %5.sub_8bit, 1, implicit-def $eflags
+ %16:gr64_nosp = COPY %3
+ JCC_1 %bb.1, 5, implicit $eflags
+ JMP_1 %bb.2
+...
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