[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Paul Walker via llvm-commits]

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@@ -20942,12 +20942,36 @@ static SDValue performReinterpretCastCombine(SDNode *N) {
   return SDValue();
 }
 
+// and(sext(Op), splat(1)) -> zext(Op)
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paulwalker-arm wrote:

I agree with @rj-jesus that this looks like a target-independent combine. In fact the combine almost already exists.

Looking at `DAGCombiner::visitAND` the combine exists for scalar types and I suspect it'll only take a few minor changes (for example, get `IsAndZeroExtMask` to use `isConstOrConstSplat` inplace of the cast) to extend the logic for vector types.

Note that you'll also need to guard the zext's construction with `!LegalOperations || TLI.isOperationLegal()`. I suspect this was an oversight with the original combine but the vector side is more likely to trip over it given vector zexts are more likely to be illegal.

https://github.com/llvm/llvm-project/pull/192405