[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

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@@ -20942,12 +20942,36 @@ static SDValue performReinterpretCastCombine(SDNode *N) {
   return SDValue();
 }
 
+// and(sext(Op), splat(1)) -> zext(Op)
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sushgokh wrote:

It ensures types have legalized and I can just avoid that i1 check

https://github.com/llvm/llvm-project/pull/192405