[llvm] [LLVM][DAGTypeLegalizer] Maintain scalableness when widening inreg extends. (PR #192482)

[Paul Walker via llvm-commits]

https://github.com/paulwalker-arm created https://github.com/llvm/llvm-project/pull/192482

Fixes https://github.com/llvm/llvm-project/issues/187557

>From 20a0247b3b37247d6ca96fe3261dd3fe58e0c5ad Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Thu, 16 Apr 2026 17:01:21 +0100
Subject: [PATCH] [LLVM][DAGTypeLegalizer] Maintain scalableness when widening
 inreg extends.

---
 llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |  8 ++++----
 llvm/test/CodeGen/AArch64/sve-sext-zext.ll            | 11 +++++++++++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index a96c77bc6a4e9..f3ddb9e4b811e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -6146,10 +6146,10 @@ SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
 
 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
-  EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
-                               cast<VTSDNode>(N->getOperand(1))->getVT()
-                                 .getVectorElementType(),
-                               WidenVT.getVectorNumElements());
+  EVT ExtVT = EVT::getVectorVT(
+      *DAG.getContext(),
+      cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(),
+      WidenVT.getVectorElementCount());
   SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
   return DAG.getNode(N->getOpcode(), SDLoc(N),
                      WidenVT, WidenLHS, DAG.getValueType(ExtVT));
diff --git a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
index 54dd83eaec507..f8713c370515d 100644
--- a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
+++ b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
@@ -612,3 +612,14 @@ define <vscale x 16 x i16> @sext_inreg_i2_to_i16_from_i8(<vscale x 16 x i8> %a)
   %a.sextinreg = sext <vscale x 16 x i2> %a.trunc to <vscale x 16 x i16>
   ret <vscale x 16 x i16> %a.sextinreg
 }
+
+define <vscale x 7 x i16> @widen_sext_inreg_result(<vscale x 7 x i16> %a) {
+; CHECK-LABEL: widen_sext_inreg_result:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %a.trunc = trunc <vscale x 7 x i16> %a to <vscale x 7 x i8>
+  %a.sextinreg = sext <vscale x 7 x i8> %a.trunc to <vscale x 7 x i16>
+  ret <vscale x 7 x i16> %a.sextinreg
+}