[llvm] a81621a - AMDGPU/GlobalISel: RegBankLegalize rules for perm_pk16_b{4,6,8}_u4 (#192368)
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Thu Apr 16 09:03:03 PDT 2026
Author: vangthao95
Date: 2026-04-16T09:02:57-07:00
New Revision: a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
URL: https://github.com/llvm/llvm-project/commit/a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3
DIFF: https://github.com/llvm/llvm-project/commit/a81621a7b14ffd33d1b3fd7b6134a083f51ea1d3.diff
LOG: AMDGPU/GlobalISel: RegBankLegalize rules for perm_pk16_b{4,6,8}_u4 (#192368)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 8bd406764e64c..03b9ea9397650 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1749,6 +1749,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
amdgcn_global_load_async_to_lds_b128})
.Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
+ addRulesForIOpcs({amdgcn_perm_pk16_b4_u4}, StandardB)
+ .Uni(B64, {{UniInVgprB64}, {IntrId, Vgpr32, Vgpr32, VgprV2S32}})
+ .Div(B64, {{VgprB64}, {IntrId, Vgpr32, Vgpr32, VgprV2S32}});
+
+ addRulesForIOpcs({amdgcn_perm_pk16_b6_u4}, StandardB)
+ .Uni(B96, {{UniInVgprB96}, {IntrId, Vgpr32, VgprB64, VgprV2S32}})
+ .Div(B96, {{VgprB96}, {IntrId, Vgpr32, VgprB64, VgprV2S32}});
+
+ addRulesForIOpcs({amdgcn_perm_pk16_b8_u4}, StandardB)
+ .Uni(B128, {{UniInVgprB128}, {IntrId, VgprB64, VgprB64, VgprV2S32}})
+ .Div(B128, {{VgprB128}, {IntrId, VgprB64, VgprB64, VgprV2S32}});
+
addRulesForIOpcs({amdgcn_wwm, amdgcn_strict_wwm, amdgcn_wqm, amdgcn_softwqm,
amdgcn_strict_wqm},
StandardB)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
index 9705843087100..0f6d0dacd06cf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
declare <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32, i32, <2 x i32>)
declare <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32, i64, <2 x i32>)
@@ -64,3 +64,97 @@ define void @test_perm_pk16_b8_u4(i64 %a, i64 %b, <2 x i32> %c, ptr %out) {
store <4 x i32> %ret, ptr %out, align 16
ret void
}
+
+define amdgpu_ps <2 x i32> @test_perm_pk16_b4_u4_sss(i32 inreg %a, i32 inreg %b, <2 x i32> inreg %c) {
+; GFX1250-SDAG-LABEL: test_perm_pk16_b4_u4_sss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_perm_pk16_b4_u4 v[0:1], s0, s1, v[0:1]
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-LABEL: test_perm_pk16_b4_u4_sss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_perm_pk16_b4_u4 v[0:1], s0, s1, v[0:1]
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-GISEL-NEXT: ; return to shader part epilog
+ %ret = tail call <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32 %a, i32 %b, <2 x i32> %c)
+ ret <2 x i32> %ret
+}
+
+define amdgpu_ps <3 x i32> @test_perm_pk16_b6_u4_sss(i32 inreg %a, i64 inreg %b, <2 x i32> inreg %c) {
+; GFX1250-SDAG-LABEL: test_perm_pk16_b6_u4_sss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: s_mov_b32 s7, s2
+; GFX1250-SDAG-NEXT: s_mov_b32 s6, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_perm_pk16_b6_u4 v[0:2], s0, s[6:7], v[0:1]
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-LABEL: test_perm_pk16_b6_u4_sss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s3
+; GFX1250-GISEL-NEXT: s_mov_b32 s7, s4
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s1
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_perm_pk16_b6_u4 v[0:2], s0, s[4:5], v[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: ; return to shader part epilog
+ %ret = tail call <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32 %a, i64 %b, <2 x i32> %c)
+ ret <3 x i32> %ret
+}
+
+define amdgpu_ps <4 x i32> @test_perm_pk16_b8_u4_sss(i64 inreg %a, i64 inreg %b, <2 x i32> inreg %c) {
+; GFX1250-SDAG-LABEL: test_perm_pk16_b8_u4_sss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_perm_pk16_b8_u4 v[0:3], s[0:1], s[2:3], v[0:1]
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-LABEL: test_perm_pk16_b8_u4_sss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_perm_pk16_b8_u4 v[0:3], s[0:1], s[2:3], v[0:1]
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1250-GISEL-NEXT: ; return to shader part epilog
+ %ret = tail call <4 x i32> @llvm.amdgcn.perm.pk16.b8.u4(i64 %a, i64 %b, <2 x i32> %c)
+ ret <4 x i32> %ret
+}
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