[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for split barrier intrinsics (PR #192170)

[via llvm-commits]

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@@ -1528,6 +1516,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_s_sleep_var})
       .Any({{}, {{}, {IntrId, SgprB32_ReadFirstLane}}});
 
+  addRulesForIOpcs({amdgcn_s_barrier_join, amdgcn_s_wakeup_barrier})
+      .Any({{}, {{}, {IntrId, SgprB32_M0}}});
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vangthao95 wrote:

I would say SgprB32_M0 is the more proper solution. If somehow input was divergent then compiler would crash due to not being able to handle vgpr input. SgprB32_M0 handles this by forcing input to be in sgpr with readfirstlane even if the input may be invalid.

https://github.com/llvm/llvm-project/pull/192170